CN113156387A

CN113156387A - Radar target simulation assembly and radar detection method

Info

Publication number: CN113156387A
Application number: CN202110471271.5A
Authority: CN
Inventors: 陈利群; 韩斐; 张玉霞
Original assignee: Beijing Institute of Radio Measurement
Current assignee: Beijing Institute of Radio Measurement
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2021-07-23
Anticipated expiration: 2041-04-29
Also published as: CN113156387B

Abstract

One embodiment of the invention discloses a radar target simulation assembly and a radar inspection method, wherein the assembly comprises: the device comprises an analog-to-digital converter, a controller, an FPGA, M groups of DDR4 memories and M digital-to-analog converters; the analog-to-digital converter is used for sampling an input radar intermediate frequency signal, performing analog-to-digital conversion on the sampled radar intermediate frequency signal and then transmitting the analog-to-digital converted radar intermediate frequency signal to the FPGA; the controller is used for providing parameters for the FPGA; the FPGA is used for processing the received radar intermediate frequency signals to generate M target echo signals and respectively transmitting the M target echo signals to the M digital-to-analog converters; the M groups of DDR4 memories are connected with the FPGA and used for storing radar effective signals generated in the process that the FPGA processes the radar intermediate-frequency signals; and the M digital-to-analog converters are used for performing digital-to-analog conversion on the received target echo signals and then sending the target echo signals to the radar.

Description

Radar target simulation assembly and radar detection method

Technical Field

The invention relates to the technical field of radars, in particular to a radar target simulation assembly and a radar inspection method.

Background

In the development process of the current radar technology, the requirements on the broadband direct acquisition and broadband playback technology are higher and higher, and the simulation task of a simulator for simulating a plurality of targets is difficult to complete by the conventional radar target simulation component.

Disclosure of Invention

The invention aims to provide a radar target simulation component and a radar detection method, a plurality of targets can be simulated through the component to generate target echo signals, meanwhile, an FPGA in the component can select the signal processing frequency in the FPGA according to requirements, and therefore the purposes of saving resources or reducing data processing difficulty are achieved.

In order to achieve the purpose, the invention adopts the following technical scheme:

one aspect of the invention provides a radar target simulation assembly, the assembly comprising:

the device comprises an analog-to-digital converter, a controller, an FPGA, M groups of DDR4 memories and M digital-to-analog converters;

the analog-to-digital converter is used for sampling an input radar intermediate frequency signal, performing analog-to-digital conversion on the sampled radar intermediate frequency signal and then transmitting the analog-to-digital converted radar intermediate frequency signal to the FPGA;

the controller is used for providing parameters for the FPGA;

the FPGA is used for processing the received radar intermediate frequency signals to generate M target echo signals and respectively transmitting the M target echo signals to the M digital-to-analog converters;

the M groups of DDR4 memories are connected with the FPGA and used for storing radar effective signals generated in the process that the FPGA processes the radar intermediate-frequency signals;

the M digital-to-analog converters are used for performing digital-to-analog conversion on the received target echo signals and then sending the target echo signals to the radar;

wherein M is a natural number of 1 or more.

In one specific embodiment, the signal processing frequency at the hardware interface of the FPGA is 300MHz, the signal processing frequency of each group of DDR4 memories is 250MHz, and the signal processing frequency inside the FPGA is 150 MHz.

In a specific embodiment, the signal processing frequency at the hardware interface of the FPGA and the signal processing frequency inside the FPGA are both 300MHz, and the signal processing frequency of each group of DDR4 memories is 250 MHz.

In one particular embodiment, each set of DDR4 memory includes ten DDR4 in parallel.

In another aspect, the invention provides a method of radar inspection according to the above assembly, the method comprising:

s10: the analog-to-digital converter samples the input radar intermediate frequency signal, performs analog-to-digital conversion on the sampled radar intermediate frequency signal and then transmits the signal to the FPGA;

s12: the FPGA carries out down-conversion and multi-phase filtering on the received radar intermediate frequency signal to obtain baseband data of the radar intermediate frequency signal;

s14: the FPGA divides the baseband data into the same M paths;

s16: the FPGA carries out denoising and detection on the baseband data in each path to obtain a radar effective signal, and stores the radar effective signal into a corresponding DDR4 memory;

s18: the FPGA reads the radar effective signals in each group of DDR4 memories at the same time or different times according to the parameters provided by the controller to generate a plurality of targets in each path;

s20: the FPGA respectively adds the targets generated in each path to obtain M target signals, and if the peak value of the target signal is greater than the digit of a digital-to-analog converter, the peak value of the target signal is cut off according to the digit of the digital-to-analog converter; if the peak value of the target signal is smaller than the digit of the digital-to-analog converter, modulating the peak value of the target signal according to the digit of the digital-to-analog converter;

s22: the FPGA carries out Doppler frequency modulation on the modulated or cut target signal in each path according to the parameters provided by the controller;

s24: the FPGA carries out filtering, quadrature modulation and up-conversion on the target signal subjected to Doppler frequency modulation in each path to obtain a corresponding target echo signal;

s26: the FPGA transmits the target echo signal to a corresponding digital-to-analog converter;

s28: the digital-to-analog converter performs digital-to-analog conversion on the received target echo signal and then sends the target echo signal to the radar;

s30: the radar processes the received target echo signal to obtain target echo data, the target echo data is compared with correct target echo data obtained in a radar verification system, if the target echo data is the same as the correct target echo data, the radar works normally, and if the target echo data is different from the correct target echo data, the radar works abnormally;

wherein M is a natural number of 1 or more.

In a specific embodiment, the method further comprises:

s13: the FPGA extracts the baseband data and reduces the frequency of the baseband data;

s23: and the FPGA interpolates the target signals after Doppler frequency modulation in each path, and restores the frequency of the target signals after Doppler frequency modulation to the frequency of the baseband data.

The invention has the following beneficial effects:

the radar target simulation assembly provided by the invention can simulate a plurality of targets to generate target echo signals, and meanwhile, the FPGA in the assembly can select the internal signal processing frequency of the FPGA according to the requirement, so that the aim of saving resources or reducing the data processing difficulty is fulfilled; the radar detection method provided by the invention can accurately judge whether the radar works normally.

Drawings

In order to more clearly illustrate the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are one embodiment of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 shows a block diagram of a radar target simulation component, according to one embodiment of the invention.

Fig. 2 shows a flow diagram of a radar verification method according to an embodiment of the invention.

Detailed Description

In order to make the technical solution of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The present invention will be described in detail with reference to specific examples, but the present invention is not limited to these examples. Variations and modifications may be made by those skilled in the art without departing from the principles of the invention and should be considered within the scope of the invention.

In one aspect, the present embodiment provides a radar target simulation module, as shown in fig. 1, the module includes:

the controller is used for providing parameters for the FPGA; the parameters include: the number and the time of the targets generated by the FPGA, the frequency parameters required by the FPGA for Doppler frequency modulation and the like.

m is a natural number greater than or equal to 1, in this embodiment, M is 1, fig. 1 also only shows 1 group of DDR4 memories and 1 digital-to-analog converter, and each group of DDR4 memories includes ten parallel DDR 4.

In another aspect, this embodiment provides a method for radar verification using the radar target simulation module, as shown in fig. 2, where the method includes:

in this embodiment, the bandwidth of the radar intermediate frequency signal is 2GHz, and the center frequency is 1.2 ± 1 GHz; the sampling frequency of the analog-to-digital converter is 4.8GHz, and the bit width is 12 bits.

s13: the FPGA extracts the baseband data and reduces the frequency of the baseband data; reducing the frequency of the baseband data can save resources, and in this embodiment, the FPGA performs double extraction on the baseband data to obtain the baseband data with a sampling frequency of 2.4 GHz.

S14: the FPGA divides the baseband data into the same M paths;

m is a natural number greater than or equal to 1; the number of the ways corresponds to the number of the DDR4 memories and the number of the digital-to-analog converters, and each way corresponds to a group of DDR4 memories and a digital-to-analog converter.

for example, when 3 targets at the same time need to be generated, the FPGA reads the number 3 of generated targets provided by the controller and the time t of the generated targets, reads the radar valid signal in the DDR4 memory at the time t to generate 3 targets, and the generated targets at the same time are the same.

For example, when it is necessary to generate targets at 4 different times, the FPGA reads the number of generated targets 4 provided by the controller, the time t of generating the targets, and the target time delay Δ t, reads the radar valid signal in the DDR4 memory at the time t to generate a first target, generates second to fourth targets at the time t + Δ t, and generates Δ t of the second to fourth targets according to the requirements, which may be the same or different, for example, the second target is generated at the time t +1, the third target is generated at the time t +2, and the fourth target is generated at the time t +3, or the second to fourth targets may be generated at the time t + 1.

In this embodiment, the FPGA reserves 10 bits during data processing, the DDR4 data bit width is 80 bits, the data is truncated to 10 bits, and the final data output rate is 4.8GHz × 10 bit. To achieve 4-target simulation, the cache speed of the cache module, i.e., each group of DDR4 memories, needs to reach 4.8GHz × 10bit × 6 to 600MHz × 80bit × 6 (simultaneously, 1 group of write operations and 4 groups of read operations are achieved, with at least 1 group of margins). Each DDR4 adopts a low voltage of 1.2V, which can achieve a data throughput speed of 2.4T/s, and the buffer speed of 10 parallel DDR4 can achieve 2400MHz × 2 × 80bit (4800 MHz × 80bit >3600MHz × 80 bit), thereby realizing 4 independent target simulation tasks. Therefore, in this embodiment, a group of DDR4 memories generates 4 targets at most, and when more targets need to be generated, more targets can be generated by changing the value of M, for example, when M is 2, the FPGA divides the baseband data into two identical paths, where one path generates 4 targets, and one path generates 3 targets to obtain 7 targets, and two paths can generate 8 targets at most.

s22: the FPGA carries out Doppler frequency modulation on the modulated or cut target signal in each path according to the parameters provided by the controller; the target signal is subjected to Doppler frequency modulation to achieve the purpose of enabling the target signal to simulate a moving object.

S23: the FPGA interpolates the target signals after Doppler frequency modulation in each path, and restores the frequency of the target signals after Doppler frequency modulation to the frequency of the baseband data;

s24: the FPGA carries out filtering, quadrature modulation and up-conversion on the target signal subjected to Doppler frequency modulation in each path to obtain a corresponding target echo signal; the target echo signal carries target information, and in this embodiment, the bandwidth of the target echo signal is 2GHz, and the center frequency is 1.2 ± 1 GHz.

s30: and the radar processes the received target echo signal to obtain target echo data, compares the target echo data with correct target echo data obtained in the radar verification system, if the target echo data are the same as the correct target echo data, the radar works normally, and if the target echo data are different from the correct target echo data, the radar works abnormally.

In addition, those skilled in the art can understand that the steps S13 and S23 are preferred steps, and the method is also true when the steps S13 and S23 are eliminated.

The present embodiment provides two data flow schemes on the basis of the above components and methods:

the first scheme is as follows: the signal processing frequency (clock) at the FPGA hardware interface is 300MHz, the signal processing frequency (user clock) of the DDR4 memory is 250MHz, and the signal processing frequency (main working clock) inside the FPGA is 150 MHz.

The scheme has the advantages that the data processing part comprises the operations of frequency mixing, filtering, target generation and the like, the main working clock is low, the time sequence reliability is high, and the data processing difficulty is low. The method has the defects that the clock domain is crossed for many times, the data processing function is improper, the cache size is unreasonable to process, the problem of point dropping is easy to occur, and the resource consumption is high.

The FPGA is connected with the analog-to-digital converter and the M digital-to-analog converter through an 8-channel JESD204B interface;

the data flow starts from sampling of the analog-to-digital converter, an IP core of JESD204B is adopted in the FPGA, the output clock of the IP is 300MHz, and the data bit width is 256 bits (the data is a real number of 16 bits multiplied by 16); i.e., 300MHz × 256bit (real);

after entering the FPGA to start signal processing, clock domain conversion is carried out to change the signals into a main working clock with 150MHz and 512bit width of data (the data is a real number 16bit multiplied by 32); i.e., 150MHz × 512bit (real);

when the M groups of DDR4 memories perform data caching or the FPGA reads data from the DDR4 memory, clock domain conversion is performed, the clock domain conversion is changed into a user clock with 250MHz and a data bit with 320 bits; 250MHz by 320bit (complex I or Q);

when the FPGA reads data from the DDR4 memory and processes the data again, the clock domain is changed back to the main working clock of 150 MHz;

when the data stream is interfaced from the FPGA to the M digital-to-analog converter through JESD204B, the clock domain is changed back to 300MHz of the clock at the FPGA hardware interface.

Scheme II: the signal processing frequency (clock) at the FPGA hardware interface and the signal processing frequency (main working clock) inside the FPGA are both 300MHz, and the signal processing frequency (user clock) of the DDR4 memory is 250 MHz;

the scheme has the advantages that cross-clock domains are not needed at the interface of the JESD204B and between signal processing inside the FPGA, and the main working clock is high, so that resources can be saved. The disadvantages are that the main working clock is high, timing problems may occur, and the difficulty of data processing is large.

the clock domain is unchanged after the signal processing is started after the signal enters the FPGA;

when the FPGA reads data from the DDR4 memory and processes the data again, the clock domain is changed back to the main working clock of 300 MHz;

when the data stream is interfaced from the FPGA to the M digital-to-analog converter through the JESD204B, the clock domain is unchanged and is still 300 MHz.

In practical application, a proper scheme can be selected according to requirements, and the purposes of saving resources or reducing data processing difficulty are achieved.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims

1. A radar target simulation assembly, the assembly comprising:

the controller is used for providing parameters for the FPGA;

wherein M is a natural number of 1 or more.

2. The assembly of claim 1, wherein a signal processing frequency at the FPGA hardware interface is 300MHz, a signal processing frequency of each group of DDR4 memories is 250MHz, and a signal processing frequency inside the FPGA is 150 MHz.

3. The assembly of claim 1, wherein the signal processing frequency at the FPGA hardware interface and the FPGA internal signal processing frequency are both 300MHz, and the signal processing frequency for each set of DDR4 memories is 250 MHz.

4. The assembly of claim 1, wherein each group of DDR4 memory comprises ten DDR4 in parallel.

5. A method of radar verification of an assembly according to any one of claims 1 to 4, the method comprising:

s14: the FPGA divides the baseband data into the same M paths;

wherein M is a natural number of 1 or more.

6. The method of claim 5, further comprising: