CN113131873B - Self-adaptive feedforward linearization power amplifier device - Google Patents
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Abstract
The application relates to a self-adaptive feedforward linearization power amplifier device. The device comprises: an adaptive error detection loop based on a simulated minimum average method and an adaptive error cancellation loop based on a simulated minimum average method; the first input end of the self-adaptive error detection loop is connected with the input end of the main power amplifier, the output end of the main power amplifier is respectively connected with the second input end of the self-adaptive error detection loop and the second input end of the self-adaptive error cancellation loop, the output end of the self-adaptive error detection loop is connected with the first input end of the self-adaptive error cancellation loop, the output end of the self-adaptive error cancellation loop outputs signals, the self-adaptive state adjusting function of the feedforward power amplifier is realized by using the self-adaptive error detection loop based on the simulation minimum average method and the self-adaptive error cancellation loop based on the simulation minimum average method, the circuit scheme is simple, and the circuit complexity of the power amplifying device is higher.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a self-adaptive feedforward linearization power amplifier device.
Background
The radio frequency power amplifier is a core component of the wireless transceiver system. Wireless communication applications typically require that the output signal of the power amplifier have less distortion, i.e., that the power amplification system have a high degree of linearity. To improve additional efficiency, the linearity of the rf power amplifier is often poor. Therefore, various power amplification linearization techniques are used in the wireless communication system, and typical linearization techniques include: predistortion techniques, negative feedback techniques, feedforward techniques, etc.
Compared with other linearization techniques, the feedforward technique has better performance. The basic principle of feed-forward linearization power amplifier is summarized as follows: firstly, comparing an undistorted signal input by a power amplifier with an output distorted signal by a proper method, and extracting to obtain a sample of an error signal generated by a main power amplifier; and then, properly adjusting the error signal sample and then mutually canceling the error signal sample and the distortion signal to achieve the effect of eliminating distortion. Therefore, the error signal sample extraction and error signal cancellation are two functional modules at the most core of the feedforward power amplifier, and the accuracy degree of the two functional implementation directly determines the linearity of the feedforward power amplifier.
In general, when the feedforward power amplifier works, the working states of the error sample extraction module and the error signal cancellation module need to be adjusted in real time or periodically, so that the error cancellation effect cannot be influenced by factors such as time, temperature change, component parameter drift, emission signal spectrum change and the like. To achieve this function, the prior art generally uses control methods based on digital adaptive algorithms, which often include relatively complex digital control systems, and introduce auxiliary signals, such as pilot frequencies, so that the power amplifying device has a high circuit complexity.
Disclosure of Invention
In view of the foregoing, it is desirable to provide an adaptive feed-forward linearization power amplifier device capable of reducing the circuit complexity of a power amplification system.
An adaptive feed-forward linearization power amplifier arrangement, the arrangement comprising: an adaptive error detection loop based on a simulated minimum average method and an adaptive error cancellation loop based on a simulated minimum average method;
the first input end of the self-adaptive error detection loop is connected with the input end of the main power amplifier, the output end of the main power amplifier is respectively connected with the second input end of the self-adaptive error detection loop and the second input end of the self-adaptive error cancellation loop, the output end of the self-adaptive error detection loop is connected with the first input end of the self-adaptive error cancellation loop, and the output end of the self-adaptive error cancellation loop outputs signals;
the self-adaptive error detection loop is used for extracting an undistorted signal from the input end of the main power amplifier, extracting a first distorted signal from the output end of the main power amplifier, processing the undistorted signal and the first distorted signal, and outputting an error sample signal to the first input end of the self-adaptive error cancellation loop;
The adaptive error cancellation loop is configured to take the error sample signal and the first distortion signal output by the output end of the main power amplifier as input signals, process the error sample signal and the first distortion signal, and adaptively cancel an error signal component in the first distortion signal and output the resultant.
In one embodiment, the apparatus further comprises: a first delay line;
the first delay line is connected between the output end of the main power amplifier and the second input end of the self-adaptive error cancellation loop.
In one embodiment, the adaptive error detection loop comprises: a first directional coupler, a second directional coupler, a third directional coupler, a first modulator, a first demodulator, and a first loop filter bank;
the input end of the first directional coupler is used as the first input end of the self-adaptive error detection loop, the coupling output end of the first directional coupler is connected with the first input end of the first modulator, the through output end of the first directional coupler is connected with the first input end of the first demodulator, the output end of the first demodulator is connected with the input end of the first loop filter bank, the output end of the first loop filter bank is connected with the second input end of the first modulator, the output end of the first modulator is connected with the first input end of the second directional coupler, the second input end of the second directional coupler is used as the second input end of the self-adaptive error detection loop, the output end of the second directional coupler is connected with the output end of the main power amplifier, the output end of the second directional coupler is connected with the input end of the third directional coupler, the coupling output end of the third directional coupler is connected with the second input end of the first demodulator, and the second input end of the third directional coupler is used as the self-adaptive error detection loop.
In one embodiment, the adaptive error detection loop further comprises: a second delay line;
one end of the second delay line is connected with the through output end of the first directional coupler, and the other end of the second delay line is connected with the first input end of the first demodulator.
In one embodiment, the first modulator is comprised of at least one orthogonal multiplying unit.
In one embodiment, the first demodulator is comprised of at least one orthogonal multiplying unit.
In one embodiment, the adaptive error cancellation loop includes: a second demodulator, a second loop filter bank, a second modulator, a linear power amplifier, a fourth directional coupler, a fifth directional coupler, and a sixth directional coupler;
the input end of the fourth directional coupler is used as the first input end of the adaptive error cancellation loop, the coupling output end of the fourth directional coupler is connected with the first input end of the second modulator, the output end of the second directional coupler is connected with the input end of the linear power amplifier, the output end of the linear power amplifier is connected with the first input end of the fifth directional coupler, the second input end of the fifth directional coupler is used as the second input end of the adaptive error cancellation loop, the output end of the fifth directional coupler is connected with the input end of the sixth directional coupler, the through output end of the sixth directional coupler is used as the output end of the adaptive error cancellation loop, the coupling output end of the sixth directional coupler is connected with the second input end of the second demodulator, the output end of the fourth directional coupler is connected with the first input end of the second demodulator, the output end of the second directional coupler is connected with the second input end of the second loop filter bank, and the output end of the second directional coupler is connected with the second input end of the second modulator.
In one embodiment, the adaptive error cancellation loop further comprises: a fifth delay line;
one end of the fifth delay line is connected with the through output end of the fourth directional coupler, and the other end of the fifth delay line is connected with the first input end of the second demodulator.
In one embodiment, the second modulator is formed by at least one orthogonal multiplying unit.
In one embodiment, the second demodulator is formed by at least one orthogonal multiplying unit.
The self-adaptive feedforward linearization power amplifier device is characterized in that a first input end of a self-adaptive error detection loop is connected with an input end of a main power amplifier, an output end of the main power amplifier is respectively connected with a second input end of the self-adaptive error detection loop and a second input end of a self-adaptive error cancellation loop, an output end of the self-adaptive error detection loop is connected with the first input end of the self-adaptive error cancellation loop, and an output end of the self-adaptive error cancellation loop outputs signals; the self-adaptive error detection loop is used for extracting an undistorted signal from the input end of the main power amplifier, extracting a first distorted signal from the output end of the main power amplifier, processing the undistorted signal and the first distorted signal, and outputting an error sample signal to the first input end of the self-adaptive error cancellation loop; the self-adaptive error cancellation loop is used for taking the error sample signal and the first distortion signal output by the output end of the main power amplifier as input signals, processing the error sample signal and the first distortion signal, and outputting the self-adaptively cancelled error signal component in the first distortion signal.
Drawings
FIG. 1 is a schematic diagram of an adaptive feedforward linearization power amplifier device in an embodiment;
FIG. 2 is a schematic diagram of an adaptive feedforward linearization power amplifier device in another embodiment;
FIG. 3 is a schematic diagram of an adaptive feedforward linearization power amplifier device in another embodiment;
FIG. 4 is a schematic diagram of an adaptive feedforward linearization power amplifier device in another embodiment;
FIG. 5 is a schematic diagram of an adaptive feedforward linearization power amplifier device in another embodiment;
fig. 6 is a schematic structural diagram of an adaptive feedforward linearization power amplifier device in another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In one embodiment, as shown in fig. 1, there is provided an adaptive feedforward linearization power amplifier device, including: an adaptive error detection loop 2 based on a simulation minimum average method and an adaptive error cancellation loop 3 based on a simulation minimum average method; the first input end of the self-adaptive error detection loop 2 is connected with the input end of the main power amplifier 1, the output end of the main power amplifier 1 is respectively connected with the second input end of the self-adaptive error detection loop 2 and the second input end of the self-adaptive error cancellation loop 3, the output end of the self-adaptive error detection loop 2 is connected with the first input end of the self-adaptive error cancellation loop 3, and the output end of the self-adaptive error cancellation loop 3 outputs signals.
The self-adaptive error detection loop 2 is used for extracting an undistorted signal from the input end of the main power amplifier 1, extracting a first distorted signal from the output end of the main power amplifier 1, processing the undistorted signal and the first distorted signal, and outputting an error sample signal to the first input end of the self-adaptive error cancellation loop 3; the adaptive error cancellation loop 3 is configured to take the error sample signal and the first distortion signal output by the output end of the main power amplifier 1 as input signals, process the error sample signal and the first distortion signal, and adaptively cancel the error signal component in the first distortion signal and output the resultant.
The main power amplifier 1 is a radio frequency power amplifier to be linearized, and a radio frequency input signal of the feedforward power amplifier is amplified by the main power amplifier 1, and a nonlinear error signal generated by the main power amplifier 1 is superimposed on a linear signal due to nonlinearity of the main power amplifier 1, so as to obtain a distorted output signal (i.e., a first distortion signal). The adaptive error detection loop 2 is an adaptive feedback loop based on an analog minimum average method, and is used for adaptively extracting an undistorted signal which is not amplified by the main power amplifier 1 at an input port of the main power amplifier 1, and adaptively extracting a first distorted signal which is amplified by the main power amplifier 1 at an output port of the main power amplifier 1, and the adaptive error detection loop 2 compares the undistorted signal with the first distorted signal and adaptively outputs an error sample signal. The self-adaptive error cancellation loop 3 is a self-adaptive feedback loop based on an analog minimum average method, and is used for self-adaptively canceling an error signal in a distortion signal output by the main power amplifier 1, an error sample signal output by the self-adaptive error detection loop 2 and a first distortion signal output by the main power amplifier 1 are used as input signals of the self-adaptive error cancellation loop 3, and after the self-adaptive error cancellation loop 3 processes the error sample signal and the first distortion signal, the self-adaptive error cancellation loop is used for self-adaptively canceling an error signal component in the first distortion signal to obtain a linearized radio frequency output signal. Thereby improving the linearity of the feedforward power amplifier.
As shown in fig. 2, in one embodiment, an adaptive feedforward linearization power amplifier device further includes a first delay line 4; the first delay line 4 is connected between the output end of the main power amplifier 1 and the second input end of the adaptive error cancellation loop 3.
As shown in fig. 3, in one embodiment, the adaptive error detection loop 2 includes: a first directional coupler 27, a second directional coupler 26, a third directional coupler 25, a first modulator 21, a first demodulator 22 and a first loop filter bank 23.
The input end of the first directional coupler 27 is used as the first input end of the adaptive error detection loop 2, the coupling output end of the first directional coupler 27 is connected with the first input end of the first modulator 21, the through output end of the first directional coupler 27 is connected with the first input end of the first demodulator 22, the output end of the first demodulator 22 is connected with the input end of the first loop filter bank 23, the output end of the first loop filter bank 23 is connected with the second input end of the first modulator 21, the output end of the first modulator 21 is connected with the first input end of the second directional coupler 26, the second input end of the second directional coupler 26 is used as the second input end of the adaptive error detection loop 2 and is connected with the output end of the main power amplifier 1, the coupling output end of the second directional coupler 26 is connected with the input end of the third directional coupler 25, and the coupling output end of the third directional coupler 25 is connected with the second input end of the first demodulator 22, and the through output end of the third directional coupler 25 is used as the adaptive error detection loop 2.
In the adaptive error detection loop 2, a plurality of undistorted signals with different delays form a first reference signal vector set, and the first reference signal vector set is subjected to inner product with the conjugate of a complex weight vector in the first modulator 21 to obtain a transformed undistorted signal after amplitude-phase transformation. The transformed undistorted signal and the first distorted signal are mutually canceled to obtain an error sample signal. The conjugate of the first reference signal vector set and the error sample signal is multiplied by a complex signal in the first demodulator 22, and the output complex vector set is low-pass filtered by the first loop filter set 23 to obtain a complex weight vector of the first modulator 21, thereby forming an adaptive cancellation loop based on the analog minimum average method.
As shown in fig. 4, in one embodiment, the adaptive error detection loop 2 further includes: a second delay line 24; one end of the second delay line 24 is connected to the through output of the first directional coupler 27, and the other end of the second delay line 24 is connected to the first input of the first demodulator 22.
In the adaptive error detection loop 2, before the undistorted signal is input into the first demodulator 22, the bandwidth of the stable operation of the first loop filter bank 23 can be increased through a second delay line 24, so that the reliability of the normal operation of the first loop filter bank 23 is improved.
In one embodiment, the first modulator 21 is constituted by at least one orthogonal multiplying unit.
The orthogonal multiplication unit is used for implementing complex signal conjugate multiplication operation in the first modulator 21, and the more the adopted orthogonal multiplication units are, the better the cancellation bandwidth and precision are.
In one embodiment, when the first modulator 21 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit is the first input of the first modulator 21, the output of the quadrature multiplication unit is the output of the first modulator 21, and the second input of the quadrature multiplication unit is the second input of the first modulator 21; when the first modulator 21 is constituted by two or more orthogonal multiplying units, it is connected to other devices in the adaptive error detection loop 2 through a power divider.
Specifically, taking the first modulator 21 as an example constituted by two orthogonal multiplying units, as shown in fig. 4, the first modulator 21 includes: a first power divider 214, a first orthogonal multiplying unit 211, a third delay line 213, a second orthogonal multiplying unit 212, and a second power divider 215.
The combining port of the first power divider 214 is used as a first input end of the first modulator 21, two power dividing ports of the first power divider 214 are respectively connected with a first input end of the first orthogonal multiplying unit 211 and one end of a third delay line 213, the other end of the third delay line 213 is connected with a first input end of the second orthogonal multiplying unit 212, output ends of the first orthogonal multiplying unit 211 and the second orthogonal multiplying unit 212 are respectively connected with two power dividing ports of the second power divider 215, a combining end of the second power divider 215 is used as an output end of the first modulator 21, and a second input end of the first orthogonal multiplying unit 211 and a second orthogonal multiplying unit 212 are used as a second input end of the first modulator 21.
Wherein the first orthogonal multiplying unit 211 includes: a first quadrature coupler 2113, a first multiplication unit 2111, a second multiplication unit 2112, and a first phase-to-power divider 2114; the input end of the first quadrature coupler 2113 is used as the first input end of the first quadrature multiplication unit 211, the in-phase output end of the first quadrature coupler 2113 is connected with the first signal input end of the first multiplication unit 2111, the quadrature output end of the first quadrature coupler 2113 is connected with the first signal input end of the second multiplication unit 2112, the signal output ends of the first multiplication unit 2111 and the second multiplication unit 2112 are respectively connected with two power division ports of the first in-phase power divider 2114, the combining end of the first in-phase power divider 2114 is used as the output end of the first quadrature multiplication unit 211, and the second signal input ends of the first multiplication unit 2111 and the second multiplication unit 2112 are used as the second input end of the first quadrature multiplication unit 211.
The second orthogonal multiplication unit 212 includes: a second quadrature coupler 2123, a third multiplying unit 2121, a fourth multiplying unit 2122, and a second in-phase power divider 2124; the input end of the second quadrature coupler 2123 is used as the first input end of the second quadrature multiplication unit 212, the inphase output end of the second quadrature coupler 2123 is connected with the first signal input end of the third multiplication unit 2121, the quadrature output end of the second quadrature coupler 2123 is connected with the first signal input end of the fourth multiplication unit 2122, the signal output ends of the third multiplication unit 2121 and the fourth multiplication unit 2122 are respectively connected with two power division ports of the second inphase power divider 2124, the combining end of the second inphase power divider 2124 is used as the output end of the second quadrature multiplication unit 212, and the second signal input ends of the third multiplication unit 2121 and the fourth multiplication unit 2122 are used as the second input end of the second quadrature multiplication unit 212.
In one embodiment, the first demodulator 22 is comprised of at least one quadrature multiplication unit.
The orthogonal multiplication unit is used for implementing complex signal conjugate multiplication operation in the first demodulator 22, and the more the adopted orthogonal multiplication units are, the better the cancellation bandwidth and precision are.
In one embodiment, when the first demodulator 22 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit is the first input of the first demodulator 22, the output of the quadrature multiplication unit is the output of the first demodulator 22, and the second input of the quadrature multiplication unit is the second input of the first demodulator 22; when the first demodulator 22 is constituted by two or more orthogonal multiplying units, it is connected to other devices in the adaptive error detection loop 2 through a power divider.
Specifically, taking the first demodulator 22 as an example constituted by two orthogonal multiplying units, as shown in fig. 4, in one embodiment, the first demodulator 22 includes: a third power divider 224, a fourth delay line 223, a third orthogonal multiplying unit 221, a fourth orthogonal multiplying unit 222, and a fourth power divider 225.
The combining end of the third power divider 224 is used as the first input end of the first demodulator 22, two power dividing ports of the third power divider 224 are respectively connected with the first input end of the third orthogonal multiplying unit 221 and one end of the fourth delay line 223, the other end of the fourth delay line 223 is connected with the first input end of the fourth orthogonal multiplying unit 222, the second input ends of the third orthogonal multiplying unit 221 and the fourth orthogonal multiplying unit 222 are respectively connected with two power dividing ports of the fourth power divider 225, the combining end of the fourth power divider 225 is used as the second input end of the first demodulator 22, and the output ends of the third orthogonal multiplying unit 221 and the fourth orthogonal multiplying unit 222 are used as the output ends of the first demodulator 22.
Wherein the third orthogonal multiplying unit 221 includes: a third quadrature coupler 2213, a fifth multiplication unit 2211, a sixth multiplication unit 2212, and a third in-phase power divider 2214; the input end of the third quadrature coupler 2213 is used as the first input end of the third quadrature multiplication unit 221, the in-phase output end of the third quadrature coupler 2213 is connected with the first signal input end of the fifth multiplication unit 2211, the quadrature output end of the third quadrature coupler 2213 is connected with the first signal input end of the sixth multiplication unit 2212, the second signal input ends of the fifth multiplication unit 2211 and the sixth multiplication unit 2212 are respectively connected with two power division ports of the third in-phase power divider 2214, the combining end of the third in-phase power divider 2214 is used as the second input end of the third quadrature multiplication unit 221, and the signal output ends of the fifth multiplication unit 2211 and the sixth multiplication unit 2212 are used as the output end of the third quadrature multiplication unit 221.
The fourth orthogonal multiplying unit 222 includes: the input end of the fourth quadrature coupler 2223 is used as the first input end of the fourth quadrature multiplication unit 222, the in-phase output end of the fourth quadrature coupler 2223 is connected with the first signal input end of the seventh multiplication unit 2221, the quadrature output end of the fourth quadrature coupler 2223 is connected with the first signal input end of the eighth multiplication unit 2222, the second signal input ends of the seventh multiplication unit 2221 and the eighth multiplication unit 2222 are respectively connected with two power division ports of the fourth in-phase power divider 2224, the combined end of the fourth in-phase power divider 2224 is used as the second input end of the fourth quadrature multiplication unit 222, and the signal output ends of the seventh multiplication unit 2221 and the eighth multiplication unit 2222 are used as the output end of the fourth quadrature multiplication unit 222.
Wherein the third delay line 213 and the fourth delay line 223 have the same amount of delay.
In one embodiment, the first loop filter bank 23 is composed of four loop filters, respectively: a first loop filter 231, a second loop filter 232, a third loop filter 233, and a fourth loop filter 234, the signal input terminal of the first loop filter 231 being connected to the signal output terminal of the fifth multiplication unit 2211, the signal output terminal of the first loop filter 231 being connected to the second signal input terminal of the first multiplication unit 2111; the signal input end of the second loop filter 232 is connected to the signal output end of the sixth multiplying unit 2212, and the signal output end of the second loop filter 232 is connected to the second signal input end of the second multiplying unit 2112; a signal input terminal of the third loop filter 233 is connected to a signal output terminal of the seventh multiplying unit 2221, and a signal output terminal of the third loop filter 233 is connected to a second signal input terminal of the third multiplying unit 2121; the signal input terminal of the fourth loop filter 234 is connected to the signal output terminal of the eighth multiplying unit 2222, and the signal output terminal of the fourth loop filter 234 is connected to the second signal input terminal of the third multiplying unit 2121.
As shown in fig. 5, in one embodiment, the adaptive error cancellation loop 3 includes: a second demodulator 32, a second loop filter bank 33, a second modulator 31, a linear power amplifier 34, a fourth directional coupler 38, a fifth directional coupler 36 and a sixth directional coupler 37;
the input of the fourth directional coupler 38 is used as the first input of the adaptive error cancellation loop 3, the coupled output of the fourth directional coupler 38 is connected to the first input of the second modulator 31, the output of the second modulator 31 is connected to the input of the linear power amplifier 34, the output of the linear power amplifier 34 is connected to the first input of the fifth directional coupler 36, the second input of the fifth directional coupler 36 is used as the second input of the adaptive error cancellation loop 3, the output of the fifth directional coupler 36 is connected to the input of the sixth directional coupler 37, the through output of the sixth directional coupler 37 is used as the output of the adaptive error cancellation loop 3, the coupled output of the sixth directional coupler 37 is connected to the second input of the second demodulator 32, the through output of the fourth directional coupler 38 is connected to the first input of the second demodulator 32, the output of the second demodulator 32 is connected to the input of the second loop filter bank 33, and the output of the second loop filter bank 33 is connected to the second input of the second modulator 31.
In the adaptive error cancellation loop 3, a plurality of error sample signals with different delays form a second reference signal vector set, the second reference signal vector set is subjected to inner product with the conjugate of a complex weight vector in the second modulator 31, and amplified by the linear power amplifier 34 to obtain a transformed error signal subjected to amplitude-phase transformation, the transformed error signal and the first distortion signal are mutually cancelled, an error component in the first distortion signal is eliminated, a radio frequency output signal with feedforward power amplification is obtained, the conjugate of the second reference signal vector set and the linear output signal is subjected to complex signal multiplication operation in the second demodulator 32, and the output complex weight vector of the second modulator 31 is obtained after low-pass filtering by the second loop filter set 33, thereby forming an adaptive loop cancellation based on an analog minimum average method.
As shown in fig. 6, in one embodiment, the adaptive error cancellation loop 3 further includes: a fifth delay line 35; one end of the fifth delay line 35 is connected to the through output of the fourth directional coupler 38, and the other end of the fifth delay line 35 is connected to the first input of the second demodulator 32.
In the adaptive error cancellation loop 3, the bandwidth of the stable operation of the second loop filter 33 can be increased through a delay circuit 35 before the error signal is input to the demodulator 32, so as to improve the reliability of the normal operation of the second loop filter 33.
In one embodiment, the second modulator 31 is constituted by at least one orthogonal multiplying unit.
The orthogonal multiplying unit is used for implementing complex signal conjugate multiplication operation in the second modulator 31, and the more the orthogonal multiplying units are adopted, the better the cancellation bandwidth and precision are.
In one embodiment, when the second modulator 31 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit is the first input of the second modulator 31, the output of the quadrature multiplication unit is the output of the second modulator 31, and the second input of the quadrature multiplication unit is the second input of the second modulator 31; when the second modulator 31 is constituted by two or more orthogonal multiplying units, it is connected to other devices in the adaptive error cancellation loop 3 through a power divider.
Specifically, taking the second modulator 31 as an example constituted by two orthogonal multiplying units, as shown in fig. 6, in one embodiment, the second modulator 31 includes: a fifth power divider 314, a sixth delay line 313, a fifth orthogonal multiplying unit 311, a sixth orthogonal multiplying unit 312, and a sixth power divider 315; the combining port of the fifth power divider 314 is used as the first input end of the second modulator 31, the two power dividing ports of the fifth power divider 314 are respectively connected with the first input end of the fifth orthogonal multiplying unit 311 and one end of the sixth delay line 313, the other end of the sixth delay line 313 is connected with the first input end of the sixth orthogonal multiplying unit 312, the output ends of the fifth orthogonal multiplying unit 311 and the sixth orthogonal multiplying unit 312 are respectively connected with the two power dividing ports of the sixth power divider 315, the combining port of the sixth power divider 315 is used as the output end of the second modulator 31, and the second input ends of the fifth orthogonal multiplying unit 311 and the sixth orthogonal multiplying unit 312 are used as the second input end of the second modulator 31.
Wherein the fifth orthogonal multiplying unit 311 includes: a fifth quadrature coupler 3113, a ninth multiplication unit 3111, a tenth multiplication unit 3112, and a fifth in-phase power divider 3114; the input end of the fifth quadrature coupler 3113 is used as the first input end of the fifth quadrature multiplication unit 311, the in-phase output end of the fifth quadrature coupler 3113 is connected to the first signal input end of the ninth quadrature multiplication unit 3111, the quadrature output end of the fifth quadrature coupler 3113 is connected to the first signal input end of the tenth multiplication unit 3112, the signal output ends of the ninth multiplication unit 3111 and the tenth multiplication unit 3112 are respectively connected to the two power division ports of the fifth in-phase power divider 3114, the combining end of the fifth in-phase power divider 3114 is used as the output end of the fifth quadrature multiplication unit 311, and the second signal input ends of the ninth multiplication unit 3111 and the tenth multiplication unit 3112 are used as the second input end of the fifth quadrature multiplication unit 311.
The sixth orthogonal multiplying unit 312 includes: a sixth quadrature coupler 3123, an eleventh multiplication unit 3121, a twelfth multiplication unit 3122, and a sixth in-phase power divider 3124; the input end of the sixth quadrature coupler 3123 is used as the first input end of the sixth quadrature multiplication unit 312, the in-phase output end of the sixth quadrature coupler 3123 is connected with the first signal input end of the eleventh multiplication unit 3121, the quadrature output end of the sixth quadrature coupler 3123 is connected with the first signal input end of the twelfth multiplication unit 3122, the signal output ends of the eleventh multiplication unit 3121 and the twelfth multiplication unit 3122 are respectively connected with two power division ports of the sixth in-phase power divider 3124, the combining end of the sixth in-phase power divider 3124 is used as the output end of the sixth quadrature multiplication unit 312, and the second signal input ends of the eleventh multiplication unit 3121 and the twelfth multiplication unit 3122 are used as the second input end of the sixth quadrature multiplication unit 312.
In one embodiment, the second demodulator 32 is comprised of at least one quadrature multiplication unit.
The orthogonal multiplication unit is used for implementing complex signal conjugate multiplication operation in the second demodulator 32, and the more the adopted orthogonal multiplication units are, the better the cancellation bandwidth and precision are.
In one embodiment, when the second demodulator 32 is formed by a quadrature multiplication unit, the first input of the quadrature multiplication unit is the first input of the second demodulator 32, the output of the quadrature multiplication unit is the output of the second demodulator 32, and the second input of the quadrature multiplication unit is the second input of the second demodulator 32; when the second demodulator 32 is constituted by two or more orthogonal multiplying units, it is connected to other devices in the adaptive error cancellation loop 3 through a power divider.
Specifically, taking the second demodulator 32 as an example constituted by two orthogonal multiplying units, as shown in fig. 6, in one embodiment, the second demodulator 32 includes: seventh power divider 324, seventh delay line 323, seventh orthogonal multiplying unit 321, eighth orthogonal multiplying unit 322, and eighth power divider 325; the combining end of the seventh power divider 324 is used as the first input end of the second demodulator 32, two power dividing ports of the seventh power divider 324 are respectively connected with the first input end of the seventh orthogonal multiplying unit 321 and one end of the seventh delay line 323, the other end of the seventh delay line 323 is connected with the first input end of the eighth orthogonal multiplying unit 322, the second input ends of the seventh orthogonal multiplying unit 321 and the eighth orthogonal multiplying unit 322 are respectively connected with two power dividing ports of the eighth power divider 325, the combining end of the eighth power divider 325 is used as the second input end of the second demodulator 32, and the output ends of the seventh orthogonal multiplying unit 321 and the eighth orthogonal multiplying unit 322 are used as the output ends of the second demodulator 32.
Wherein the seventh orthogonal multiplying unit 321 includes: a seventh quadrature coupler 3213, a thirteenth multiplying unit 3211, a fourteenth multiplying unit 3212, and a seventh in-phase power divider 3214; the input end of the seventh quadrature coupler 3213 is used as the first input end of the seventh quadrature multiplication unit 321, the in-phase output end of the seventh quadrature coupler 3213 is connected with the first signal input end of the thirteenth multiplication unit 3211, the quadrature output end of the seventh quadrature coupler 3212 is connected with the first signal input end of the fourteenth multiplication unit 3212, the second signal input ends of the thirteenth multiplication unit 3211 and the fourteenth multiplication unit 3212 are respectively connected with two power division ports of the seventh in-phase power divider 3214, the combining end of the seventh in-phase power divider 3214 is used as the second input end of the seventh quadrature multiplication unit 321, and the signal output ends of the thirteenth multiplication unit 3211 and the fourteenth multiplication unit 3212 are used as the output ends of the seventh quadrature multiplication unit 321.
The eighth orthogonal multiplying unit 322 includes: an eighth quadrature coupler 3223, a fifteenth multiplying unit 3221, a sixteenth multiplying unit 3222, and an eighth in-phase power divider 3224; the input end of the eighth quadrature coupler 3223 is used as the first signal input end of the eighth quadrature multiplication unit 322, the in-phase output end of the eighth quadrature coupler 3223 is connected with the first signal input end of the fifteenth multiplication unit 3221, the quadrature output end of the eighth quadrature coupler 3223 is connected with the first signal input end of the sixteenth multiplication unit 3222, the second signal input ends of the fifteenth multiplication unit 3221 and the sixteenth multiplication unit 3222 are respectively connected with two power division ports of the eighth in-phase power divider 3224, the combining end of the eighth in-phase power divider 3224 is used as the second signal input end of the eighth quadrature multiplication unit 322, and the signal output ends of the fifteenth multiplication unit 3221 and the sixteenth multiplication unit 3222 are used as the output ends of the eighth quadrature multiplication unit 322.
In one embodiment, the second loop filter bank 33 is composed of four loop filters, respectively: the signal inputs of the fifth loop filter 311, the sixth loop filter 332, the seventh loop filter 333, and the eighth loop filter 334 serve as the inputs of the second loop filter bank 33, and the signal outputs of the fifth loop filter 311, the sixth loop filter 332, the seventh loop filter 333, and the eighth loop filter 334 serve as the outputs of the second loop filter bank 33.
A signal input terminal of the fifth loop filter 331 is connected to a signal output terminal of the thirteenth multiplying unit 3211, and a signal output terminal of the fifth loop filter 331 is connected to a second signal input terminal of the ninth multiplying unit 3111; a signal input terminal of the sixth loop filter 332 is connected to a signal output terminal of the fourteenth multiplying unit 3212, and a signal output terminal of the sixth loop filter 332 is connected to a second signal input terminal of the tenth multiplying unit 3112; a signal input terminal of the seventh loop filter 333 is connected to a signal output terminal of the fifteenth multiplying unit 3221, and a signal output terminal of the seventh loop filter 333 is connected to a second signal input terminal of the eleventh multiplying unit 3121; a signal input terminal of the eighth loop filter 334 is connected to a signal output terminal of the sixteenth multiplying unit 3222, and a signal output terminal of the eighth loop filter 334 is connected to a second signal input terminal of the twelfth multiplying unit 3122.
Wherein the sixth delay line 313 and the seventh delay line 323 have the same delay amount.
The first in-phase power divider 2114, the second in-phase power divider 2124, the third in-phase power divider 2214, the fourth in-phase power divider 2224, the fifth in-phase power divider 3114, the sixth in-phase power divider 3124, the seventh in-phase power divider 3214, and the eighth in-phase power divider 3224 are configured to divide one signal into two signals with equal amplitude and in-phase, and the first quadrature coupler 2113, the second quadrature coupler 2123, the third quadrature coupler 2213, the fourth quadrature coupler 2223, the fifth quadrature coupler 3113, the sixth quadrature coupler 3123, the seventh quadrature coupler 3213, and the eighth quadrature coupler 3223 are configured to divide one signal into two signals with equal amplitude and phase differences of 90 °.
As shown in fig. 4, the signal flow in the adaptive error detection loop 2 is described as follows:
for ease of description, the transmission losses of each power divider and each quadrature coupler are omitted from the analysis below.
The undistorted input reference signal (i.e., undistorted signal) is denoted as r. The undistorted signal r is split into two paths in the first modulator 21, and after different delays, is input to the first orthogonal multiplying unit 211 and the second orthogonal multiplying unit 212, and is denoted as a vector r= [ r ] 1 ，r 2 ]The method comprises the steps of carrying out a first treatment on the surface of the Similarly, the undistorted signal is divided into two paths in the first demodulator 22 after passing through the delay line 24, and is input into the third orthogonal multiplying unit 221 and the fourth orthogonal multiplying unit 222 after passing through different delays, and is denoted as a vector r' = [ r ] 1 ’r 2 ’]The signal output from the first modulator 21 and the first distortion signal cancel each other out, and an error sample signal is obtained and fed back to the first demodulator 22, denoted as e. The error sample signal e is multiplied with the vector r' in a third orthogonal multiplication unit 221 and a fourth orthogonal multiplication unit 222 in the first demodulator 22.
Taking the third orthogonal multiplication unit 221 as an example, r 1 ' after being divided into two paths of orthogonal signals by the third orthogonal coupler 2213, the two paths of orthogonal signals are multiplied by the error sample signal e in the fifth multiplication unit 2211 and the sixth multiplication unit 2212, and after the obtained two product signals take low-pass components, the obtained product signals are actually the real part Re { r) of the conjugate multiplication product of the two complex signals 1 'e' and imaginary part Im { r }, respectively 1 ' e }. The two signals are low-pass filtered by a first loop filter 231 and a second loop filter 232 and then used as complex weights w 1 Is input to a first orthogonal multiplying unit 211 in the first modulator 21. Similarly, two output signals of the fourth orthogonal multiplying unit 222 Number Re { r 2 'e' and imaginary part Im { r }, respectively 2 After low-pass filtering by the third loop filter 233 and the fourth loop filter 234, 'e', as a complex weight w 2 Is input to the second orthogonal multiplying unit 212 in the first modulator 21. Complex weight w 1 And w 2 Composition weight vector w= [ w ] 1 w 2 ]。
In the first orthogonal multiplying unit 211, r 1 After being divided into two orthogonal signals by the first orthogonal coupler 2113, the two orthogonal signals are combined with a complex weight w in the first multiplying unit 2111 and the second multiplying unit 2112 1 The real and imaginary parts of (2) are multiplied respectively, the products are combined by the first in-phase power divider 2114 as an output signal, the transmission loss of the first in-phase power divider 2114 is ignored, and the output signal is r 1 w 1 * . Similarly, the output of the second orthogonal multiplication unit 212 may be denoted as r 2 w 2 * . It follows that the first demodulator 22 implements a function of multiplying the vector r' by the conjugate of the error sample signal e; the first modulator 21 performs the function of inner product of the conjugate of the vector r and the weight vector w, whereby the adaptive error detection loop 2 is an adaptive loop based on an analog minimum average method.
The signal flow in the adaptive error cancellation loop 3 is described as follows:
for ease of description, the transmission losses of each power divider and each quadrature coupler are omitted from the analysis below.
The error sample signal is taken as a reference input signal, denoted r e . Error sample signal r e Is divided into two paths in the second modulator 31, and is input to a fifth orthogonal multiplying unit 311 and a sixth orthogonal multiplying unit 312 after different delays, and is denoted as a vector r e ＝[r e1 ，r e2 ]The method comprises the steps of carrying out a first treatment on the surface of the Similarly, error sample signal r e After passing through the fifth delay line 35, the signal is divided into two paths in the second demodulator 32, and after passing through different delays, the signals are input into a seventh orthogonal multiplying unit 321 and an eighth orthogonal multiplying unit 322, and are marked as a vector r e ’＝[r e1 ’，r e2 ’]. The signal output by the second modulator 31 is amplified by the linear power amplifier 34 and then in the sixth direction with the first distortion signalThe resulting linearized RF output signal, which has been cancelled by the error signal, is fed back to the second demodulator 32 as a linearized RF output signal S lin . Linearized radio frequency output signal S lin Vector r is multiplied by a seventh orthogonal multiplication unit 321 and an eighth orthogonal multiplication unit 322 in the second demodulator 32 e 'multiplication'.
Taking the seventh orthogonal multiplication unit 321 as an example, r e1 ' after being split into two orthogonal signals by the seventh orthogonal coupler 3213, the signal is combined with the linearized radio frequency output signal S in the thirteenth multiplying unit 3211 and the fourteenth multiplying unit 3212 lin After the obtained two product signals are multiplied by each other to obtain a low-pass component, the low-pass component is actually the real part Re { r } of the conjugate multiplication product of the two complex signals e1 ’，S lin * And imaginary part Im { r } e1 ’，S lin * }. The two signals are low-pass filtered by a fifth loop filter 311 and a sixth loop filter 332 and then used as complex weights v 1 Is input to the fifth orthogonal multiplying unit 311 in the second modulator 31. Similarly, two output signals Re { r } of the eighth orthogonal multiplying unit 322 e2 ’，S lin * Sum Im { r } e2 ’，S lin * After passing through the seventh loop filter 333 and the eighth loop filter 334, the low pass filter is used as a complex weight v 2 Is input to a sixth orthogonal multiplying unit 312 in the second modulator 31. Complex weight v 1 And v 2 Composition weight vector v= [ v ] 1 ，v 2 ]。
In fifth orthogonal multiplying unit 311, r e1 After being divided into two orthogonal signals by the fifth orthogonal coupler 3113, the signals are combined with a complex weight v in the ninth multiplying unit 3111 and the tenth multiplying unit 3112 1 The real and imaginary parts of (a) are multiplied, respectively, and the products are combined by the fifth in-phase power divider 3114 as an output signal, which is denoted r, ignoring the transmission loss of the fifth in-phase power divider 3114 e1 v 1 * . Similarly, the output of the sixth orthogonal multiplication unit 312 may be represented as r e2 v 2 * . It follows that the second demodulator 32 implements the vector r e ' AND linearized radio frequency output signal S lin A function of conjugate multiplication of (a); the second modulator 31 implements the vector r e The conjugate with the weight vector v is the function of the inner product, whereby the adaptive error detection loop 2 is an adaptive loop based on the analog minimum average method.
In summary, the application provides a self-adaptive feedforward linearization power amplifier device, which uses a self-adaptive error detection loop based on a simulation minimum average method and a self-adaptive error cancellation loop based on a simulation minimum average method, can perform self-adaptive state adjustment function of a feedforward power amplifier, has a simple circuit scheme, can adaptively adjust the error cancellation state, is not influenced by factors such as environment and main power amplifier parameter drift, and the like, does not introduce auxiliary signals such as pilot frequency, is realized in a mode of a functional full analog circuit, is suitable for linearization amplification of band-pass transmitting signals, is suitable for integration, is suitable for wireless transmitting systems with band-pass signals of various transmitting signals, and has better cancellation bandwidth and precision as the orthogonal multiplication units adopted by modulators and demodulation are more. Therefore, the power amplifier is suitable for realizing broadband and high-linearity power amplification.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (9)
1. An adaptive feed-forward linearization power amplifier device, comprising: an adaptive error detection loop based on a simulated minimum average method and an adaptive error cancellation loop based on a simulated minimum average method;
the first input end of the self-adaptive error detection loop is connected with the input end of the main power amplifier, the output end of the main power amplifier is respectively connected with the second input end of the self-adaptive error detection loop and the second input end of the self-adaptive error cancellation loop, the output end of the self-adaptive error detection loop is connected with the first input end of the self-adaptive error cancellation loop, and the output end of the self-adaptive error cancellation loop outputs signals;
The self-adaptive error detection loop is used for extracting an undistorted signal from the input end of the main power amplifier, extracting a first distorted signal from the output end of the main power amplifier, processing the undistorted signal and the first distorted signal, and outputting an error sample signal to the first input end of the self-adaptive error cancellation loop;
the self-adaptive error cancellation loop is used for taking the error sample signal and the first distortion signal output by the output end of the main power amplifier as input signals, processing the error sample signal and the first distortion signal, and outputting after self-adaptively canceling the error signal component in the first distortion signal;
the adaptive error detection loop includes: a first directional coupler, a second directional coupler, a third directional coupler, a first modulator, a first demodulator, and a first loop filter bank;
the input end of the first directional coupler is used as the first input end of the self-adaptive error detection loop, the coupling output end of the first directional coupler is connected with the first input end of the first modulator, the through output end of the first directional coupler is connected with the first input end of the first demodulator, the output end of the first demodulator is connected with the input end of the first loop filter bank, the output end of the first loop filter bank is connected with the second input end of the first modulator, the output end of the first modulator is connected with the first input end of the second directional coupler, the second input end of the second directional coupler is used as the second input end of the self-adaptive error detection loop, the output end of the second directional coupler is connected with the output end of the main power amplifier, the output end of the second directional coupler is connected with the input end of the third directional coupler, the coupling output end of the third directional coupler is connected with the second input end of the first demodulator, and the second input end of the third directional coupler is used as the self-adaptive error detection loop.
2. The apparatus of claim 1, wherein the apparatus further comprises: a first delay line;
the first delay line is connected between the output end of the main power amplifier and the second input end of the self-adaptive error cancellation loop.
3. The apparatus of claim 1, wherein the adaptive error detection loop further comprises: a second delay line;
one end of the second delay line is connected with the through output end of the first directional coupler, and the other end of the second delay line is connected with the first input end of the first demodulator.
4. The apparatus of claim 1, wherein the first modulator is comprised of at least one orthogonal multiplying unit.
5. The apparatus of claim 1, wherein the first demodulator is comprised of at least one orthogonal multiplying unit.
6. The apparatus of claim 1, wherein the adaptive error cancellation loop comprises: a second demodulator, a second loop filter bank, a second modulator, a linear power amplifier, a fourth directional coupler, a fifth directional coupler, and a sixth directional coupler;
the input end of the fourth directional coupler is used as the first input end of the adaptive error cancellation loop, the coupling output end of the fourth directional coupler is connected with the first input end of the second modulator, the output end of the second directional coupler is connected with the input end of the linear power amplifier, the output end of the linear power amplifier is connected with the first input end of the fifth directional coupler, the second input end of the fifth directional coupler is used as the second input end of the adaptive error cancellation loop, the output end of the fifth directional coupler is connected with the input end of the sixth directional coupler, the through output end of the sixth directional coupler is used as the output end of the adaptive error cancellation loop, the coupling output end of the sixth directional coupler is connected with the second input end of the second demodulator, the output end of the fourth directional coupler is connected with the first input end of the second demodulator, the output end of the second directional coupler is connected with the second input end of the second loop filter bank, and the output end of the second directional coupler is connected with the second input end of the second modulator.
7. The apparatus of claim 6, wherein the adaptive error cancellation loop further comprises: a fifth delay line;
one end of the fifth delay line is connected with the through output end of the fourth directional coupler, and the other end of the fifth delay line is connected with the first input end of the second demodulator.
8. The apparatus of claim 6, wherein the second modulator is comprised of at least one orthogonal multiplying unit.
9. The apparatus of claim 6, wherein the second demodulator is comprised of at least one orthogonal multiplying unit.
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