CN113114262B - Efficient direct function mapping analog-to-digital conversion circuit - Google Patents
Efficient direct function mapping analog-to-digital conversion circuit Download PDFInfo
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- CN113114262B CN113114262B CN202110481335.XA CN202110481335A CN113114262B CN 113114262 B CN113114262 B CN 113114262B CN 202110481335 A CN202110481335 A CN 202110481335A CN 113114262 B CN113114262 B CN 113114262B
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Abstract
The invention discloses a high-efficiency direct function mapping analog-to-digital conversion circuit, which mainly comprises: the circuit comprises a sample hold circuit, a comparator circuit, a DAC circuit and a register circuit. The circuit can generate a reference voltage with a special function shape along with clock variation at one end of a comparator through a logic control circuit by directly integrating an LUT circuit into a globally shared DAC circuit. Some special activation function mapping can be directly completed aiming at the simulation deep learning hardware acceleration network. The method greatly reduces the area of the circuit required for realizing the activation function, accelerates the calculation process and greatly improves the energy efficiency of the whole calculation circuit. Meanwhile, the invention optimizes the structure of the dynamic comparator aiming at the problems of parasitic parameters of the current comparator and greatly reduces the coupling effect between input and output. The invention only needs to modify the digital logic control part of the DAC, and has the characteristics of strong practicability, high energy efficiency, low power consumption, simple realization and the like.
Description
Technical Field
The invention relates to the technical field of analog-to-digital converters, in particular to an efficient direct function mapping analog-to-digital conversion circuit.
Background
Traditional computing systems based on von neumann architectures are limited by difficulties in scaling transistor dimensions and the problem of "memory walls" that have not been able to meet the computational demands of the Artificial Intelligence (AI) era. The memory computing system based on analog computation can provide low-delay and high-efficiency parallel multiply-accumulate operation for AI computation, and has great potential and advantages in accelerating AI computation. Among them, the analog computation framework based on the pulse neural network (SNN) of the pulse communication is expected to reduce the power consumption of computation while realizing artificial intelligence. In the design of each functional module of the special hardware circuit of the SNN, the design of an ADC circuit module plays a key role. The ADC circuit has high energy efficiency and low power consumption, and has good application prospect in the architecture design of a storage and computation integrated circuit such as a pulse neural network (SNN), a Convolutional Neural Network (CNN) and the like.
Referring to fig. 1, a schematic diagram of a simulation-computation-integrated computing system implementing a single-layer deep learning network is shown. Analog computation is a means to achieve efficient multiply-accumulate computation. The general operation flow of the multiply-accumulate calculating unit based on simulation is as follows: the DAC digital-to-analog conversion circuit converts a digital input signal into a corresponding analog voltage, multiplication operation of the input voltage and the weight is realized through the storage circuit unit and converted into current, the current is collected together through a conducting wire to complete accumulation operation, the current-to-voltage conversion circuit converts the obtained accumulated current into accumulated voltage, and finally the analog weighted voltage is converted into a digital signal through the ADC. The digital signal obtained by the analog calculation unit can obtain the final calculation result of the current layer of the neural network only by the digital activation function circuit and is output to the calculation module of the next layer of the neural network.
Referring to the ADC circuit of fig. 2, an ADC circuit with a shared DAC architecture is shown. The structure can support the full parallel multiply-accumulate operation and greatly reduce the area overhead of the whole ADC circuit in the analog computation unit. The working mode of the digital control global shared DAC is to generate an ascending reference voltage signal, then the reference signal is sequentially compared with an analog voltage signal to be converted to generate square wave signals with different widths, and finally the square wave signals are converted into digital signals through a digital counter. When the number of bits of the ADC is high, the mode has large conversion delay, so that the mode is suitable for scenes with low precision and large analog matrix operation scale.
Referring to fig. 3, a diagram of some deep learning activation functions is shown. Common include sigmoid, reLU, leak-ReLU, etc. These activation functions are usually implemented using LUT (look-up table) circuits for flexible implementation. For the circuit shown in fig. 2, the output of the ADC is used as an input to the LUT circuit to implement the activation function. Because of the large area overhead of a single LUT circuit, this approach must reduce the area overhead by multiplexing the modes of the LUT circuit cells, but also greatly increases the computation latency of the overall circuit.
Disclosure of Invention
The invention aims to provide an efficient direct function mapping analog-to-digital conversion circuit, which can reduce the calculation delay of an analog calculation module and has the advantages of strong practicability, high energy efficiency, low power consumption, simple implementation and the like.
The purpose of the invention is realized by the following technical scheme:
an efficient direct function mapping analog-to-digital conversion circuit comprising: the sampling and holding circuit, the comparator circuit, the DAC circuit and the register circuit; wherein:
the DAC circuit is a globally shared circuit structure, which includes: the logic control circuit, the LUT circuit and the DAC capacitor array are connected in sequence; the output end of the DAC capacitor array is connected with the reverse input ends of all the comparator circuits; the logic control circuit generates incremental binary data, and the incremental binary data is converted into control signals of corresponding DAC capacitor arrays through the LUT circuit, so that different reference voltages are generated;
the positive input end of each comparator circuit is independently connected with a sampling and holding circuit, analog voltage signals to be converted output by the sampling and holding circuit are input, and the output end of each comparator circuit is independently connected with a register circuit; when the state of the comparator circuit is changed, the corresponding register circuit stores the binary data output by the logic control circuit to obtain a binary analog-to-digital conversion result.
According to the technical scheme provided by the invention, on one hand, the LUT circuit with the function of the activation function of the deep neural network is integrated into the shared DAC circuit, so that the conversion delay of the activation function circuit is greatly reduced; and on the premise of not losing the calculation parallelism, the realization of the fully parallel neural network activation function can be realized by only using one LUT circuit, and the power consumption and the area of the neural network accelerator are reduced. On the other hand, a logic control circuit in the shared DAC circuit generates a counting signal and directly controls whether the counting signal is input into the register storage unit or not through the output of the comparator, so that the storage scheme of the output signal is simplified, and unnecessary calculation energy consumption is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic diagram of a single-layer deep learning network implemented by a simulation matrix computing system according to the background art of the present invention;
FIG. 2 is a schematic diagram of a prior art shared DAC ADC architecture according to the background of the invention;
FIG. 3 is a schematic diagram of an activation function for deep learning according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an efficient direct function mapping ADC circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a comparator circuit according to an embodiment of the present invention;
FIG. 6 is a timing waveform diagram according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an efficient direct function mapping analog-to-digital conversion circuit, where the circuit can implement a fully parallel activation function only with one LUT circuit unit, and the circuit is applied In an analog-to-In-Memory (Computing-In-Memory) architecture, as shown In fig. 4, the circuit mainly includes: a sample hold circuit (S/H circuit), a comparator circuit, a DAC circuit, and a register circuit; wherein:
the DAC circuit is a globally shared circuit structure, which includes: the logic control circuit, the LUT circuit and the DAC capacitor array are connected in sequence; the output end of the DAC capacitor array is connected with the reverse input ends of all the comparator circuits; the logic control circuit generates incremental binary data, and the incremental binary data is converted into control signals of corresponding DAC capacitor arrays through the LUT circuit, so that different reference voltages are generated;
the positive input end of each comparator circuit is independently connected with a sampling and holding circuit, analog voltage signals to be converted output by the sampling and holding circuit are input, and the output end of each comparator circuit is independently connected with a register circuit; when the state of the comparator circuit is changed, the corresponding register circuit stores the binary data (count value) output by the logic control circuit, and a binary analog-to-digital conversion result is obtained.
For ease of understanding, the various parts of the circuit and the principles of operation are described in detail below.
1. And a DAC circuit.
In the embodiment of the present invention, the DAC circuit is a globally shared circuit, and mainly includes: the device comprises a logic control circuit, an LUT circuit and a DAC capacitor array.
1. A logic control circuit.
As shown in fig. 4, the logic control circuit mainly includes: a multi-bit Counter (Counter) and a timing Control Logic circuit (Logic Control).
1) The control end of the time sequence control logic circuit is connected with each sampling holding circuit and each comparator circuit, and outputs time sequence control signals of each stage (sampling/holding, reference potential generation, analog voltage comparison and digital output data storage) in the process of generating the analog-to-digital conversion circuit.
2) The multi-bit counter connects the LUT circuit with all the register circuits.
2. A LUT circuit.
The LUT circuit corresponds to a RAM, and the logic control circuit generates binary data to be input to the LUT circuit in increments as an address signal of the LUT circuit, and the LUT circuit finds a logic result which is defined in advance. The LUT circuit is integrated into a globally shared DAC circuit, and the action of a capacitor array in the DAC is controlled by the output of the LUT circuit, so that the global reference voltage generated by the DAC does not increase in proportion but changes according to a preset function rule.
The internal working process of the LUT circuit comprises the following steps: an activation function is selected in advance, in order to enable the final data result to be subjected to the fitting of the activation function, after the activation function is selected, an inverse function of the activation function is obtained, and the inverse function is quantized according to the fitting precision; taking the independent variable of the inverse function as the address of the LUT circuit, and taking the dependent variable as the logic result stored in the RAM in the LUT; and when receiving the increasing binary data, sequentially outputting the data stored in the lookup table to a switch circuit of the DAC capacitor array, thereby controlling the DAC capacitor array to generate different reference voltages.
Taking the sigmoid function as an example, the sigmoid function is: y = 1/(1+e) -x ). The inverse function is Y = ln (x/(1-x)), and the arguments of the inverse function are divided evenly as LUT addresses. When x = k x 0 Where k is converted into a binary number as address signal, x 0 Is the minimum quantization precision. At this time, the value stored in the LUT at the address k should be Y = ln (k × x) 0 /(1-k*x 0 ))。
3. And a DAC capacitor array.
The DAC capacitor array comprises two input ends, the first input end is connected with the output end of the LUT circuit, and the second input end inputs a reference voltage signal V REF 。
The DAC capacitor array adopts a strategy with segmented capacitors, one end of each capacitor is controlled by a switch to be gated to different voltages, and control signals of the switches are from an LUT circuit. Specifically, a strategy with a segmented capacitor and a mode of bridging the capacitor are adopted, so that the ratio of the maximum capacitance value to the minimum capacitance value in the circuit is reduced, and the size of the total capacitance value of the circuit is greatly reduced. The capacitor array can be actually seen as two groups of capacitor array branches, wherein the two branches adopt a common charge distribution structure, and one branch is converted into digitalThe other path converts the low bit of the input digit, the analog output of the low bit is reduced by a plurality of times after passing through the voltage dividing capacitor, and then is superposed with the analog output of the high bit. Compared with the common charge distribution structure, the capacitor array construction mode has small area and reduced capacitance difference, so that higher precision can be obtained. The input signal of the capacitor array comprises V REF GND, LUT, output control signal, output voltage signal V DAC Directly to the negative terminals of all comparators.
2. A comparator circuit.
In the embodiment of the invention, all the comparator circuits have the same structure and can be clock-controlled dynamic comparators, and the comparators compare signals of positive and negative input ends of the comparators to generate 1-bit digital codes. As shown in fig. 5, the clocked dynamic comparator includes: the two pre-amplifying circuits and the latch circuit have dynamic power consumption only at the clock edge, and the other time is equivalent to that the static latch has only static power consumption. The dynamic comparator in the present embodiment is optimized based on a conventional dynamic comparator.
In order to reduce the coupling effect from the output to the input, the two pre-amplifying circuits respectively adopt PMOS transistor and NMOS transistor input strategies (such as P2, P3, N4 and N5 in fig. 5), and meanwhile, the two pre-amplifying circuits are connected by adopting cross-coupled PMOS and NMOS, so that the coupling effect between the input and the output (such as P4, P7, N3 and N7 in the figure) can be greatly reduced. The load tube and the bias tube of the two pre-amplifying circuits are controlled by the clock, so that the static power consumption of the pre-amplifying circuits can be eliminated.
The latch circuit utilizes a cross-coupling structure of a PMOS tube and an NMOS tube to store a comparison value (namely a comparison result of a reference voltage and an analog voltage); the latch state is when the clock is high and the reset state is when the clock is low (OP and ON are both set to 1). The compare state is entered only when the clock transitions from low to high. Inputs V + and V- (V +, V-each representing a forward input and a reverse input, V + being connected to the analog voltage to be converted as described earlier, V-being connected to the output reference voltage of the DAC array) are controlled P10 and P11 via the pre-amplifier circuit such that the speed at which OP and ON are converted from GND to VDD is different. Since the high positive feedback switching speed suppresses the low switching speed, the high switching speed end becomes high and the low switching speed end becomes low, thereby obtaining a comparison result.
The specific structure is shown in fig. 5, a gate of a PMOS transistor P1 is connected with a CLKN signal, a source is connected with VDD, a drain is connected with sources of PMOS transistors P2 and P3, and the CLKN signal is a local clock signal; the grid electrode of the PMOS pipe P2 inputs a V-signal, and the drain electrode is connected with the drain electrode of the NMOS pipe N1; a grid electrode of the PMOS pipe P3 inputs a V + signal, and a drain electrode is connected with a drain electrode of the NMOS pipe N2; the grid electrodes of the NMOS tubes N1 and N2 are connected and input with CLKN signals, and the source electrodes are connected to GND; the source electrode of the PMOS tube P4 is connected with VDD, the drain electrode is connected with the drain electrodes of the PMOS tube P3 and the NMOS tube N2 and the grid electrode of the NMOS tube N3, the grid electrode is connected with the drain electrodes of the NMOS tubes N3 and N4 and the drain electrode of the PMOS tube P5, and the connection point is marked as a node AP; the source electrode of the PMOS tube P5 is connected with VDD, and the grid electrode of the PMOS tube P6 is connected with the grid electrode of the PMOS tube P and inputs CLK signals; a grid electrode of the NMOS tube N4 inputs a V-signal, and a source electrode is connected with a source electrode of the NMOS tube N5 and a drain electrode of the NMOS tube N6; the gate of the NMOS tube N6 inputs a CLK signal, and the source is connected with GND; a grid electrode of the NMOS tube N5 inputs a V + signal, a drain electrode is connected with a drain electrode of the PMOS tube P6, a grid electrode of the PMOS tube P7 and a drain electrode of the NMOS tube N7, and a connection point is marked as a node AN; the source electrodes of the PMOS tube P6 and the PMOS tube P7 are both connected with a VDD signal, the drain electrode of the PMOS tube P7 is connected with the grid electrode of the NMOS tube N7, and the source electrode of the NMOS tube N7 is connected with GND; the grid electrode of the NMOS tube N8 is connected with a CLKN signal, the drain electrode is connected with the drain electrode of the NMOS tube N9, the drain electrode of the PMOS tube P10 and the grid electrodes of the PMOS tube P9 and the NMOS tube N11, and the source electrodes of the NMOS tubes N8 and N9 are connected with GND; the grid electrode of the NMOS tube N9 is connected with the grid electrode of the PMOS tube P8 and is also connected to the NMOS tubes N11 and N12 and the drain electrode of the PMOS tube P11 through leads; the source electrodes of the NMOS tube N11 and the NMOS tube N12 are connected with GND, a CLKN signal is input to the grid electrode of the NMOS tube N12, the grid electrodes of the PMOS tube P10 and the PMOS tube P11 are respectively connected with a node AN and a node AP, and the source electrodes of the PMOS tube P10 and the PMOS tube P11 are respectively connected with the drain electrodes of the PMOS tube P8 and the PMOS tube P9; the sources of PMOS transistors P8 and P9 are both connected to VDD.
In addition, when the comparator is detected to be transited in the output state of the data conversion stage, the clock control comparator circuit locking the corresponding comparator circuit is in a dormant state, so that the power consumption is reduced.
3. A sample and hold circuit.
The sample-and-hold circuit samples the analog voltage value to be converted and holds the analog voltage value at the positive input end of the comparator circuit during the whole data conversion period. The analog voltage value can be kept by adopting a sampling capacitor. As shown in FIG. 4, V 1 ～V n The analog voltages output by the sampling and holding circuits to the corresponding comparator circuits are independent from each other.
4. A register circuit.
The data register is used to store the final ADC output data, unlike previous architectures. Because the reference analog voltage signal generated by the DAC is gradually increased, when the output state of the comparator changes, the comparison of the current channel is considered to be completed, and the current count value of the counter can be directly transmitted to the data register of the current channel, that is, the final binary ADC conversion result is obtained. Meanwhile, the clock of the current channel comparator can be locked to enable the comparator to be in a dormant state, and power consumption is reduced.
The following describes each operating state and characteristic of the analog-to-digital conversion circuit in detail with reference to the timing waveform diagram shown in fig. 6. Wherein: CLK denotes the ADC clock; en _ LUT represents the write port of the lookup table circuit, and the high level is effective; en _ SH represents a sample-and-hold circuit enable signal, active high; en _ DAC represents a DAC array enabling signal, and the high level is effective; CLK _ DAC represents the clock of the DAC array; VSH and VDAC represent the sampled and held analog voltage signal and the reference voltage signal generated by the DAC, respectively; out _ comp represents the output signal of the comparator; en _ comp represents a comparator enable signal, active high; DAC _ counter represents the output signal of the global counter. Before the analog-digital conversion circuit is not operated, a specific activation function needs to be selected first, and corresponding data is stored in a RAM in an LUT in advance in a PH1 stage. In the phase PH2, the sample hold circuit is turned on, and the analog voltage to be converted is input to the forward port of the comparator via the sample hold circuit while the count value of the counter is set to 0. The PH2 phase begins to turn on the dynamic comparator so that the dynamic comparator starts to operate. The DAC starts to work in the PH3 phase, and discrete incremental values are generated according to the clock of the DACThe reference analog voltage value is compared with the sample-hold voltage collected in the PH2 stage, and only when V is present in the PH3 stage DAC >V S/H The output of the comparator is low. In order to reduce power consumption, when the output of the comparator is in a low level in the phase, the comparator of the corresponding channel is closed, and meanwhile, the numerical value of the current counter is output to the corresponding register, and the digital conversion value of the analog voltage of the current channel is obtained.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (3)
1. An efficient direct function mapped analog-to-digital conversion circuit, comprising: the sampling hold circuit, the comparator circuit, the DAC circuit and the register circuit; wherein:
the DAC circuit is a globally shared circuit structure comprising: the logic control circuit, the LUT circuit and the DAC capacitor array are connected in sequence; the output end of the DAC capacitor array is connected with the reverse input ends of all the comparator circuits; the logic control circuit generates incremental binary data, and the incremental binary data is converted into control signals of corresponding DAC capacitor arrays through the LUT circuit, so that different reference voltages are generated;
the positive input end of each comparator circuit is independently connected with a sampling and holding circuit, analog voltage signals to be converted output by the sampling and holding circuit are input, and the output end of each comparator circuit is independently connected with a register circuit; when the state of the comparator circuit is changed, the corresponding register circuit stores the binary data output by the logic control circuit to obtain a binary analog-to-digital conversion result;
the logic control circuit includes: a multi-bit counter and timing control logic; the control end of the sequential control logic circuit is connected with each sampling hold circuit and each comparator circuit, and outputs sequential control signals of each stage in the process of generating the analog-digital conversion circuit; the multi-bit counter is connected with the LUT circuit and all the register circuits;
the logic control circuit generates incremental binary data to be input to the LUT circuit as an address signal of the LUT circuit, and the LUT circuit finds out a predefined logic result; the internal working process of the LUT circuit comprises the following steps: after an activation function is selected in advance, solving an inverse function of the activation function, and quantizing the inverse function according to fitting precision; taking the independent variable of the inverse function as the address of the LUT circuit, and taking the dependent variable as the logic result stored in the RAM in the LUT; when incremental binary data are received, sequentially outputting the data stored in the lookup table to a switch circuit of the DAC capacitor array, thereby controlling the DAC capacitor array to generate different reference voltages;
the DAC capacitor array comprises two input ends, the first input end is connected with the output end of the LUT circuit, and the second input end inputs a reference voltage signal; the DAC capacitor array adopts a strategy with segmented capacitors, one end of each capacitor is controlled by a switch to be gated to different voltages, and control signals of the switches are from an LUT circuit.
2. An efficient direct function mapped analog to digital conversion circuit as claimed in claim 1 wherein said comparator circuit is a clocked dynamic comparator comprising: two pre-amplifying circuits and a latch circuit; the two pre-amplifying circuits respectively adopt PMOS tube and NMOS tube input strategies, the two pre-amplifying circuits are connected by adopting cross-coupled PMOS and NMOS, and the load tubes and the bias tubes of the two pre-amplifying circuits are controlled by a clock; the latch circuit stores the comparison value by using a cross coupling structure of a PMOS tube and an NMOS tube;
and when the comparator is detected to be changed in the output state in the data conversion stage, locking the clock control comparator circuit of the corresponding comparator circuit to be in a dormant state.
3. An efficient direct function mapping analog to digital conversion circuit as claimed in claim 1 or 2, wherein said comparator circuit is configured to:
the gate of the PMOS tube P1 is connected with a CLKN signal, the source electrode is connected with VDD, the drain electrode is connected with the source electrodes of the PMOS tubes P2 and P3, and the CLKN signal is a local clock signal;
the grid electrode of the PMOS pipe P2 inputs a V-signal, and the drain electrode is connected with the drain electrode of the NMOS pipe N1;
a grid electrode of the PMOS pipe P3 inputs a V + signal, and a drain electrode is connected with a drain electrode of the NMOS pipe N2; the V-signal and the V + signal respectively represent a reverse input end signal and a forward input end signal of the comparator circuit;
the grid electrodes of the NMOS tubes N1 and N2 are connected and input with CLKN signals, and the source electrodes are connected to GND;
the source electrode of the PMOS tube P4 is connected with VDD, the drain electrode is connected with the drain electrodes of the PMOS tube P3 and the NMOS tube N2 and the grid electrode of the NMOS tube N3, the grid electrode is connected with the drain electrodes of the NMOS tubes N3 and N4 and the drain electrode of the PMOS tube P5, and the connection point is marked as a node AP;
the source electrode of the PMOS pipe P5 is connected with VDD, the grid electrode of the PMOS pipe P6 is connected with the grid electrode of the PMOS pipe P6, and a CLK signal is input, wherein the CLK signal is an ADC clock signal;
a grid electrode of the NMOS tube N4 inputs a V-signal, and a source electrode is connected with a source electrode of the NMOS tube N5 and a drain electrode of the NMOS tube N6;
the gate of the NMOS tube N6 inputs a CLK signal, and the source is connected with GND;
a grid electrode of the NMOS tube N5 inputs a V + signal, a drain electrode is connected with a drain electrode of the PMOS tube P6, a grid electrode of the PMOS tube P7 and a drain electrode of the NMOS tube N7, and a connection point is marked as a node AN;
the source electrodes of the PMOS tubes P6 and P7 are both connected with a VDD signal, the drain electrode of the PMOS tube P7 is connected with the grid electrode of the NMOS tube N7, and the source electrode of the NMOS tube N7 is connected with GND;
the grid electrode of the NMOS tube N8 is connected with a CLKN signal, the drain electrode is connected with the drain electrode of the NMOS tube N9, the drain electrode of the PMOS tube P10 and the grid electrodes of the PMOS tube P9 and the NMOS tube N11, and the source electrodes of the NMOS tubes N8 and N9 are connected with GND;
the grid electrode of the NMOS tube N9 is connected with the grid electrode of the PMOS tube P8 and is also connected to the NMOS tubes N11 and N12 and the drain electrode of the PMOS tube P11 through leads;
the source electrodes of the NMOS tube N11 and the NMOS tube N12 are connected with GND, a CLKN signal is input to the grid electrode of the NMOS tube N12, grid electrodes of the PMOS tube P10 and the PMOS tube P11 are respectively connected with a node AN and a node AP, and the source electrodes of the PMOS tube P10 and the PMOS tube P11 are respectively connected with drain electrodes of a PMOS tube P8 and a PMOS tube P9;
the sources of PMOS transistors P8 and P9 are both connected to VDD.
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