CN113114190B - Clock recovery circuit and method, data processing chip and electronic equipment - Google Patents
Clock recovery circuit and method, data processing chip and electronic equipment Download PDFInfo
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- CN113114190B CN113114190B CN202110377819.XA CN202110377819A CN113114190B CN 113114190 B CN113114190 B CN 113114190B CN 202110377819 A CN202110377819 A CN 202110377819A CN 113114190 B CN113114190 B CN 113114190B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A clock recovery circuit and method, data processing chip, electronic device, clock recovery circuit includes: latch module, monostable module and inverting logic unit, wherein: the first setting end S of the latch module inputs a plurality of groups of pulse signals, and latches the rising edge and outputs the rising edge through the first output end when any group of pulse signals jump from low level to high level; the input end of the inverting logic unit is coupled with the first output end of the latch module, the first output end of the inverting logic unit is coupled with the first reset end RN of the latch module, and the second output end of the inverting logic unit is coupled with the second set end SN of the latch module; the first input end of the monostable module is coupled with the first output end of the inverting logic unit, the second input end of the monostable module inputs a voltage power supply, and the output end of the monostable module is coupled with the second reset end R of the latch module; the input signal of the first reset terminal RN is inverted to the input signal of the second reset terminal R. The scheme can realize accurate recovery of the clock.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to a clock recovery circuit and method, a data processing chip, and an electronic device.
Background
The purpose of clock recovery is to track the clock drift and a portion of the jitter at the transmitting end to determine the correct data samples. The clock recovery circuit (Clock Data Recovery, CDR) is typically implemented by means of a Phase Lock Loop (PLL) circuit.
However, the accuracy of the clock signal recovered by the existing clock recovery circuit is low.
Disclosure of Invention
The embodiment of the invention solves the technical problem that the clock signal recovered by the clock recovery circuit has lower accuracy.
In order to solve the above technical problems, an embodiment of the present invention provides a clock recovery circuit, which is applied to a C-PHY, and includes: latch module, monostable module and inverting logic unit, wherein: the first setting end S of the latch module inputs a plurality of groups of pulse signals, and latches the rising edge and outputs the rising edge through the first output end when any group of pulse signals jump from low level to high level; the input end of the inversion logic unit is coupled with the first output end of the latch module, the first output end of the inversion logic unit is coupled with the first reset end RN of the latch module, and the second output end of the inversion logic unit is coupled with the second set end SN of the latch module; the first input end of the monostable module is coupled with the first output end of the inverting logic unit, the second input end of the monostable module inputs a voltage power supply, and the output end of the monostable module is coupled with the second reset end R of the latch module; the input signal of the first reset terminal RN is inverted to the input signal of the second reset terminal R.
Optionally, the latch module includes: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube, wherein: the grid electrode of the first PMOS tube is coupled with the second output end of the latch module, the drain electrode of the first PMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the first PMOS tube inputs the power supply voltage; the grid electrode of the second PMOS tube is coupled with the first output end of the latch module, the drain electrode of the second PMOS tube is coupled with the drain electrode of the second NMOS tube, and the source electrode of the second PMOS tube inputs the power supply voltage; the grid electrode of the first NMOS tube is coupled with the second output end of the latch module, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is coupled with the first output end of the latch module, and the source electrode of the second NMOS tube is coupled with the ground; the grid electrode of the third NMOS tube is coupled with the input end of the latch module, the drain electrode of the third NMOS tube is coupled with the second output end of the latch module, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube; the grid electrode of the fourth NMOS tube is coupled with the first reset end RN of the latch module, and the source electrode of the fourth NMOS tube is grounded; the grid electrode of the fifth NMOS tube is coupled with the second reset end R of the latch module, the drain electrode of the fifth NMOS tube is coupled with the first output end of the latch module, and the source electrode of the fifth NMOS tube is coupled with the drain electrode of the sixth NMOS tube; the gate of the sixth NMOS transistor is coupled to the second set terminal SN of the latch module, and the source thereof is grounded.
Optionally, the monostable module includes a nand gate, a third inverter, a delay circuit, and a nor gate, wherein: the first input end of the NAND gate is coupled with the first input end of the monostable module, the second input end of the NAND gate is coupled with the second input end of the monostable module, and the output end of the NAND gate is coupled with the input end of the third inverter; the output end of the third inverter is coupled with the first input end of the NOR gate circuit; the input end of the delay circuit is coupled with the first output end of the inverting logic unit, and the output end of the delay circuit is coupled with the second input end of the NOR gate circuit; and the output end of the NOR gate circuit is coupled with the output end of the monostable module.
Optionally, the clock recovery circuit further includes: and the time value conversion circuit is coupled with the control end of the delay circuit and is suitable for controlling the delay time length of the delay circuit.
Optionally, the clock recovery circuit further includes: and the input end of the buffer module is coupled with the output end of the clock recovery circuit and is suitable for driving and outputting the output clock signal of the clock recovery circuit.
Optionally, the buffer module includes a fourth inverter and a fifth inverter, wherein: the input end of the fourth inverter is coupled with the first output end of the inversion logic unit, and the output end of the fourth inverter is coupled with the input end of the fifth inverter; the output end of the fifth inverter outputs the clock signal after overdrive; the driving coefficient of the fifth inverter is greater than the driving coefficient of the fourth inverter.
Optionally, when the first reset terminal RN of the latch module inputs a high level, the latch module is set through the first set terminal S; when the second set terminal SN of the latch module inputs a high level, the latch module is reset through the second reset terminal R.
Optionally, the time when the first reset terminal RN of the latch module sets the second reset terminal R to the high level is located at the time when the setting of the first set terminal S is finished.
Optionally, the inverting logic unit includes a first inverter and a second inverter, wherein: the input end of the first inverter is the input end of the inversion logic unit, and the output end of the first inverter is the first output end of the inversion logic unit; the input end of the second inverter is coupled with the output end of the first inverter, and the output end of the second inverter is the second output end of the inversion logic unit.
The embodiment of the invention also provides a data processing chip which comprises the clock recovery circuit.
The embodiment of the invention also provides electronic equipment comprising the data processing chip.
The embodiment of the invention also provides a clock recovery method, which comprises the following steps: detecting the widths of a plurality of groups of input pulse signals when the plurality of groups of pulse signals are detected; and encoding the widths of the plurality of groups of pulse signals, and sending an encoding result to a clock recovery circuit to control the transient time of a monostable module in the clock recovery circuit.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the clock recovery circuit comprises a latch module, a monostable module and an inverting logic unit, wherein the latch module latches a plurality of groups of pulse signals input by a first set end of the clock recovery circuit, and when any group of pulse signals jump from a low level to a high level, the rising edge of any group of pulse signals is latched. The first output end of the inverting logic unit inverts the output signal of the first output end of the latch module, and the second output end of the inverting logic unit inverts the output signal of the first output end of the inverting logic unit. The first input end of the monostable module inputs the output signal of the first output end of the inverted latch module, and obtains stable delay through the delay path of the monostable module, thereby realizing accurate clock recovery.
Drawings
FIG. 1 is a schematic diagram of a clock recovery circuit in an embodiment of the invention;
fig. 2 is a schematic diagram of a latch module according to an embodiment of the present invention.
Detailed Description
As described in the background art above, the accuracy of the clock signal recovered by the existing clock recovery circuit is low.
In the embodiment of the invention, the clock recovery circuit comprises a latch module, a monostable module and an inverting logic unit, wherein a plurality of groups of pulse signals input by a first set end of the clock recovery circuit are latched through the latch module, and when any group of pulse signals jump from a low level to a high level, rising edges of the pulse signals are latched. The first output end of the inverting logic unit inverts the output signal of the first output end of the latch module, and the second output end of the inverting logic unit inverts the output signal of the first output end of the inverting logic unit. The first input end of the monostable module inputs the output signal of the first output end of the inverted latch module, and obtains stable delay through the delay path of the monostable module, thereby realizing accurate clock recovery.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a clock recovery circuit which is applied to a C-PHY. In an implementation, the clock recovery circuit may include: latch module 1, monostable module and inverting logic unit.
In the embodiment of the present invention, the first set terminal of the latch module 1 is an S terminal, and may input a plurality of groups of pulse signals. When any one of the pulse signals transitions from a low level to a high level, the latch module 1 may latch a rising edge and output via the first output terminal OUT of the latch module 1.
The input terminal of the inversion logic unit may be coupled to the first output terminal of the latch module 1, the first output terminal of the inversion logic unit is coupled to the first reset terminal RN of the latch module 1, and the second output terminal of the inversion logic unit is coupled to the second set terminal SN of the latch module 1.
The first input end of the monostable module is coupled with the first output end of the inverting logic unit, the second input end of the monostable module inputs the power supply voltage, and the output end of the monostable module is coupled with the second reset end R of the latch module 1.
In an embodiment, the input signal of the first reset terminal RN is inverted from the input signal of the second reset terminal R.
Referring to fig. 2, a schematic diagram of a latch module 1 according to an embodiment of the present invention is shown.
In the embodiment of the present invention, the latch module 1 may include a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6, where:
the grid electrode of the first PMOS tube MP1 can be coupled with the second output end OUTN of the latch module 1, the drain electrode of the first PMOS tube MP1 can be coupled with the drain electrode of the first NMOS tube MN1, and the source electrode of the first PMOS tube MP1 can be input with a power supply voltage;
the grid electrode of the second PMOS tube MP2 can be coupled with the first output end of the latch module 1, the drain electrode of the second PMOS tube MP2 can be coupled with the drain electrode of the second NMOS tube MN2, and the source electrode of the second PMOS tube MP2 can be input with a power supply voltage;
the grid electrode of the first NMOS tube MN1 can be coupled with the second output end OUTN of the latch module 1, the drain electrode of the first NMOS tube MN1 can be coupled with the drain electrode of the first PMOS tube MP1, and the source electrode of the first NMOS tube MN1 is grounded;
the grid electrode of the second NMOS tube MN2 can be coupled with the first output end of the latch module 1, the drain electrode of the second NMOS tube MN2 can be coupled with the drain electrode of the second PMOS tube MP2, and the source electrode of the second NMOS tube MN2 is grounded;
the gate of the third NMOS transistor MN3 may be coupled to the input terminal of the latch module 1, the drain of the third NMOS transistor MN3 may be coupled to the second output terminal of the latch module 1, and the source of the third NMOS transistor MN3 may be coupled to the drain of the fourth NMOS transistor MN 4;
the gate of the fourth NMOS transistor MN4 may be coupled to the first reset terminal RN of the latch module 1, the drain of the fourth NMOS transistor MN4 may be coupled to the source of the third NMOS transistor MN3, and the source of the fourth NMOS transistor MN4 is grounded;
the gate of the fifth NMOS transistor MN5 may be coupled to the second reset terminal R of the latch module 1, the drain of the fifth NMOS transistor MN5 may be coupled to the first output terminal of the latch module 1, and the source of the fifth NMOS transistor MN5 may be coupled to the drain of the sixth NMOS transistor MN 6;
the gate of the sixth NMOS transistor MN6 may be coupled to the second set terminal SN of the latch module 1, the drain of the sixth NMOS transistor MN6 may be coupled to the source of the fifth NMOS transistor MN5, and the source of the sixth NMOS transistor MN6 is grounded.
In a specific implementation, when the first reset terminal RN of the latch module 1 inputs a high level, the latch module 1 is set through the first set terminal S; when the second set terminal SN of the latch module 1 inputs a high level, the latch module 1 is reset through the second reset terminal R.
In an embodiment, the time when the first reset terminal RN and the second reset terminal R of the latch module 1 are set to the high level may be at the time when the setting of the first set terminal S is finished. That is, when the first set terminal srset is finished, the first reset terminal RN and the second reset terminal R of the latch module 1 may be set to a high level.
In the embodiment of the present invention, when the first set terminal S of the latch module 1 inputs a group of pulse signals, the first reset terminal RN defaults to a high level, the second set terminal SN defaults to a low level, and the second reset terminal R defaults to a low level. When the first rising edge in a set of pulse signals arrives, the output of the latch module 1 is set high and the latch module 1 is set. When the output terminal of the latch module 1 is set to a high level, the first reset terminal RN is set to a low level, the second set terminal SN is set to a high level, and the latch module 1 latches the first rising edge of the set of pulse signals without being controlled by the first set terminal S. The falling edge of the signal of the first reset terminal RN forms a reset signal after delay, and the second reset terminal R is set to a high level. Since the second set terminal is in the high-level state at this time, the output terminal of the latch module 1 is set to the low level, and the latch module 1 is reset. After the output terminal of the latch module 1 is set to a low level, the first reset terminal RN is set to a high level, the second set terminal SN is set to a low level, the rising edge of the signal of the first reset terminal RN does not undergo delay to form a reset signal, the second reset terminal R is set to a low level, and the latch module returns to a default state to wait for the next group of pulse signals.
In an embodiment of the present invention, the monostable module may include a nand gate 21, a third inverter I3, a delay circuit 22, and a nor gate 23, wherein:
a first input of the nand gate 21 may be coupled to a first input of the monostable, a second input of the nand gate 21 may be coupled to a second input of the monostable, and an output of the nand gate 21 may be coupled to an input of the third inverter I3;
an input of the third inverter I3 may be coupled to an output of the nand gate 21, and an output of the third inverter I3 may be coupled to a first input of the nor gate 23;
an input of the delay circuit 22 may be coupled to a first output of the inverting logic unit, and an output of the delay circuit 22 may be coupled to a second input of the nor gate 23;
an output of nor gate 23 may be coupled to an output of the monostable.
In implementations, the monostable may include a delayed path as well as a non-delayed path. The delay path corresponds to the delay time of the delay circuit 22 being not 0, and the delay time of the non-delay path corresponds to the delay time of the delay circuit 22 being 0. The time of the reset operation can be controlled by the delay path as well as the non-delay path.
In the embodiment of the present invention, the signal output from the first output terminal of the inverting logic unit is input to the first reset terminal RN of the latch module 1, and therefore, the signal input from the first input terminal of the monostable module is substantially the same as the signal input from the first reset terminal RN of the latch module 1. The rising edge of the output signal of the first output end of the latch module 1 passes through a delay path to obtain a delayed high-order reset signal; the falling edge of the output signal of the first output end of the latch module 1 passes through a non-delay path to obtain a low-order reset signal.
In the embodiment of the present invention, the inversion logic unit may include a first inverter I1 and a second inverter I2, wherein:
the input end of the first inverter I1 may be an input end of the inversion logic unit, and the output end of the first inverter I1 may be a first output end of the inversion logic unit;
the input terminal of the second inverter I2 may be coupled to the output terminal of the first inverter I1, and the output terminal of the second inverter I2 may be the second output terminal of the reverberation logic unit.
In implementations, the clock recovery circuit may also include a time to digital conversion circuit. The time-to-digital conversion circuit may be coupled to the control terminal CTL of the delay circuit 22, and the delay duration of the delay circuit 22 is controlled by the time-to-digital conversion circuit.
That is, the time-delay time length to be set is input to the delay circuit 22 through the time-to-digital conversion circuit, so that the control of the delay circuit 22 is realized.
In implementations, the clock recovery circuit may further include a buffer module, an input of which may be coupled to an output of the clock recovery circuit. The buffer module can drive the output clock signal of the clock recovery circuit, and increase the driving capability of the output clock signal of the clock recovery circuit.
In an embodiment of the present invention, the buffer module may include a fourth inverter I4 and a fifth inverter I5, wherein:
an input terminal of the fourth inverter I4 may be coupled to the first output terminal of the inverse logic unit, and an output terminal of the fourth inverter I4 may be coupled to an input terminal of the fifth inverter I5;
an input terminal of the fifth inverter I5 may be coupled to an output terminal of the fourth inverter I4, and an output terminal of the fifth inverter I5 may output the driven clock signal CLK.
In a specific implementation, the fourth inverter I4 and the fifth inverter I5 may have different driving coefficients. In the embodiment of the present invention, the driving coefficient of the fifth inverter I5 may be greater than the driving coefficient of the fourth inverter I4.
The embodiment of the invention also provides a data processing chip, which comprises the clock recovery circuit provided in the embodiment.
The embodiment of the invention also provides electronic equipment comprising the data processing chip.
The embodiment of the invention also provides a clock recovery method, which comprises the following steps: detecting the widths of a plurality of groups of input pulse signals when the plurality of groups of pulse signals are detected; and encoding the widths of the multiple groups of pulse signals, and sending an encoding result to a clock recovery circuit to control the transient time of a monostable module in the clock recovery circuit.
In a specific implementation, the clock recovery circuit involved in the clock recovery method may be a clock recovery circuit provided in the foregoing embodiments of the present application.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
1. A clock recovery circuit for use with a C-PHY, comprising: latch module, monostable module, inverting logic unit, wherein:
the first setting end S of the latch module inputs a plurality of groups of pulse signals, and latches the rising edge and outputs the rising edge through the first output end when any group of pulse signals jump from low level to high level;
the input end of the inversion logic unit is coupled with the first output end of the latch module, the first output end of the inversion logic unit is coupled with the first reset end RN of the latch module, and the second output end of the inversion logic unit is coupled with the second set end SN of the latch module;
the first input end of the monostable module is coupled with the first output end of the inverting logic unit, the second input end of the monostable module inputs a voltage power supply, and the output end of the monostable module is coupled with the second reset end R of the latch module; the input signal of the first reset terminal RN is opposite to the input signal of the second reset terminal R;
the monostable module comprises a NAND gate circuit, a third inverter, a delay circuit and a NOR gate circuit, wherein: the first input end of the NAND gate is coupled with the first input end of the monostable module, the second input end of the NAND gate is coupled with the second input end of the monostable module, and the output end of the NAND gate is coupled with the input end of the third inverter; the output end of the third inverter is coupled with the first input end of the NOR gate circuit; the input end of the delay circuit is coupled with the first output end of the inverting logic unit, and the output end of the delay circuit is coupled with the second input end of the NOR gate circuit; and the output end of the NOR gate circuit is coupled with the output end of the monostable module.
2. The clock recovery circuit of claim 1, wherein the latch module comprises: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube, wherein:
the grid electrode of the first PMOS tube is coupled with the second output end of the latch module, the drain electrode of the first PMOS tube is coupled with the drain electrode of the first NMOS tube, and the source electrode of the first PMOS tube inputs power supply voltage;
the grid electrode of the second PMOS tube is coupled with the first output end of the latch module, the drain electrode of the second PMOS tube is coupled with the drain electrode of the second NMOS tube, and the source electrode of the second PMOS tube inputs the power supply voltage;
the grid electrode of the first NMOS tube is coupled with the second output end of the latch module, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is coupled with the first output end of the latch module, and the source electrode of the second NMOS tube is coupled with the ground;
the grid electrode of the third NMOS tube is coupled with the input end of the latch module, the drain electrode of the third NMOS tube is coupled with the second output end of the latch module, and the source electrode of the third NMOS tube is coupled with the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is coupled with the first reset end RN of the latch module, and the source electrode of the fourth NMOS tube is grounded;
the grid electrode of the fifth NMOS tube is coupled with the second reset end R of the latch module, the drain electrode of the fifth NMOS tube is coupled with the first output end of the latch module, and the source electrode of the fifth NMOS tube is coupled with the drain electrode of the sixth NMOS tube; the gate of the sixth NMOS transistor is coupled to the second set terminal SN of the latch module, and the source thereof is grounded.
3. The clock recovery circuit of claim 1, further comprising: and the time value conversion circuit is coupled with the control end of the delay circuit and is suitable for controlling the delay time length of the delay circuit.
4. The clock recovery circuit of claim 1, further comprising: and the input end of the buffer module is coupled with the output end of the clock recovery circuit and is suitable for driving and outputting the output clock signal of the clock recovery circuit.
5. The clock recovery circuit of claim 4, wherein the buffer module comprises a fourth inverter and a fifth inverter, wherein:
the input end of the fourth inverter is coupled with the first output end of the inversion logic unit, and the output end of the fourth inverter is coupled with the input end of the fifth inverter;
the output end of the fifth inverter outputs the clock signal after overdrive; the driving coefficient of the fifth inverter is greater than the driving coefficient of the fourth inverter.
6. The clock recovery circuit of claim 1, wherein the latch module is set by the first set terminal S when the first reset terminal RN of the latch module inputs a high level; when the second set terminal SN of the latch module inputs a high level, the latch module is reset through the second reset terminal R.
7. The clock recovery circuit of claim 1, wherein the time when the first reset terminal RN and the second reset terminal R of the latch module are set high is at the time when the setting of the first set terminal S is finished.
8. The clock recovery circuit of any one of claims 1-7, wherein the inverting logic unit comprises a first inverter and a second inverter, wherein:
the input end of the first inverter is the input end of the inversion logic unit, and the output end of the first inverter is the first output end of the inversion logic unit;
the input end of the second inverter is coupled with the output end of the first inverter, and the output end of the second inverter is the second output end of the inversion logic unit.
9. A data processing chip comprising a clock recovery circuit as claimed in any one of claims 1 to 8.
10. An electronic device comprising the data processing chip of claim 9.
11. A method of clock recovery comprising:
detecting the widths of a plurality of groups of input pulse signals when the plurality of groups of pulse signals are detected;
and encoding the widths of the plurality of groups of pulse signals, and sending an encoding result to a clock recovery circuit to control the transient time of a monostable module in the clock recovery circuit.
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| CN202110377819.XA CN113114190B (en) | 2021-04-08 | 2021-04-08 | Clock recovery circuit and method, data processing chip and electronic equipment |
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|---|---|---|---|---|
| CN107925564A (en) * | 2015-09-01 | 2018-04-17 | 高通股份有限公司 | Multi-phase clock data recovery circuit is calibrated |
| CN111404543A (en) * | 2020-05-27 | 2020-07-10 | 深圳市汇顶科技股份有限公司 | Clock data recovery circuit, processing chip and electronic equipment |
| CN112204919A (en) * | 2018-05-04 | 2021-01-08 | 高通股份有限公司 | Calibration pattern and duty cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface |
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| US10742390B2 (en) * | 2016-07-13 | 2020-08-11 | Novatek Microelectronics Corp. | Method of improving clock recovery and related device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107925564A (en) * | 2015-09-01 | 2018-04-17 | 高通股份有限公司 | Multi-phase clock data recovery circuit is calibrated |
| CN112204919A (en) * | 2018-05-04 | 2021-01-08 | 高通股份有限公司 | Calibration pattern and duty cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface |
| CN111404543A (en) * | 2020-05-27 | 2020-07-10 | 深圳市汇顶科技股份有限公司 | Clock data recovery circuit, processing chip and electronic equipment |
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