CN113112481B - Hybrid heterogeneous on-chip architecture based on matrix network - Google Patents
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Abstract
The invention discloses a matrix network-based hybrid heterogeneous on-chip architecture, which is based on a ship target detection algorithm of remote sensing images and mainly comprises the following steps: an operation IP unit for decomposing the algorithm into basic image processing operation, and summarizing the basic image processing operation into 6 operation IP units; a distributed storage unit divided into independent sub-units of different storage sizes by the storage unit; the CPU main control unit is used for controlling each operation IP state jump; and the arbitration unit is used for realizing multiplexing and access arbitration of the memory. According to the method, the operation IP can be called in a time-sharing mode according to the algorithm operation steps and the memory is accessed, so that efficient multiplexing of operation and storage and optimal optimization of logic scale are realized, the multiplexing degree of storage resources of the on-board processing chip is improved, the operation logic resources are reduced, and the on-orbit real-time processing requirement is met.
Description
Technical Field
The invention belongs to the field of on-orbit real-time information processing of optical remote sensing satellites, relates to a chip architecture design technology in the field of target detection and identification processing of optical remote sensing ships, and particularly relates to a hybrid heterogeneous on-chip architecture based on a matrix network.
Background
Optical remote sensing is an important means for acquiring remote sensing information due to the characteristics of high resolution, simple load structure and the like. The on-orbit real-time processing system of the optical remote sensing image can effectively perform target detection and identification processing on the collected optical remote sensing data and transmit the target detection and identification processing to the ground in real time, so that the timeliness of acquiring the remote sensing information can be greatly improved, and disaster relief, real-time environment monitoring, emergency and anti-terrorism, stability and national security are effectively supported. Under the constraints of on-board storage resources and operation resources, the existing on-board processing system is difficult to realize on-orbit real-time processing of mass remote sensing data.
Disclosure of Invention
In view of the above, the present invention provides a hybrid heterogeneous on-chip architecture based on a matrix network, which provides a method for calculating an IP and storing distribution mapping for an optical remote sensing ship target detection and identification algorithm, and calls the calculation IP and accesses a memory in a time-sharing manner according to an algorithm calculation step, so as to realize efficient multiplexing of calculation and storage and optimal optimization of a logic scale.
A mixed heterogeneous on-chip architecture based on a matrix network comprises an operation IP unit, a storage unit, a CPU main control unit and an arbitration unit;
the plurality of operation IP units are formed by disassembling a ship target detection algorithm based on remote sensing images into a plurality of basic image processing operation units;
the storage unit is used for storing data;
the CPU main control unit is used for controlling each operation IP to jump the algorithm state according to the operation steps in the ship target detection algorithm flow;
the arbitration unit is used for:
when the reading operation is carried out, the operation IP unit sends a request to the arbitration unit, and after receiving the reading request, the arbiter reads data from the corresponding storage unit according to the priority sequence of each operation IP unit and sends the data to the operation IP unit;
when writing operation is carried out, the operation IP unit sends a request to the arbitration unit, and the arbitration unit stores data output by the operation IP unit into a corresponding storage unit according to the priority order of each operation IP unit.
Preferably, the operation IP unit includes:
(1) The overlapped whole window operation IP unit is used for carrying out translation scanning on the rectangular window data block, processing all data in the window, and realizing expansion, corrosion and filtering operations by overlapping two adjacent windows;
(2) The non-overlapping whole window operation IP unit carries out translation scanning on the rectangular window data block, takes all data in the windows for processing, and realizes the function of a lighting module without overlapping between two adjacent windows;
(3) The non-overlapping partial window operation IP unit is used for carrying out translation scanning on the rectangular window data block, taking partial data in the windows for processing, and realizing the function of a fine confirmation module without overlapping between two adjacent windows;
(4) The single pixel traversal operation IP unit is used for traversing each pixel and processing the pixel to realize the function of a histogram statistics module;
(5) The overlapping adjacent operation IP unit extracts information according to the association degree between pixels, and the irregular areas can be overlapped with each other to realize the function of a connected domain extraction module;
(6) The non-overlapping adjacent operation IP unit extracts information according to the association degree between pixels, and the areas are irregular and non-overlapping, so that SOBEL module function is realized;
preferably, the overlapped integer window processing operation IP unit may configure the integer window size and scan steps, as well as a plurality of overlapped integer window operations.
Preferably, when performing a read operation, the operation IP module sends a request to the arbitration device to send a read data length and address, and the arbitration device accesses the corresponding memory and reads data according to the data length and address.
Preferably, when performing a write operation, the operation IP module simultaneously sends a request, a write signal, an address, data, a data length, and data start and stop flag signals to the arbitration unit, and the arbitration unit accesses the corresponding memory unit accordingly and writes the data.
Preferably, when two similar algorithms with different configuration parameters need to be processed, the CPU master control unit performs parameter configuration on the same operation IP unit capable of implementing the algorithm, and controls the operation IP unit to complete the two similar algorithms in a time-sharing manner.
Preferably, when one algorithm uses the output data of the other algorithm, the CPU main control unit calls two operation IP units executing the algorithm, and connects the two operation IP units in series, and the latter operation IP unit directly receives the output data of the former operation IP unit.
Preferably, the arbitration unit is used for storing the output data of different operation IP units to different positions of the same memory.
Preferably, the storage units have different storage sizes.
The invention has the following beneficial effects:
the invention discloses a matrix network-based hybrid heterogeneous on-chip architecture, which is based on a ship target detection algorithm of remote sensing images and mainly comprises the following steps: an operation IP unit for decomposing the algorithm into basic image processing operation, and summarizing the basic image processing operation into 6 operation IP units; a distributed storage unit divided into independent sub-units of different storage sizes by the storage unit; the CPU main control unit is used for controlling each operation IP state jump; and the arbitration unit is used for realizing multiplexing and access arbitration of the memory. According to the method, the operation IP can be called in a time-sharing mode according to the algorithm operation steps and the memory is accessed, so that efficient multiplexing of operation and storage and optimal optimization of logic scale are realized, the multiplexing degree of storage resources of the on-board processing chip is improved, the operation logic resources are reduced, and the on-orbit real-time processing requirement is met.
Drawings
Fig. 1 is a schematic diagram of the present invention.
Fig. 2 is an IP diagram of overlapping whole window operations.
Fig. 3 is a non-overlapping whole window operation IP diagram.
Fig. 4 is a non-overlapping partial window operation IP diagram.
Fig. 5 is a single pixel traversal operation IP diagram.
Fig. 6 is an IP diagram of overlapping adjacencies.
Fig. 7 is a non-overlapping adjacency calculation IP diagram.
Fig. 8 is a schematic diagram of an algorithm initial flow.
Fig. 9 is a schematic diagram after algorithm optimization.
Detailed Description
The invention will now be described in detail by way of example with reference to the accompanying drawings.
The invention relates to a hybrid heterogeneous on-chip architecture based on a matrix network, and the architecture diagram is shown in figure 1. The invention comprises the following contents:
1. operation IP unit
The processing operation IP unit is a core part of the image processing system architecture provided by the invention, and the remote sensing image-based ship target detection algorithm is disassembled into basic image processing operation, so that the algorithm is generalized into 6 operation IP units, and the processing operation IP unit comprises:
(1) Overlapping whole window operation IP
The overlapping whole window operation IP is characterized in that the rectangular window data block is subjected to translation scanning, all data in the window are taken and processed, and two adjacent windows are overlapped, and related typical image processing basic steps such as expansion, corrosion, filtering and the like are performed. A block processing module based on an overlapping integer window processing operation IP is designed, which supports configurable integer window sizes and scan stepping, as well as a variety of overlapping integer window operations, configured to achieve the expansion, corrosion, filtering of 3 x 3, 5 x 5, 7 x 7 required by an optical remote sensing vessel detection algorithm. The modular architecture design is shown in fig. 2.
(2) Non-overlapping whole window operation IP
The non-overlapping whole window operation IP is to perform translation scanning on a rectangular window data block, process all data in a window, and the adjacent two windows are not overlapped, a lighting module in a remote sensing image ship target detection algorithm is realized based on the operation IP design, and the operation IP architecture is shown in figure 3.
(3) Non-overlapping partial window operation IP
The non-overlapping window operation IP is to perform translation scanning on the rectangular window data block, take partial data in the window and process the partial data, and no overlap exists between two adjacent windows. A fine confirmation module in a remote sensing image ship target detection algorithm is designed based on non-overlapping partial window operation IP, and the function of the module is to further confirm whether points in a defined search area are suspected ship targets or not in a fine mode, and an operation IP architecture is shown in fig. 4.
(4) Single pixel traversal operation IP
The single pixel traversal operation IP is to traverse each pixel and process it. A histogram statistics module in an optical remote sensing ship detection algorithm is designed based on the operation IP, and all histogram statistics and subsequent parameter calculation in the algorithm are completed by adopting the module, wherein the operation IP architecture is shown in figure 5.
(5) Overlap adjacency calculation IP
The overlap adjacency operation IP extracts information according to the degree of association between pixels, and the regions are irregularly overlapped with each other. And a connected domain extraction module based on overlapping adjacency operation IP is designed to realize single-line buffering and single-time scanning and realize the rapid extraction of the critical information of the connected domain, as shown in fig. 6.
The module mainly completes the scanning of pixels from left to right, from top to bottom, line by line, stores temporary marks and forms equivalent relation pairs during scanning, and stores the maximum value, the minimum value and the area sum of coordinates of each temporary mark area at the same time. After the scanning is finished, the equivalence relation pair is processed through a certain searching and processing mode, and meanwhile, the maximum value, the minimum value, the area sum of the coordinates are sorted, so that the first-stage false alarm rejection is completed. And finally outputting the label of the non-proposed marked area and the corresponding maximum value, minimum value and the sorted area sum of the coordinates.
(6) Non-overlapping adjacency calculation IP
The non-overlapping adjacency calculation IP extracts information according to the degree of association between pixels, and the regions are irregular and non-overlapping. Based on the operation IP, a SOBEL module in the optical remote sensing ship detection algorithm is designed, the SOBEL operation of the whole graph is realized, and the operation IP architecture is shown in figure 7.
2. Memory cell
The memory cells in the architecture are divided into an external memory and an internal memory according to the characteristics of the memory device. The external memory adopts a chip with large capacity, high sequential access speed and large power consumption such as SDRAM/SRAM, the external memory is usually used for storing original data, the internal memory adopts a memory module with SRAM as a main part, the internal memory has high access speed, large bit width, low power consumption, small capacity and random access, and is used for temporarily storing the result in the middle of data operation.
In the optical remote sensing ship target detection and identification algorithm, the image processing is formed by combining a plurality of basic steps of expansion, corrosion, communication and the like, and the memory multiplexing rate can be improved and the memory capacity can be reduced according to the characteristics of the data using time. The storage unit adopts the design concept of distributed storage, in order to ensure that data blockage does not occur when different processing operation IPs access the storage unit, the storage unit is divided into independent subunits with different storage sizes, each subunit is connected with a bus unit through an input/output interface, so that the data distributed storage is realized, a memory multiplexing rule is designed according to the data use time corresponding to the processing operation IPs and the operation IP calling time sequence, the memory multiplexing rate is improved, and the hardware resource utilization rate is improved.
3. CPU main control unit
The CPU main control unit is used for controlling each operation IP to jump the algorithm state according to the operation steps in the algorithm flow. For example, as shown in fig. 8, each state in the graph represents the image processing operation of each stage of the algorithm, the solid line represents the jump direction and sequence of the state flow, the dotted line represents the flow direction of each state data, for example, assuming that the processes of M3 and M7 are basically similar, the processes are respectively 256-point histogram statistics operation and 1024-point histogram statistics operation, but the input and output signals and the configuration parameters of the two are different, the M3 and M7 state operations can be designed as an operation IP module with the same configurable parameter. And the M4 and M5 modules respectively comprise output signals of the M2 module, the output of the M4 is used as the input of the M5, the output of the M4 and the output of the M5 are different, and the states of the M4 and the M5 can be combined, so that the operations of data reading, writing, intermediate data temporary storage and the like are reduced, and after the M4 and the M5 are combined, the dotted line data flow is reduced from 12 to 10. In addition, the final state machine can be obtained by redesigning the state machine in a data association, operation, IP multiplexing and memory multiplexing manner, as shown in fig. 9.
4. Arbitration unit
An access policy of fixed priority is adopted to realize the arbitration unit. By analyzing the memory type and the access relation, a multi-path arbiter is designed in the arbitration unit, and the multiplexing and the access arbitration of the memory are realized through the arbiter. When each operation IP accesses the memory, the high 5 bits of the access address are sent to the arbitration unit to be used as the judgment basis of priority judgment and memory access.
The operation IP realizes the operation in the algorithm processing process, accesses the off-chip and on-chip storage through the memory arbitration, and is used for reading the processed image data or storing the algorithm processing result into the corresponding memory. An APB bus protocol is employed between the operation IP and the storage arbitration logic in the implementation of the detection algorithm. The arithmetic IP block sends a request (herg) to the arbiter at the time of the read operation, and simultaneously sends a read data length (hlength) and an address (haddr), and the arbiter outputs an authorization signal (hgrant) to the arithmetic IP. And after receiving the read request, the arbiter judges the memory to be accessed through the high-order address and reads the data. The arbiter outputs data (hrdata) and a data valid signal (hready) to the operation IP, and outputs data start and stop flag signals at the same time. The operation IP block simultaneously sends a request (hreq), a write signal (hwrite), an address (haddr), data (hwdata), a data length (hlength), and data start and stop flag signals to the arbiter when performing a write operation. The arbiter determines the memory of the data store by the higher address and writes the data. Arbitration also outputs a grant signal (hcont) to the arithmetic IP unit.
To illustrate the effectiveness of the present invention, the following experimental demonstration was performed. The test data is a full-color remote sensing image with the size of 4096×4096, and the resolution is 5 m. The optical remote sensing ship target detection and identification algorithm is realized by carrying out algorithm mapping on an Xilinx XC2V3000 FPGA based on the framework of the invention, and the experimental result is shown in table 1.
TABLE 1
Compared with the traditional data driving type architecture, the architecture provided by the invention has the advantage that the storage resource and the logic resource consumption based on the architecture mapping system are mainly analyzed. As can be seen from experimental results, compared with the traditional data driving type architecture, the image processing architecture provided by the invention has less resource occupation and higher memory access efficiency.
In summary, the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The mixed heterogeneous on-chip architecture based on the matrix network is characterized by comprising an operation IP unit, a storage unit, a CPU main control unit and an arbitration unit;
the plurality of operation IP units are formed by disassembling a ship target detection algorithm based on remote sensing images into a plurality of basic image processing operation units;
the storage unit is used for storing data;
the CPU main control unit is used for controlling each operation IP to jump the algorithm state according to the operation steps in the ship target detection algorithm flow;
the arbitration unit is used for:
when the reading operation is carried out, the operation IP unit sends a request to the arbitration unit, and after receiving the reading request, the arbiter reads data from the corresponding storage unit according to the priority sequence of each operation IP unit and sends the data to the operation IP unit;
when writing operation is carried out, the operation IP unit sends a request to the arbitration unit, and the arbitration unit stores data output by the operation IP unit into a corresponding storage unit according to the priority order of each operation IP unit.
2. The hybrid heterogeneous on-chip architecture based on a matrix network of claim 1, wherein the arithmetic IP unit comprises:
(1) The overlapped whole window operation IP unit is used for carrying out translation scanning on the rectangular window data block, processing all data in the window, and realizing expansion, corrosion and filtering operations by overlapping two adjacent windows;
(2) The non-overlapping whole window operation IP unit carries out translation scanning on the rectangular window data block, takes all data in the windows for processing, and realizes the function of a lighting module without overlapping between two adjacent windows;
(3) The non-overlapping partial window operation IP unit is used for carrying out translation scanning on the rectangular window data block, taking partial data in the windows for processing, and realizing the function of a fine confirmation module without overlapping between two adjacent windows;
(4) The single pixel traversal operation IP unit is used for traversing each pixel and processing the pixel to realize the function of a histogram statistics module;
(5) The overlapping adjacent operation IP unit extracts information according to the association degree between pixels, and the irregular areas can be overlapped with each other to realize the function of a connected domain extraction module;
(6) And the non-overlapping adjacent operation IP unit extracts information according to the association degree between pixels, and the areas are irregular and non-overlapping, so that the SOBEL module function is realized.
3. The hybrid heterogeneous on-chip architecture of claim 2, wherein the overlapping integer window processing operations IP unit is configurable for integer window size and scan stepping, and for a plurality of overlapping integer window operations.
4. A hybrid heterogeneous on-chip architecture based on a matrix network according to claim 1 or 2, wherein during a read operation, the operation IP module sends a request to the arbitration unit, and the arbitration unit accesses the corresponding memory and reads the data according to the data length and address.
5. A hybrid heterogeneous on-chip architecture according to claim 1 or 2, wherein during a write operation, the operation IP module sends a request, a write signal, an address, data, a data length, and data start and stop flag signals to the arbitration unit at the same time, and the arbitration unit accesses the corresponding memory unit and writes the data accordingly.
6. The architecture of claim 1 or 2, wherein when two similar algorithm steps with different configuration parameters need to be processed, the CPU main control unit performs parameter configuration on the same operation IP unit capable of implementing the algorithm step, and controls the operation IP unit to complete the two similar algorithm steps in a time-sharing manner.
7. A hybrid heterogeneous on-chip architecture according to claim 1 or 2, wherein when one algorithm step uses output data of another algorithm step and the two algorithm steps have output data of other identical algorithm steps as input, the CPU master unit invokes two operation IP units executing the corresponding algorithm steps and connects the two operation IP units in series, and the latter operation IP unit directly receives output data of the former operation IP unit.
8. A hybrid heterogeneous on-chip architecture based on a matrix network as claimed in claim 1 or 2, wherein said arbitration unit is adapted to store different operation IP unit output data to different locations of the same memory.
9. A hybrid heterogeneous on-chip architecture based on a matrix network according to claim 1 or 2, wherein the memory cells have different memory sizes.
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