CN113111021A - UART master-slave line communication control circuit and method - Google Patents
UART master-slave line communication control circuit and method Download PDFInfo
- Publication number
- CN113111021A CN113111021A CN202110400825.2A CN202110400825A CN113111021A CN 113111021 A CN113111021 A CN 113111021A CN 202110400825 A CN202110400825 A CN 202110400825A CN 113111021 A CN113111021 A CN 113111021A
- Authority
- CN
- China
- Prior art keywords
- uart
- master
- slave
- mos tube
- slaves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 11
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 4
- 230000008054 signal transmission Effects 0.000 claims abstract description 4
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention provides a UART master-slave line communication control circuit and a method, comprising the following steps: the system comprises a master UART and a plurality of slaves provided with UART interfaces; the master UART and the plurality of slaves respectively carry out one-to-many bidirectional signal transmission through a receiving end and a transmitting end; a gating MOS tube is arranged between the receiving end of the host and the sending end of each slave; the G pole of the gating MOS tube is connected with an enable pin of the master UART; the gating MOS tube is switched on and off by controlling the level of the enabling pin, so that the on-off of the master UART and the slave machine is controlled. The invention realizes the UART communication between one host and a plurality of slaves, and enlarges the application range of the UART.
Description
Technical Field
The invention belongs to the technical field of communication control, and particularly relates to a UART master-slave line communication control circuit and a method.
Background
UART, a universal asynchronous transceiver transmitter, is generally used for communication and debugging of electronic devices, and employs an asynchronous full-duplex communication protocol to convert parallel data into serial data for transmission and reception. The current UART full-duplex communication structure is shown in fig. 1, the line hardware connection is relatively simple, the UART transmits data in a full-duplex manner, and the simplest connection method is only 3 lines. Wherein TX: a transmitting data end, which is to be connected with an RX of a face device; RX: a receiving data end, which is to be connected with TX of a face device; GND: the two devices are ensured to be in common ground and have a uniform reference plane.
When data is sent, parallel data is written into the UART, and the UART sends out the data in series on a wire according to a certain format; when receiving data, the UART detects signals on another wire, and serial collection is put in a buffer, so that the data can be acquired by reading the UART. Therefore, the conventional UART interface only supports one-to-one communication, when one device needs to perform UART communication with a plurality of devices in hardware design, the UART design for one-to-one communication cannot meet the requirement.
Disclosure of Invention
In response to the above-mentioned deficiency of the prior art, the UART interface can save hardware resources, but only supports one-to-one communication, which greatly limits its use. Therefore, the invention provides a UART master-slave line communication control circuit and a method, which can realize one-to-many communication of UART.
In a first aspect, the present invention provides a UART master-slave line communication control circuit, including: the system comprises a master UART and a plurality of slaves provided with UART interfaces; the master UART and the plurality of slaves respectively carry out one-to-many bidirectional signal transmission through a receiving end and a transmitting end; a gating MOS tube is arranged between the receiving end of the host and the sending end of each slave; the G pole of the gating MOS tube is connected with an enable pin of the master UART; the gating MOS tube is switched on and off by controlling the level of the enabling pin, so that the on-off of the master UART and the slave machine is controlled.
In a second aspect, the present invention provides a UART master-slave line communication control method, including:
when the master UART is disconnected from the current slave machine, the master UART is cut off from the communication between the master UART and the current slave machine by controlling the level of the enable pin to stop the gated MOS tube connected with the sending end of the current slave machine;
when the master UART communicates with the current slave, the gating MOS tube connected with the sending end of the current slave is gated through the enabling pin, so that the link from the sending end of the current slave to the receiving end of the master UART is conducted, and the link from the sending end of the slave to the receiving end of the master UART is controlled to be cut off.
The beneficial effect of the invention is that,
the UART master-slave line communication control circuit and the method thereof provided by the invention realize UART communication between a host and a plurality of slave machines, do not need to add an extension chip and are convenient to realize; meanwhile, the phenomenon that the slave machine sends messages in disorder and pulls the bus by mistake can be avoided; meanwhile, the damage of hardware pins under the condition of one master and multiple slaves is prevented, and the application range of the UART is expanded.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of the prior art structure of the present invention.
Fig. 2 is a schematic structural diagram of an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
Example 1
As shown in fig. 2, the present embodiment provides a UART master-slave line communication control circuit, which includes: the system comprises a master UART and a plurality of slaves provided with UART interfaces; the master UART and the plurality of slaves respectively carry out one-to-many bidirectional signal transmission through a receiving end and a transmitting end; a gating MOS tube is arranged between the receiving end of the host and the sending end of each slave; the G pole of the gating MOS tube is connected with an enable pin of the master UART; the gating MOS tube is switched on and off by controlling the level of the enabling pin, so that the on-off of the master UART and the slave machine is controlled.
In this embodiment, when the master sends information, all the slaves can receive the information, and when the master communicates with a single slave, the master only needs to control the enable signal at the master end to turn on the MOS connected to the slave sending end and turn off the MOS connected to the other slave sending ends, so as to realize one-to-one communication between the master and the slave. Meanwhile, the phenomenon that the slave machine sends messages in disorder and pulls the bus by mistake can be avoided; and simultaneously, the damage of hardware pins under the condition of one master and multiple slaves is prevented.
For clearly explaining the implementation of the design method, the implementation steps are explained in conjunction with fig. 2. The method comprises the following specific steps:
1) when the master UART is not communicated with the slave, the level of an enable pin (EN) is controlled; the MOS connected with the sending end of the slave is cut off; and the master UART is isolated from communicating with all the slaves.
2) When the master UART communicates with the slave UART0, the MOS connected with the transmitting end of the slave UART0 is gated through an enable pin (EN 0); enabling the slave UART0 transmit-to-master UART receive-side link.
3) Meanwhile, MOS connected with the sending ends of other slaves is controlled through an EN pin; the link from the other slave sending end to the master UART receiving end is cut off, so that the situation that when the master UART communicates with the slave UART0, the other slaves send messages randomly and pull the bus by mistake to influence the communication between the master UART and the slave UART0 is prevented. The master UART may then communicate with the slave UART0 for normal transceiving.
4) When the master UART communicates with the slave UART1, the MOS connected to the slave UART1 is gated through EN1 and the other MOS is disabled. Enabling master UART to communicate with slave UART 1.
5) And by analogy, one master multi-slave UART communication can be realized.
The MOS is controlled to be switched on or switched off through an enabling pin of the host, so that the on-off of a slave TX end and a host RX link is controlled, and the slave needing communication is selected by the host; thereby implementing a master multi-slave UART communication. An expansion chip is not required to be added, so that the realization is convenient; meanwhile, the phenomenon that the slave machine sends messages in disorder and pulls the bus by mistake can be avoided; and simultaneously, the damage of hardware pins under the condition of one master and multiple slaves is prevented.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (2)
1. A UART master-slave line communication control circuit, comprising: the system comprises a master UART and a plurality of slaves provided with UART interfaces; the master UART and the plurality of slaves respectively carry out one-to-many bidirectional signal transmission through a receiving end and a transmitting end; a gating MOS tube is arranged between the receiving end of the host and the sending end of each slave; the G pole of the gating MOS tube is connected with an enable pin of the master UART; the gating MOS tube is switched on and off by controlling the level of the enabling pin, so that the on-off of the master UART and the slave machine is controlled.
2. A UART master-slave line communication control method is characterized by comprising the following steps:
when the master UART is disconnected from the current slave machine, the master UART is cut off from the communication between the master UART and the current slave machine by controlling the level of the enable pin to stop the gated MOS tube connected with the sending end of the current slave machine;
when the master UART communicates with the current slave, the gating MOS tube connected with the sending end of the current slave is gated through the enabling pin, so that the link from the sending end of the current slave to the receiving end of the master UART is conducted, and the link from the sending end of the slave to the receiving end of the master UART is controlled to be cut off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110400825.2A CN113111021A (en) | 2021-04-14 | 2021-04-14 | UART master-slave line communication control circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110400825.2A CN113111021A (en) | 2021-04-14 | 2021-04-14 | UART master-slave line communication control circuit and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113111021A true CN113111021A (en) | 2021-07-13 |
Family
ID=76717606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110400825.2A Pending CN113111021A (en) | 2021-04-14 | 2021-04-14 | UART master-slave line communication control circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113111021A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115499032A (en) * | 2022-09-01 | 2022-12-20 | 上海盛本智能科技股份有限公司 | One-to-many UART communication method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120008667A1 (en) * | 2010-07-07 | 2012-01-12 | Lsis Co., Ltd. | Communication apparatus and method in plc |
| CN111625491A (en) * | 2020-06-29 | 2020-09-04 | 科华恒盛股份有限公司 | Multi-machine serial communication device and method |
-
2021
- 2021-04-14 CN CN202110400825.2A patent/CN113111021A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120008667A1 (en) * | 2010-07-07 | 2012-01-12 | Lsis Co., Ltd. | Communication apparatus and method in plc |
| CN111625491A (en) * | 2020-06-29 | 2020-09-04 | 科华恒盛股份有限公司 | Multi-machine serial communication device and method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115499032A (en) * | 2022-09-01 | 2022-12-20 | 上海盛本智能科技股份有限公司 | One-to-many UART communication method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106453383B (en) | UART-based master-slave multi-machine communication system and method | |
| US9160451B2 (en) | Active optical cable connector plug and active optical cable using same | |
| CN101788972B (en) | System and method for transmitting data | |
| CN108111382B (en) | Communication device based on I3C bus and communication method thereof | |
| CN105141491B (en) | RS485 communication circuit and method for realizing spontaneous self-receiving | |
| CN105760328B (en) | A kind of VR equipment USB master-slave switching method and system | |
| CN102591826A (en) | Method and system for detecting and asserting bus speed condition in a USB isolating device | |
| CN101977082B (en) | Optical receiving and transmitting module, optical transmitting device and optical transmitting method | |
| CN102347830A (en) | Synchronization method and system of Ethernet | |
| CN113111021A (en) | UART master-slave line communication control circuit and method | |
| CN102929830A (en) | Software simulation rapid communication protocol | |
| CN113792003A (en) | Single bus communication unit, system and method | |
| CN210867765U (en) | Remote control network switch | |
| CN210639609U (en) | RS232 and RS485 adaptive multiplexing circuit, module and equipment | |
| CN108920394A (en) | A kind of backboard serial bus communication method and system | |
| CN218772141U (en) | Dual-processor circuit and control mainboard of distributed control system | |
| CN107070547B (en) | A kind of CPCI type gigabit Ethernet device with failure monitoring ability | |
| CN103268301A (en) | Automatic-flowing half-duplex UART interface circuit | |
| CN206805761U (en) | A kind of data transmission device with master and slave wireless module | |
| CN107980223B (en) | Ethernet interconnection circuit and device | |
| CN108494889B (en) | Communication circuit based on I2C bus and debugging method | |
| CN209860929U (en) | Communication bus structure | |
| CN209842613U (en) | Data transmission device | |
| CN101662405B (en) | Communication circuit of CAN bus | |
| CN209767567U (en) | Multi-master RS485 bus system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210713 |