CN113078995A - High-complexity four-dimensional hyperchaotic circuit - Google Patents
High-complexity four-dimensional hyperchaotic circuit Download PDFInfo
- Publication number
- CN113078995A CN113078995A CN202110463487.7A CN202110463487A CN113078995A CN 113078995 A CN113078995 A CN 113078995A CN 202110463487 A CN202110463487 A CN 202110463487A CN 113078995 A CN113078995 A CN 113078995A
- Authority
- CN
- China
- Prior art keywords
- operational amplifier
- resistor
- input end
- negative input
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a high-complexity four-dimensional hyperchaotic circuit which consists of four channel circuits, wherein each of a first channel circuit, a second channel circuit and a third channel circuit consists of a multiplier, an operational amplifier, a resistor and a capacitor; the circuit topology structure provided by the invention is simple, does not contain complex nonlinear terms, is easy to realize, has obvious advantages in three aspects of attractor complexity, system parameter robustness and signal bandwidth, and has outstanding engineering application potential.
Description
Technical Field
The invention relates to the field of nonlinear circuits, in particular to a high-complexity four-dimensional hyperchaotic circuit.
Background
The development of natural science and technology is making the traditional discipline division and research method change profoundly, the interdiffusion between disciplines and the combination of traditional disciplines and new technology of the day-new-month-difference promote the inoculation and development of a large number of comprehensive marginal disciplines. One important characteristic of the development is 'nonlinearity', the development of nonlinear science fundamentally affects and changes the whole scientific system, and the research of nonlinear science not only has great scientific significance, but also has wide application prospect. Generally, the subject of nonlinear science includes studies of chaos, bifurcation, typing, solitons, and complexity, wherein the studies of chaos account for a great deal of components. The nonlinear circuit, namely the chaotic circuit, reveals the real law and the basic characteristics of the motion of the nonlinear system and reflects the dynamic characteristics of the system. Due to the randomness of the chaotic signal, the characteristic of a continuous broadband power spectrum, the sensitive dependence of the chaotic system on initial test conditions, the easy generation of the chaotic signal, the difficulty in prediction and separation through common time domain and frequency domain processing and the like, the chaotic signal is particularly suitable for the fields of secret communication and information encryption, and plays an important role in the fields of marine electricity, ship systems, aerospace engineering and the like.
The current chaotic/hyper-chaotic systems/circuits have outstanding properties in some aspects (mainly focused complexity), but the high complexity of these systems mainly comes from the coupling of multiple complex nonlinear terms, which may cause certain difficulties for specific circuit implementations. At the same time, these systems are difficult to implement in terms of engineering applications (including system complexity, parameter robustness, signal bandwidth) while having good properties. The two points prevent the practical application of the chaotic system/circuit in engineering.
Disclosure of Invention
The invention aims to provide a high-complexity four-dimensional hyperchaotic circuit which is used for solving the problem of difficulty in realizing the circuit engineering of a hyperchaotic system.
In order to achieve the above object, the present invention provides a high complexity four-dimensional hyper-chaotic circuit, comprising a first channel circuit, a second channel circuit, a third channel circuit and a fourth channel circuit, wherein:
the first channel circuit comprises a multiplier A1, an operational amplifier U1A, an operational amplifier U1B, an operational amplifier U1C, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7 and a capacitor C1;
the output end of the multiplier a1 is connected to the resistor R3, the resistor R3 is connected in parallel with the resistor R1 and the resistor R2 and then is connected to the negative input end of the operational amplifier U1A, the output end of the operational amplifier U1A is fed back to the negative input end of the operational amplifier U1A through the resistor R4, the output end of the operational amplifier U1A is connected to the negative input end of the operational amplifier U1B through the resistor R5, the output end of the operational amplifier U1B is fed back to the negative input end of the operational amplifier U1B through the capacitor C1, the output end of the operational amplifier U1B is connected to the negative input end of the operational amplifier U1C through the resistor R6, and the output end of the operational amplifier U1C is fed back to the negative input end of the operational amplifier U1C through the resistor R7;
the second channel circuit comprises a multiplier A2, an operational amplifier U2A, an operational amplifier U2B, an operational amplifier U2C, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a capacitor C2;
the output end of the multiplier a2 is connected to the resistor R9, the resistor R9 is connected in parallel with the resistor R8 and the resistor R10 and then is connected to the negative input end of the operational amplifier U2A, the output end of the operational amplifier U2A is fed back to the negative input end of the operational amplifier U2A through the resistor R11, the output end of the operational amplifier U2A is connected to the negative input end of the operational amplifier U2B through the resistor R12, the output end of the operational amplifier U2B is fed back to the negative input end of the operational amplifier U2B through the capacitor C2, the output end of the operational amplifier U2B is connected to the negative input end of the operational amplifier U2C through the resistor R13, and the output end of the operational amplifier U2C is fed back to the negative input end of the operational amplifier U2C through the resistor R14;
the third channel circuit comprises a multiplier A3, a multiplier A4, an operational amplifier U3A, an operational amplifier U3B, an operational amplifier U3C, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21 and a capacitor C3;
the output end of the multiplier A3 is connected to the resistor R15, the output end of the multiplier a4 is connected to the resistor R17, the resistor R15 is connected in parallel with the resistor R16 and the resistor R17 and then connected to the negative input end of the operational amplifier U3A, the output end of the operational amplifier U3A is fed back to the negative input end of the operational amplifier U3A through the resistor R18, the output end of the operational amplifier U3A is connected to the negative input end of the operational amplifier U3B through the resistor R19, the output end of the operational amplifier U3B is fed back to the negative input end of the operational amplifier U3B through the capacitor C3, the output end of the operational amplifier U3B is connected to the negative input end of the operational amplifier U3C through the resistor R20, and the output end of the operational amplifier U3C is fed back to the negative input end of the operational amplifier U3C through the resistor R21;
the fourth channel circuit comprises an operational amplifier U4A, an operational amplifier U4B, a resistor R22, a resistor R23, a resistor R24 and a capacitor C4;
the resistor R22 is connected to the negative input terminal of the operational amplifier U4A, the output terminal of the operational amplifier U4A is fed back to the negative input terminal of the operational amplifier U4A through the resistor R23, the output terminal of the operational amplifier U4A is connected to the negative input terminal of the operational amplifier U4B through the resistor R24, and the output terminal of the operational amplifier U4B is fed back to the negative input terminal of the operational amplifier U4B through the capacitor C4.
Further, in the high complexity four-dimensional hyper-chaotic circuit, there are also x connection lines, -x connection lines, y connection lines, -y connection lines, z connection lines and w connection lines, wherein:
in an x connection line, the output end of the operational amplifier U1B is fed back to the negative input end of the operational amplifier U2A through the resistor R10, and the output end of the operational amplifier U1B is respectively connected to the input end of the multiplier A3 and the input end of the multiplier a 4;
in the-x connection line, the output end of the operational amplifier U1C is fed back to the negative input end of the operational amplifier U4A through the resistor R22, and the output end of the operational amplifier U1C is fed back to the input end of the multiplier a 2;
in a y connection line, the output end of the operational amplifier U2B is fed back to the negative input end of the operational amplifier U1A through the resistor R1, and the output end of the operational amplifier U2B is connected to the input end of the multiplier a1 and the input end of the multiplier a4 respectively;
in the-y connection line, the output end of the operational amplifier U2C is fed back to the negative input end of the operational amplifier U2A through the resistor R8;
in a z connection line, the output end of the operational amplifier U3B is fed back to the negative input end of the operational amplifier U3A through the resistor R16, and the output end of the operational amplifier U3B is respectively connected to the input end of the multiplier a1 and the input end of the multiplier a 2;
in the w connection line, the output of the amplfier U4B is connected to the input of the multiplier A3.
Further, in the high-complexity four-dimensional hyperchaotic circuit, the operational amplifier U1A, the operational amplifier U1B, the operational amplifier U1C, the operational amplifier U2A, the operational amplifier U2B, the operational amplifier U2C, the operational amplifier U3A, the operational amplifier U3B, the operational amplifier U3C, the operational amplifier U4A and the operational amplifier U4B are all four-way operational amplifiers.
Further, in the high-complexity four-dimensional hyperchaotic circuit, the model of the four-way operational amplifier is LF347 BN.
Compared with the prior art, the invention has the following beneficial effects: the circuit provided by the invention is easy to realize, has a simpler system topological structure, is more complex in system dynamics behavior, and has obvious advantages in three aspects of initial value sensitivity, signal bandwidth and system parameter robustness, which are strongly related to engineering application.
Drawings
FIG. 1 is a schematic circuit diagram of a high-complexity four-dimensional hyperchaotic circuit according to the present invention;
FIG. 2 is a projection of a hyperchaotic attractor of a system implemented by the high-complexity four-dimensional hyperchaotic circuit in the invention on a space x-y-z;
FIG. 3 is a projection of a hyper-chaotic attractor of a system implemented by a high complexity four-dimensional hyper-chaotic circuit in the space x-y-w;
FIG. 4 is a projection of a hyper-chaotic attractor of a system implemented by a high complexity four-dimensional hyper-chaotic circuit in the space x-z-w;
FIG. 5 is a projection of a hyperchaotic attractor of a system implemented by the high complexity four-dimensional hyperchaotic circuit in the space y-z-w.
Detailed Description
The high complexity four-dimensional hyper-chaotic circuit of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that a person skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
In the description of the present invention, it should be noted that, for the terms of orientation, such as "central", "lateral", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., it indicates that the orientation and positional relationship shown in the drawings are based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated without limiting the specific scope of protection of the present invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
As shown in fig. 1, the present invention provides a high complexity four-dimensional hyper-chaotic circuit, which includes a first channel circuit, a second channel circuit, a third channel circuit and a fourth channel circuit, wherein:
the first channel circuit comprises a multiplier A1, an operational amplifier U1A, an operational amplifier U1B, an operational amplifier U1C, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7 and a capacitor C1;
the output end of the multiplier A1 is connected with a resistor R3, the resistor R3 is connected with a resistor R1 and a resistor R2 in parallel and then connected to the negative input end of an operational amplifier U1A, the output end of the operational amplifier U1A is fed back to the negative input end of the operational amplifier U1A through a resistor R4, the output end of the operational amplifier U1A is connected with the negative input end of an operational amplifier U1B through a resistor R5, the output end of the operational amplifier U1B is fed back to the negative input end of an operational amplifier U1B through a capacitor C1, the output end of the operational amplifier U1B is connected with the negative input end of an operational amplifier U1C through a resistor R6, and the output end of the operational amplifier U1C is fed back to the negative input end of the operational amplifier U1C;
the second channel circuit comprises a multiplier A2, an operational amplifier U2A, an operational amplifier U2B, an operational amplifier U2C, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a capacitor C2;
the output end of the multiplier A2 is connected with a resistor R9, the resistor R9 is connected with a resistor R8 and a resistor R10 in parallel and then connected to the negative input end of an operational amplifier U2A, the output end of the operational amplifier U2A is fed back to the negative input end of the operational amplifier U2A through a resistor R11, the output end of the operational amplifier U2A is connected with the negative input end of an operational amplifier U2B through a resistor R12, the output end of the operational amplifier U2B is fed back to the negative input end of an operational amplifier U2B through a capacitor C2, the output end of the operational amplifier U2B is connected with the negative input end of an operational amplifier U2C through a resistor R13, and the output end of the operational amplifier U2C is fed back to the negative input end of the operational amplifier U2C;
the third channel circuit comprises a multiplier A3, a multiplier A4, an operational amplifier U3A, an operational amplifier U3B, an operational amplifier U3C, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21 and a capacitor C3;
the output end of a multiplier A3 is connected with a resistor R15, the output end of a multiplier A4 is connected with a resistor R17, a resistor R15 is connected with a resistor R16 and a resistor R17 in parallel and then is connected with the negative input end of an operational amplifier U3A, the output end of an operational amplifier U3A is fed back to the negative input end of the operational amplifier U3A through a resistor R18, the output end of the operational amplifier U3A is connected with the negative input end of the operational amplifier U3B through a resistor R19, the output end of the operational amplifier U3B is fed back to the negative input end of an operational amplifier U3B through a capacitor C3, the output end of the operational amplifier U3B is connected with the negative input end of an operational amplifier U3C through a resistor R20 and then is fed back to the negative input end of an operational amplifier U3C through a resistor R63;
the fourth channel circuit comprises an operational amplifier U4A, an operational amplifier U4B, a resistor R22, a resistor R23, a resistor R24 and a capacitor C4;
the resistor R22 is connected with the negative input end of the operational amplifier U4A, the output end of the operational amplifier U4A is fed back to the negative input end of the operational amplifier U4A through the resistor R23, the output end of the operational amplifier U4A is connected with the negative input end of the operational amplifier U4B after being connected through the resistor R24, and the output end of the operational amplifier U4B is fed back to the negative input end of the operational amplifier U4B through the capacitor C4.
Further, as shown in fig. 1, in the present embodiment, there are also an x connection line, a y connection line, a z connection line, and a w connection line, wherein:
in the x connection line, the output end of the operational amplifier U1B is fed back to the negative input end of the operational amplifier U2A through a resistor R10, and the output end of the operational amplifier U1B is respectively connected to the input end of the multiplier A3 and the input end of the multiplier a 4;
in the-x connection line, the output end of the operational amplifier U1C is fed back to the negative input end of the operational amplifier U4A through a resistor R22, and the output end of the operational amplifier U1C is connected to the input end of the multiplier a 2;
in the y connection line, the output end of the operational amplifier U2B is fed back to the negative input end of the operational amplifier U1A through a resistor R1, and the output end of the operational amplifier U2B is connected to the input end of the multiplier a1 and the input end of the multiplier a4 respectively;
in the-y connection line, the output end of the operational amplifier U2C is fed back to the negative input end of the operational amplifier U2A through a resistor R8;
in a z connection line, the output end of the operational amplifier U3B is fed back to the negative input end of the operational amplifier U3A through a resistor R16, and the output end of the operational amplifier U3B is respectively connected to the input end of the multiplier A1 and the input end of the multiplier A2;
in the w connection, the output of the amplfier U4B is connected to the input of the multiplier A3.
Further, in this embodiment, the operational amplifier U1A, the operational amplifier U1B, the operational amplifier U1C, the operational amplifier U2A, the operational amplifier U2B, the operational amplifier U2C, the operational amplifier U3A, the operational amplifier U3B, the operational amplifier U3C, the operational amplifier U4A and the operational amplifier U4B are all four-way operational amplifiers with model number LF347BN, which has the advantages of low price and stable operation.
In the specific implementation, as shown in fig. 1, a resistor R1 is 2.56k Ω, a resistor R2 is 2.56k Ω, a resistor R3 is 0.813 Ω, a resistor R4 is 10k Ω, a resistor R5 is 10k Ω, a resistor R6 is 10k Ω, a resistor R7 is 10k Ω, a capacitor C1 is 1nF, a resistor R8 is 2.1k Ω, a resistor R9 is 1k Ω, a resistor R10 is 6.7k Ω, a resistor R11 is 10k Ω, a resistor R12 is 10k Ω, a resistor R13 is 10k Ω, a resistor R14 is 10k Ω, a capacitor C2 is 1nF, a resistor R2 is 2.86k Ω, a resistor R2 is 2.43k, a resistor R2 is 1k Ω, a resistor R2 is 10k Ω, a resistor R2 k is 10k Ω, a resistor nF 72 k, a resistor R2 k is 10 nF, a capacitor C1 nF, and a capacitor C2 is 10 nF, nF 3k, nF 3C 1k, nF 3C 1k is 10k, nF 3C 1. The parameters of the multiplier A1, the multiplier A2, the multiplier A3 and the multiplier A4 are all 100 mV/V.0V. The state variables x, y, z, -x, -y, -z and w are present in the x connection line, -x connection line, y connection line, -y connection line, z connection line and w connection line, respectively, formed after the wiring in fig. 1.
The hyperchaotic system realized by the circuit is described by the following kinetic equation:
wherein x, y, z and w are state variables, and a, b, c, d, e, r and k are system parameters. When the system parameters (a, b, c, D, e, r, k) — (39, 48,15,41,123, -100, -35), the system is in a hyper-chaotic state, Lyapunov indexes are (LE1, LE2, LE3, LE4) — (12.876,6.346,0, -50.641), the state variable output end of the circuit is connected to an oscilloscope, that is, the state variables x, y, z and w are connected to A, B, C of the oscilloscope, and the projection of the D-end hyper-chaotic attractor in space is shown in fig. 2, fig. 3, fig. 4 and fig. 5. Wherein: FIG. 2 is a projection of a hyperchaotic attractor in space x-y-z; FIG. 3 is a projection of a hyperchaotic attractor in space x-y-w; FIG. 4 is a projection of a hyperchaotic attractor in space x-z-w; FIG. 5 is a projection of a hyperchaotic attractor in space y-z-w. The system is transformed from a classical chaotic Qi system: on the basis of keeping the basic topological structure of the Qi system, the original three-dimensional system is modified into a four-dimensional system by adding a linear item, and a newly added fourth dimension and other dimensions are coupled together by adding a nonlinear item, so that the new four-dimensional autonomous system is obtained.
The four-dimensional nonlinear circuit provided by the invention is used for realizing a new four-dimensional hyper-chaotic system. Compared with the existing system, the system has better properties in the aspects related to application, such as initial value sensitivity, bandwidth, parameter robustness and the like, for example, experiments prove that the system (1) has the largest Kaplan-Yorke dimension (the best result before comparison is improved by 16.4% relatively), the bandwidth is 104Hz (the best result before comparison is improved by 25.0% relatively), and the system has outstanding engineering application value.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A high-complexity four-dimensional hyperchaotic circuit is characterized by comprising a first channel circuit, a second channel circuit, a third channel circuit and a fourth channel circuit, wherein:
the first channel circuit comprises a multiplier A1, an operational amplifier U1A, an operational amplifier U1B, an operational amplifier U1C, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7 and a capacitor C1;
the output end of the multiplier a1 is connected to the resistor R3, the resistor R3 is connected in parallel with the resistor R1 and the resistor R2 and then is connected to the negative input end of the operational amplifier U1A, the output end of the operational amplifier U1A is fed back to the negative input end of the operational amplifier U1A through the resistor R4, the output end of the operational amplifier U1A is connected to the negative input end of the operational amplifier U1B through the resistor R5, the output end of the operational amplifier U1B is fed back to the negative input end of the operational amplifier U1B through the capacitor C1, the output end of the operational amplifier U1B is connected to the negative input end of the operational amplifier U1C through the resistor R6, and the output end of the operational amplifier U1C is fed back to the negative input end of the operational amplifier U1C through the resistor R7;
the second channel circuit comprises a multiplier A2, an operational amplifier U2A, an operational amplifier U2B, an operational amplifier U2C, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a capacitor C2;
the output end of the multiplier a2 is connected to the resistor R9, the resistor R9 is connected in parallel with the resistor R8 and the resistor R10 and then is connected to the negative input end of the operational amplifier U2A, the output end of the operational amplifier U2A is fed back to the negative input end of the operational amplifier U2A through the resistor R11, the output end of the operational amplifier U2A is connected to the negative input end of the operational amplifier U2B through the resistor R12, the output end of the operational amplifier U2B is fed back to the negative input end of the operational amplifier U2B through the capacitor C2, the output end of the operational amplifier U2B is connected to the negative input end of the operational amplifier U2C through the resistor R13, and the output end of the operational amplifier U2C is fed back to the negative input end of the operational amplifier U2C through the resistor R14;
the third channel circuit comprises a multiplier A3, a multiplier A4, an operational amplifier U3A, an operational amplifier U3B, an operational amplifier U3C, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21 and a capacitor C3;
the output end of the multiplier A3 is connected to the resistor R15, the output end of the multiplier a4 is connected to the resistor R17, the resistor R15 is connected in parallel with the resistor R16 and the resistor R17 and then connected to the negative input end of the operational amplifier U3A, the output end of the operational amplifier U3A is fed back to the negative input end of the operational amplifier U3A through the resistor R18, the output end of the operational amplifier U3A is connected to the negative input end of the operational amplifier U3B through the resistor R19, the output end of the operational amplifier U3B is fed back to the negative input end of the operational amplifier U3B through the capacitor C3, the output end of the operational amplifier U3B is connected to the negative input end of the operational amplifier U3C through the resistor R20, and the output end of the operational amplifier U3C is fed back to the negative input end of the operational amplifier U3C through the resistor R21;
the fourth channel circuit comprises an operational amplifier U4A, an operational amplifier U4B, a resistor R22, a resistor R23, a resistor R24 and a capacitor C4;
the resistor R22 is connected to the negative input terminal of the operational amplifier U4A, the output terminal of the operational amplifier U4A is fed back to the negative input terminal of the operational amplifier U4A through the resistor R23, the output terminal of the operational amplifier U4A is connected to the negative input terminal of the operational amplifier U4B through the resistor R24, and the output terminal of the operational amplifier U4B is fed back to the negative input terminal of the operational amplifier U4B through the capacitor C4.
2. The high complexity four dimensional hyper-chaotic circuit as in claim 1, further comprising x connection lines, -x connection lines, y connection lines, -y connection lines, z connection lines, and w connection lines, wherein:
in an x connection line, the output end of the operational amplifier U1B is fed back to the negative input end of the operational amplifier U2A through the resistor R10, and the output end of the operational amplifier U1B is respectively connected to the input end of the multiplier A3 and the input end of the multiplier a 4;
in the-x connection line, the output end of the operational amplifier U1C is fed back to the negative input end of the operational amplifier U4A through the resistor R22, and the output end of the operational amplifier U1C is fed back to the input end of the multiplier a 2;
in a y connection line, the output end of the operational amplifier U2B is fed back to the negative input end of the operational amplifier U1A through the resistor R1, and the output end of the operational amplifier U2B is connected to the input end of the multiplier a1 and the input end of the multiplier a4 respectively;
in the-y connection line, the output end of the operational amplifier U2C is fed back to the negative input end of the operational amplifier U2A through the resistor R8;
in a z connection line, the output end of the operational amplifier U3B is fed back to the negative input end of the operational amplifier U3A through the resistor R16, and the output end of the operational amplifier U3B is respectively connected to the input end of the multiplier a1 and the input end of the multiplier a 2;
in the w connection line, the output of the amplfier U4B is connected to the input of the multiplier A3.
3. The high-complexity four-dimensional hyperchaotic circuit according to claim 1, characterized in that the operational amplifier U1A, operational amplifier U1B, operational amplifier U1C, operational amplifier U2A, operational amplifier U2B, operational amplifier U2C, operational amplifier U3A, operational amplifier U3B, operational amplifier U3C, operational amplifier U4A and operational amplifier U4B are all four-way operational amplifiers.
4. The high complexity four-dimensional hyperchaotic circuit according to claim 3 wherein the four-way operational amplifier is of type LF347 BN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110463487.7A CN113078995A (en) | 2021-04-23 | 2021-04-23 | High-complexity four-dimensional hyperchaotic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110463487.7A CN113078995A (en) | 2021-04-23 | 2021-04-23 | High-complexity four-dimensional hyperchaotic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113078995A true CN113078995A (en) | 2021-07-06 |
Family
ID=76618891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110463487.7A Pending CN113078995A (en) | 2021-04-23 | 2021-04-23 | High-complexity four-dimensional hyperchaotic circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113078995A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105681021A (en) * | 2016-04-06 | 2016-06-15 | 仓诗建 | Three-dimensional generalized dissipative Hamilton system chaotic circuit |
| CN105827392A (en) * | 2016-04-28 | 2016-08-03 | 李博雅 | Simplest series memristor circuit |
| CN106059744A (en) * | 2016-05-22 | 2016-10-26 | 姜语锐 | Sprott B chaotic system linearization method and circuit |
| CN208508912U (en) * | 2018-08-23 | 2019-02-15 | 南京信息工程大学 | A kind of user-network signal reception circuit |
| CN110113146A (en) * | 2019-06-04 | 2019-08-09 | 齐鲁理工学院 | A kind of analog circuit of chaotic systems with fractional order |
| CN112152573A (en) * | 2019-06-28 | 2020-12-29 | 天津科技大学 | Conservative system with four clusters of chaotic streams and circuit implementation thereof |
-
2021
- 2021-04-23 CN CN202110463487.7A patent/CN113078995A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105681021A (en) * | 2016-04-06 | 2016-06-15 | 仓诗建 | Three-dimensional generalized dissipative Hamilton system chaotic circuit |
| CN105827392A (en) * | 2016-04-28 | 2016-08-03 | 李博雅 | Simplest series memristor circuit |
| CN106059744A (en) * | 2016-05-22 | 2016-10-26 | 姜语锐 | Sprott B chaotic system linearization method and circuit |
| CN107453860A (en) * | 2016-05-22 | 2017-12-08 | 杨景美 | Sprott B chaos systems are linearized as the secondary and circuit of quadratic term |
| CN107453859A (en) * | 2016-05-22 | 2017-12-08 | 杨景美 | Sprott B chaos systems are linearized as the secondary and circuit of cubic term |
| CN208508912U (en) * | 2018-08-23 | 2019-02-15 | 南京信息工程大学 | A kind of user-network signal reception circuit |
| CN110113146A (en) * | 2019-06-04 | 2019-08-09 | 齐鲁理工学院 | A kind of analog circuit of chaotic systems with fractional order |
| CN112152573A (en) * | 2019-06-28 | 2020-12-29 | 天津科技大学 | Conservative system with four clusters of chaotic streams and circuit implementation thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DIOP | From the geometry to the algebra of nonlinear observability | |
| Long et al. | Fixed-time synchronization for delayed inertial complex-valued neural networks | |
| CN105681021B (en) | A kind of chaos circuit of Three Dimensional Generalized dissipation Hamilton system | |
| Grabowski | Isomorphisms and ideals of the Lie algebras of vector fields | |
| Li et al. | Hyperchaos from two coupled Wien‐bridge oscillators | |
| CN113078995A (en) | High-complexity four-dimensional hyperchaotic circuit | |
| CN112422263B (en) | Generalized Sprott-A system with three-dimensional 3 x 2 cluster conservative chaotic stream and circuit implementation thereof | |
| Rennie | Summability for nonunital spectral triples | |
| di Bernardo | Normal forms of border collisions in high-dimensional nonsmooth maps | |
| Bridy | The Artin-Mazur zeta function of a dynamically affine rational map in positive characteristic | |
| Liu et al. | Structural balance for discrete-time complex dynamical network associated with the controlled nodes | |
| CN109347615A (en) | Two chaos systems switching building method and analog circuit based on fractional order Lorenz system | |
| Yang et al. | Horseshoe chaos and topological entropy estimate in a simple power system | |
| Carlet | Constructing balanced functions with optimum algebraic immunity | |
| Kargin | The norm of products of free random variables | |
| Shuai et al. | Maximum hyperchaos in chaotic nonmonotonic neuronal networks | |
| Brayton et al. | A theorem on inverses of convex sets of real matrices with application to the worst case DC problem | |
| Malinen | Discrete time H∞ algebraic Riccati equations | |
| Zhang et al. | Generalized Reversibility of Topological Dynamical Systems and Cellular Automata. | |
| CN109543313A (en) | The circuit model of hyperchaotic system based on memristor feedback | |
| Evans | Equivalence and perpendicularity of local field Gaussian measures | |
| Xiao | Hurwitz-Schur stability test of interval bivariate polynomials | |
| CN109474416A (en) | A kind of hyperchaos signal generating circuit containing hiding attractor | |
| Meng et al. | Exponential stability analysis of Cohen-Grossberg neural networks with time-varying delays | |
| Brockett et al. | Application of system theory to power processing problems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20220104 Address after: 215501 356, No. 21-59, Suolan South Road, Changzhou City, Jiangsu Province Applicant after: Yibao (Suzhou) Intelligent Robot Technology Co.,Ltd. Address before: 200093 No. 516, military road, Shanghai, Yangpu District Applicant before: University of Shanghai for Science and Technology |
|
| TA01 | Transfer of patent application right | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210706 |
|
| RJ01 | Rejection of invention patent application after publication |