CN113078133A - Multilayer wiring adapter plate and preparation method thereof - Google Patents

Multilayer wiring adapter plate and preparation method thereof Download PDF

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Publication number
CN113078133A
CN113078133A CN202110616822.2A CN202110616822A CN113078133A CN 113078133 A CN113078133 A CN 113078133A CN 202110616822 A CN202110616822 A CN 202110616822A CN 113078133 A CN113078133 A CN 113078133A
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layer
rdl layer
substrate
embedded
rdl
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冯光建
郭西
黄雷
高群
顾毛毛
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a multilayer wiring adapter plate and a preparation method thereof.A embedded RDL layer with larger thickness which is contacted with a TSV column is prepared in a substrate, so that large current can pass through the embedded RDL layer, the defect that thick metal cannot be prepared in the previous process can be overcome, and the stress caused by the RDL layer can be greatly reduced by the embedded RDL layer which is embedded in the substrate, so that the problems of preparation and stress of the adapter plate can be solved; the first rewiring structure with multilayer wiring on the front surface of the substrate provides a signal integration effect for the chip again through the metal interconnection structure, so that the number of pins of the chip is greatly reduced; the second rewiring structure on the back side of the substrate provides package level interconnection and terminal drop out functionality for the dropped signals.

Description

Multilayer wiring adapter plate and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a multilayer wiring adapter plate and a preparation method thereof.
Background
The multilayer wiring adapter plate is characterized in that a multilayer structure is arranged on a silicon-based material in an RDL metal wiring mode, wherein an RDL metal layer and the RDL metal layer can be isolated by adopting PI or silicon oxide and other insulating layers, and the RDL layer can be manufactured in a Damascus or electroplating mode. The multilayer wiring adapter plate is firstly manufactured by a previous process, such as a copper Damascus process including a nanometer level and a polishing process of an IMD layer, so that the advantage of manufacturing a multilayer wiring structure on a substrate is realized, the substrate cannot deform due to stress brought by a pattern, but the disadvantage of the previous process is that the thickness of a metal wire is too small, the width of the wiring needs to be increased for an interconnection point needing overlarge current, but for a product with thousands of interconnection pins such as an FPGA, basically no extra area is needed for distributing wider wires, and thick metal needs to be designed to meet the requirement.
However, the IMD layer of the Damascus process is usually passivated with silicon oxide, and the thickness is generally not more than 2 μm, and if the required line thickness is in the order of tens of microns, it is obvious that notching the passivation layer with the thickness of 2 μm cannot handle the thicker line preparation.
Therefore, it is necessary to provide a multi-layer wiring adapter board and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a multi-layer wiring interposer and a method for manufacturing the same, which is used to solve the problem that it is difficult to manufacture a multi-layer wiring interposer applicable for transmitting large current and high quality in the prior art.
To achieve the above and other related objects, the present invention provides a multilayer wiring interposer, comprising:
the TSV column and the embedded RDL layer are positioned in the substrate, wherein a first end of the TSV column is exposed at a first face of the substrate, the embedded RDL layer is in contact with a second end of the TSV column, and the embedded RDL layer is exposed at a second face of the substrate;
a first redistribution structure on the first side of the substrate, the first redistribution structure comprising a first RDL layer and a first dielectric layer, and the first RDL layer being in contact with the first end of the TSV pillar;
a metal interconnection structure on the first redistribution structure, the metal interconnection structure including a UBM layer and a passivation layer, the UBM layer being in contact with the first RDL layer, and the passivation layer having a first interconnection hole therein exposing the UBM layer;
the second rewiring structure is located on the second face of the substrate and comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the embedded RDL layer, the thickness of the embedded RDL layer is larger than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer.
Optionally, the thickness of the embedded RDL layer is 5 μm to 50 μm; the thickness of the second RDL layer is 1-5 mu m.
The present invention also provides a multilayer wiring interposer, comprising:
the TSV column, the first embedded RDL layer and the second embedded RDL layer are positioned in the substrate, wherein the first end of the TSV column is in contact with the first embedded RDL layer, the first embedded RDL layer is exposed out of the first face of the substrate, the second embedded RDL layer is in contact with the second end of the TSV column, and the second embedded RDL layer is exposed out of the second face of the substrate;
a first redistribution structure on the first side of the substrate, the first redistribution structure comprising a first RDL layer and a first dielectric layer, the first RDL layer in contact with the first embedded RDL layer, and the first embedded RDL layer having a thickness greater than a thickness of the first RDL layer;
the metal interconnection structure comprises a UBM layer and a passivation layer, the UBM layer is in contact with the first RDL layer, and a first interconnection hole exposing the UBM layer is formed in the passivation layer;
the second rewiring structure is located on the second face of the substrate and comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the second embedded RDL layer, the thickness of the second embedded RDL layer is larger than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer.
Optionally, the thickness of the first embedded RDL layer is 5 μm to 50 μm, and the thickness of the first RDL layer is 1 μm to 5 μm; the thickness of the second embedded RDL layer is 5-50 μm, and the thickness of the second RDL layer is 1-5 μm.
Optionally, M layers of the first RDL layer are included, and M is more than or equal to 2; the second RDL layer comprises N layers, and N is more than or equal to 2.
The invention also provides a preparation method of the multilayer wiring adapter plate, which comprises the following steps:
providing a substrate;
forming a TSV pillar in the substrate, wherein a first end of the TSV pillar is exposed at a first face of the substrate;
forming a first redistribution structure on the first side of the substrate, wherein the first redistribution structure comprises a first RDL layer and a first dielectric layer, and the first RDL layer is in contact with the first end of the TSV column;
forming a metal interconnection structure on the first re-wiring structure, wherein the metal interconnection structure comprises a UBM layer and a passivation layer, the UBM layer is in contact with the first RDL layer, and the passivation layer is provided with a first interconnection hole for exposing the UBM layer;
providing a temporary bonding substrate, and bonding the temporary bonding substrate and the metal interconnection structure;
thinning the substrate, forming a groove exposing the second end of the TSV column in the substrate, and forming an embedded RDL layer in the groove, wherein the embedded RDL layer is in contact with the second end of the TSV column;
forming a second re-wiring structure on the second surface of the substrate, wherein the second re-wiring structure comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the embedded RDL layer, the thickness of the embedded RDL layer is greater than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer;
and removing the temporary bonding substrate to obtain the multilayer wiring adapter plate.
Optionally, the thickness of the embedded RDL layer is 5 μm to 50 μm; the thickness of the second RDL layer is 1-5 μm.
The invention also provides a preparation method of the multilayer wiring adapter plate, which comprises the following steps:
providing a substrate;
forming a first embedded RDL layer and a TSV pillar in the substrate, wherein a first end of the TSV pillar is in contact with the first embedded RDL layer, and the first embedded RDL layer is exposed at a first face of the substrate;
forming a first redistribution structure on the first surface of the substrate, wherein the first redistribution structure comprises a first RDL layer and a first dielectric layer, the first RDL layer is in contact with the first embedded RDL layer, and the thickness of the first embedded RDL layer is greater than that of the first RDL layer;
forming a metal interconnection structure on the first re-wiring structure, wherein the metal interconnection structure comprises a UBM layer and a passivation layer, the UBM layer is in contact with the first RDL layer, and the passivation layer is provided with a first interconnection hole for exposing the UBM layer;
providing a temporary bonding substrate, and bonding the temporary bonding substrate and the metal interconnection structure;
thinning the substrate, forming a groove exposing the second end of the TSV column in the substrate, and forming a second embedded RDL layer in the groove, wherein the second embedded RDL layer is in contact with the second end of the TSV column;
forming a second re-wiring structure on the second surface of the substrate, wherein the second re-wiring structure comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the second embedded RDL layer, the thickness of the second embedded RDL layer is greater than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer;
and removing the temporary bonding substrate to obtain the multilayer wiring adapter plate.
Optionally, the step of forming the first embedded RDL layer and TSV pillars in the substrate includes:
forming a groove in the substrate, and forming a TSV communicated with the groove at the bottom of the groove;
forming a metal layer for filling the TSV hole and the groove by adopting an electroplating method;
and carrying out planarization treatment to obtain the first embedded RDL layer and the TSV column which are positioned in the substrate.
Optionally, the thickness of the formed first embedded RDL layer is 5 μm to 50 μm, and the thickness of the formed first RDL layer is 1 μm to 5 μm; the thickness of the formed second embedded RDL layer is 5-50 μm, and the thickness of the formed second RDL layer is 1-5 μm.
As described above, according to the multilayer wiring adapter plate and the preparation method thereof, the embedded RDL layer with a large thickness contacting with the TSV pillar is prepared in the substrate, so that a large current can pass through the embedded RDL layer, the defect that thick metal cannot be prepared in a previous process can be overcome, and the embedded RDL layer embedded in the substrate can greatly reduce stress caused by the RDL layer, so that the problems of preparation and stress of the adapter plate can be solved; the first rewiring structure with multilayer wiring on the front surface of the substrate provides a signal integration effect for the chip again through the metal interconnection structure, so that the number of pins of the chip is greatly reduced; the second rewiring structure on the back side of the substrate provides package level interconnection and terminal drop out functionality for the dropped signals.
Drawings
Fig. 1 is a schematic process flow diagram of a process for manufacturing a multilayer wiring interposer according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a substrate according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram illustrating a TSV hole formed in a substrate according to a first embodiment of the invention.
Fig. 4 is a schematic structural diagram illustrating a structure after filling the TSV hole in the embodiment of the invention.
Fig. 5 is a schematic structural diagram illustrating a TSV pillar formed in accordance with an embodiment of the present invention.
Fig. 6 is a schematic structural diagram illustrating a first redistribution structure according to a first embodiment of the invention.
Fig. 7 is a schematic structural diagram illustrating a metal interconnection structure formed in accordance with a first embodiment of the present invention.
Fig. 8 is a schematic structural diagram illustrating a structure after forming a groove exposing a TSV pillar in a substrate according to a first embodiment of the invention.
Fig. 9 is a schematic structural diagram illustrating an embedded RDL layer formed in a groove according to a first embodiment of the present invention.
Fig. 10 is a schematic structural diagram illustrating a second dielectric layer formed according to a first embodiment of the invention.
Fig. 11 is a schematic structural diagram illustrating a second RDL layer formed according to a first embodiment of the present invention.
Fig. 12 is a schematic structural diagram illustrating a second interconnection hole formed in the first embodiment of the invention.
Fig. 13 is a schematic process flow diagram illustrating a process for manufacturing a multilayer wiring interposer according to a second embodiment of the present invention.
Fig. 14 is a schematic structural diagram illustrating a substrate with a trench formed therein according to a second embodiment of the invention.
Fig. 15 is a schematic structural diagram illustrating a TSV hole formed in the bottom of the trench according to a second embodiment of the present invention.
Fig. 16 is a schematic structural diagram illustrating the structure after the trenches and the TSV holes are filled in the second embodiment of the invention.
Fig. 17 is a schematic structural diagram illustrating the first embedded RDL layer and the TSV pillar after being formed according to the second embodiment of the invention.
Fig. 18 is a schematic structural diagram illustrating a first redistribution structure according to a second embodiment of the present invention.
Fig. 19 is a schematic structural diagram illustrating a metal interconnection structure formed in the second embodiment of the present invention.
Fig. 20 is a schematic structural diagram illustrating a structure after forming a groove exposing a TSV pillar in a substrate according to a second embodiment of the invention.
Fig. 21 is a schematic structural diagram illustrating a second embedded RDL layer formed in the recess according to a second embodiment of the present invention.
Fig. 22 is a schematic structural diagram illustrating a second dielectric layer formed in accordance with a second embodiment of the present invention.
Fig. 23 is a schematic structural diagram illustrating a second RDL layer formed according to a second embodiment of the present invention.
Fig. 24 is a schematic structural view illustrating a second interconnection hole formed in the second embodiment of the present invention.
Description of the element reference numerals
111. 121-a substrate; 112. 123-TSV holes; 122-a trench; 113. 125-TSV posts; 124-a first embedded RDL layer; 210. 220-first re-routing structure; 211. 221-a first RDL layer; 212. 222-a first dielectric layer; 310. 320-metal interconnect structure; 311. 321-UBM layer; 312. 322-a passivation layer; 313. 323-first interconnecting holes; 114. 126-a groove; 115-embedded RDL layer; 127-second embedded RDL layer; 410. 420-a second rewiring structure; 411. 421-a second RDL layer; 412. 422-a second dielectric layer; 413. 423-second interconnecting holes.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
Referring to fig. 12, the present embodiment provides a multilayer wiring interposer, including:
a substrate 111, and a TSV pillar 113 and an embedded RDL layer 115 in the substrate 111, wherein a first end of the TSV pillar 113 is exposed at a first side of the substrate 111, the embedded RDL layer 115 is in contact with a second end of the TSV pillar 113, and the embedded RDL layer 115 is exposed at a second side of the substrate 111;
a first re-wiring structure 210, the first re-wiring structure 210 being located on a first side of the substrate 111, the first re-wiring structure 210 including a first RDL layer 211 and a first dielectric layer 212, and the first RDL layer 211 being in contact with a first end of the TSV pillar 113;
a metal interconnection structure 310, wherein the metal interconnection structure 310 is located on the first re-routing structure 210, the metal interconnection structure 310 includes a UBM layer 311 and a passivation layer 312, the UBM layer 311 is in contact with the first RDL layer 211, and the passivation layer 312 has a first interconnection hole 313 therein, which exposes the UBM layer 311;
a second redistribution structure 410, wherein the second redistribution structure 410 is located on the second side of the substrate 111, the second redistribution structure 410 includes a second RDL layer 411 and a second dielectric layer 412, the second RDL layer 411 is in contact with the embedded RDL layer 115, the thickness of the embedded RDL layer 115 is greater than that of the second RDL layer 411, and a second interconnection hole 413 exposing the second RDL layer 411 is formed in the second dielectric layer 412.
By way of example, the thickness of the embedded RDL layer 115 is 5 μm to 50 μm; the thickness of the second RDL layer 411 is 1-5 μm.
In the multilayer wiring adapter plate of the embodiment, the embedded RDL layer 115 with a larger thickness in the substrate 111 can allow a large current to pass through, so that the defect that thick metal cannot be prepared in a previous process can be overcome, and meanwhile, the embedded RDL layer 115 embedded in the substrate 111 can greatly reduce stress caused by the RDL layer, so that the problems of preparation and stress of the adapter plate can be solved; the first rewiring structure 210 with multilayer wiring on the front surface of the substrate 111 provides a function of signal integration again for the chip through the metal interconnection structure 310, so that the number of chip pins is greatly reduced; the second redistribution structure 410 on the back side of the substrate 111 provides package-level interconnection and terminal extraction functions for the extracted signals.
Referring to fig. 1 to 12, the present embodiment further provides a method for manufacturing a multilayer wiring interposer, and the following describes a specific structure and a manufacturing method of the multilayer wiring interposer in the present application with reference to the drawings.
First, referring to fig. 1, step S1 is performed: a substrate 111 is provided.
Specifically, the substrate 111 may include a silicon substrate, and the substrate 111 may be a wafer-level substrate, that is, the size of the wafer-level substrate may include 4 inches to 12 inches, such as 4 inches, 6 inches, 8 inches, and 12 inches, and the thickness of the wafer-level substrate may be 200 μm to 2000 μm, such as 200 μm, 500 μm, 1000 μm, and 2000 μm, and the wafer-level substrate may also be made of other materials, such as inorganic materials, such as glass, quartz, silicon carbide, and aluminum oxide, and may also be made of organic materials, such as epoxy resin and polyurethane, and the main function of the wafer-level substrate is to provide a supporting function. The material, thickness and size of the substrate 111 are not limited thereto, and are not limited herein.
Next, referring to fig. 2 to 5, step S2 is performed: a TSV pillar 113 is formed in the substrate 111, and a first end of the TSV pillar 113 is exposed at a first surface of the substrate 111.
Specifically, the step of forming the TSV pillar 113 in the substrate 111 may include:
as shown in fig. 3, a TSV hole 112 is first fabricated in the substrate 111 through photolithography and etching processes, and the diameter of the TSV hole 112 may be 1 μm to 1000 μm, such as 1 μm, 10 μm, 100 μm, 500 μm, 1000 μm, and the like; the depth may be 10 μm to 1000 μm, such as 10 μm, 100 μm, 500 μm, 1000 μm, etc.
Next, depositing an insulating layer (not shown) such as silicon oxide or silicon nitride on the first surface of the substrate 111, or directly performing thermal oxidation to form an insulating layer of silicon oxide, wherein the thickness of the insulating layer may be in a range of 10nm to 100 μm, such as 10nm, 1 μm, 10 μm, 50 μm, 100 μm, etc.; the method, material and thickness of the insulating layer are not limited herein.
Then, a seed layer (not shown) is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer can be 1 nm-100 μm, such as 1nm, 1 μm, 10 μm, 50 μm, 100 μm, and the like, the seed layer can be one layer or a multilayer stack, and the material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, and the like; the method, material and thickness of the seed layer are not limited herein.
Next, as shown in fig. 4, a metal is deposited, which may be, but not limited to, copper, in this embodiment, the TSV hole 112 is filled with copper metal, and the copper is densified at a temperature of 200 to 500 degrees, so as to form a TSV pillar 113 made of copper.
Next, as shown in fig. 5, a CMP process may be used to remove the excess metal material on the first surface of the substrate 111 to expose the first end of the TSV pillar 113, wherein the insulating layer on the first surface of the substrate 111 may be removed by a dry etching process or a wet etching process, but may also remain, so as to complete the preparation of the TSV pillar 113.
Next, referring to fig. 6, step S3 is performed: a first redistribution structure 210 is formed on the first surface of the substrate 111, the first redistribution structure 210 includes a first RDL layer 211 and a first dielectric layer 212, and the first RDL layer 211 is in contact with the first end of the TSV pillar 113.
Specifically, the step of forming the first re-wiring structure 210 may include: forming a seed layer (not shown) on the first surface of the substrate 111, coating a photoresist (not shown), exposing and developing to obtain a patterned photoresist layer, forming the first RDL layer 211 by using an electroplating method, and removing the photoresist layer and the seed layer; the first dielectric layer 212 is then formed with interconnect holes over the first dielectric layer 212 to form connections between the multiple RDL layers. The first redistribution structure 210 may include M layers of the first RDL layer 211, where M ≧ 2. The first dielectric layer 212 may be a silicon oxide material, or PI glue, and the first RDL layer 211 may be a copper metal wiring, or other metal wiring, and the preparation method, material and structure of the first redistribution layer 210 are not limited herein, and may be selected according to the requirement
Next, referring to fig. 7, step S4 is performed: a metal interconnection structure 310 is formed on the first re-routing structure 210, the metal interconnection structure 310 includes a UBM layer 311 and a passivation layer 312, the UBM layer 311 is in contact with the first RDL layer 211, and the passivation layer 312 has a first interconnection hole 313 therein exposing the UBM layer 311.
The connection between a subsequent device and the UBM layer 311 is facilitated through the first interconnection hole 313, the UBM layer 311 is applied as an interconnection pad, the material of the UBM layer 311 may be, but is not limited to, copper, the material of the passivation layer 312 may be, but is not limited to, PI, and the passivation layer 312 may also be an insulating layer such as silicon oxide, silicon nitride, or the like.
Subsequently, step S5 is performed: a temporary bonding substrate (not shown) is provided and bonded to the metal interconnect structure 310.
Specifically, a temporary bonding carrier (not shown) may be provided, and the carrier and the metal interconnection structure 310 may be bonded together by a temporary bonding process, so as to protect the metal interconnection structure 310 through the carrier, and the carrier may be used as a support to thin the substrate 111. The slide glass can comprise 4-inch, 6-inch, 8-inch and 12-inch silicon wafer slide glasses, the slide glass can also be made of other materials, such as inorganic materials including glass, quartz, silicon carbide, aluminum oxide and the like, organic materials including epoxy resin, polyurethane and the like, and metal materials including titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, the main function of the slide glass is to provide a supporting function, and the specific type, thickness and bonding method of the slide glass are not limited herein.
Next, referring to fig. 8 and 9, step S6 is performed: the substrate 111 is thinned, a groove 114 exposing the second end of the TSV pillar 113 is formed in the substrate 111, an embedded RDL layer 115 is formed in the groove 114, and the embedded RDL layer 115 is in contact with the second end of the TSV pillar 113.
The method for forming the groove 114 may adopt dry etching, and after depositing metal to form the embedded RDL layer 115, a planarization step may be further included to obtain a flat surface.
Next, referring to fig. 10 to 12, step S7 is performed: forming a second redistribution structure 410 on the second surface of the substrate 111, wherein the second redistribution structure 410 comprises a second RDL layer 411 and a second dielectric layer 412, the second RDL layer 411 is in contact with the embedded RDL layer 115, the thickness of the embedded RDL layer 115 is greater than the thickness 411 of the second RDL layer, and a second interconnection hole 413 exposing the second RDL layer 411 is formed in the second dielectric layer 412.
Specifically, the second dielectric layer 412 may be a silicon oxide material, or PI glue, etc., and the second RDL layer 411 may be a copper metal wiring, or other metal wirings, and the preparation method, material and structure of the second redistribution structure 410 are not limited herein, and may be selected according to the needs.
By way of example, the thickness of the embedded RDL layer 115 is 5 μm to 50 μm; the thickness of the second RDL layer 411 is 1-5 μm.
Specifically, the thickness of the embedded RDL layer 115 may be 5 μm, 10 μm, 25 μm, 50 μm, etc., and the thickness of the second RDL layer 411 may be 1 μm, 2 μm, 4 μm, 5 μm, etc. The embedded RDL layer 115 with larger thickness in the substrate 111 can allow large current to pass, can make up the defect that thick metal cannot be prepared in the previous process, and can greatly reduce the stress caused by the RDL layer by the embedded RDL layer 115 in the substrate 111, thereby solving the problems of preparation and stress of the adapter plate; the first rewiring structure 210 with multilayer wiring on the front surface of the substrate 111 provides a function of signal integration again for the chip through the metal interconnection structure 310, so that the number of chip pins is greatly reduced; the second redistribution structure 410 on the back side of the substrate 111 provides package-level interconnection and terminal extraction functions for the extracted signals.
Finally, step S8 is performed: and removing the temporary bonding substrate to obtain the multilayer wiring adapter plate.
Example two
Referring to fig. 24, the present embodiment further provides a multilayer wiring interposer, which is different from the multilayer wiring interposer in the first embodiment mainly in that: in this embodiment there are embedded RDL layers on opposite sides of the substrate.
Specifically, the multilayer wiring patch panel includes:
a substrate 121, and a TSV pillar 125, a first embedded RDL layer 124 and a second embedded RDL layer 127 located in the substrate 121, wherein a first end of the TSV pillar 121 contacts the first embedded RDL layer 124, the first embedded RDL layer 124 is exposed at a first side of the substrate 111, the second embedded RDL layer 127 contacts a second end of the TSV pillar 125, and the second embedded RDL layer 127 is exposed at a second side of the substrate 121;
a first re-wiring structure 220, the first re-wiring structure 220 being located on a first side of the substrate 121, the first re-wiring structure 220 comprising a first RDL layer 221 and a first dielectric layer 222, the first RDL layer 221 being in contact with the first embedded RDL layer 124, and a thickness of the first embedded RDL layer 124 being greater than a thickness of the first RDL layer 221;
a metal interconnection structure 320, wherein the metal interconnection structure 320 includes a UBM layer 321 and a passivation layer 322, the UBM layer 321 is in contact with the first RDL layer 221, and the passivation layer 322 has a first interconnection hole 323 exposing the UBM layer 321 therein;
a second redistribution structure 420, the second redistribution structure 420 being located on the second side of the substrate 121, the second redistribution structure 420 including a second RDL layer 421 and a second dielectric layer 422, the second RDL layer 421 being in contact with the second embedded RDL layer 127, the second embedded RDL layer 127 having a thickness greater than that of the second RDL layer 421, the second dielectric layer 422 having a second interconnection hole 423 therein exposing the second RDL layer 421.
For example, the thickness of the first embedded RDL layer 124 is 5 μm to 50 μm, and the thickness of the first RDL layer 221 is 1 μm to 5 μm; the thickness of the second embedded RDL layer 127 is 5-50 μm, and the thickness of the second RDL layer 421 is 1-5 μm.
By way of example, M layers of the first RDL layer 221 are included, and M ≧ 2; the second RDL layer 421 comprises N layers, and N is more than or equal to 2.
In the multilayer wiring adapter plate of the embodiment, the first embedded RDL layer 124 and the second embedded RDL layer 127 which are located in the substrate 121 and have a larger thickness are used, so that a large current can pass through the multilayer wiring adapter plate, the defect that thick metal cannot be prepared in a previous process can be overcome, and the stress caused by the RDL layer can be greatly reduced by the embedded RDL layer embedded in the substrate 121, so that the problems of preparation and stress of the adapter plate can be solved; the first rewiring structure 220 with multilayer wiring on the front surface of the substrate 121 provides a function of signal integration again for the chip through the metal interconnection structure 320, so that the number of chip pins is greatly reduced; the second redistribution structure 420 on the back side of the substrate 121 provides package-level interconnection and terminal extraction functions for the extracted signals.
Referring to fig. 13 to 24, the present embodiment further provides a method for manufacturing a multilayer wiring interposer, and the following describes a specific structure and a manufacturing method of the multilayer wiring interposer in the present application with reference to the drawings.
First, step S1' is performed: providing the substrate 121, reference may be made to the first embodiment regarding the material, the size, and the like of the substrate 121, which is not described herein again.
Next, referring to fig. 14 to 17, step S2': a first embedded RDL layer 124 and a TSV pillar 125 are formed in the substrate 121, a first end of the TSV pillar 125 is in contact with the first embedded RDL layer 124, and the first embedded RDL layer 124 is exposed on a first side of the substrate 121.
As an example, the step of forming the first embedded RDL layer 124 and TSV pillars 125 in the substrate 121 may include:
forming a trench 122 in the substrate 121, and forming a TSV hole 123 penetrating the trench 122 at the bottom of the trench 122, as shown in fig. 14 and 15;
forming a metal layer filling the TSV holes 123 and the trenches 122 by using an electroplating method, as shown in fig. 16;
a planarization process is performed to obtain the first embedded RDL layer 124 and TSV pillars 125 in the substrate 121, as shown in fig. 17.
The material for forming the first embedded RDL layer 124 and the TSV pillar 125 may include, but is not limited to, copper.
Next, referring to fig. 18, step S3': forming a first re-wiring structure 220 on the first surface of the substrate 121, wherein the first re-wiring structure 220 includes a first RDL layer 221 and a first dielectric layer 222, the first RDL layer 221 is in contact with the first embedded RDL layer 124, and the thickness of the first embedded RDL layer 124 is greater than that of the first RDL layer 221. For the preparation of the first redistribution structure 220, reference may be made to the first embodiment, which is not described herein.
Next, referring to fig. 19, step S4': a metal interconnection structure 320 is formed on the first rewiring junction 220, the metal interconnection structure 320 includes a UBM layer 321 and a passivation layer 322, the UBM layer 321 contacts the first RDL layer 124, and the passivation layer 322 has a first interconnection hole 323 exposing the UBM layer 321 therein. For the preparation of the metal interconnection structure 320, reference may be made to the first embodiment, which is not described herein.
Next, step S5': providing a temporary bonding substrate (not shown), and bonding the temporary bonding substrate and the metal interconnection structure 320, wherein reference may be made to the first embodiment for the kind of the temporary bonding substrate, which is not described herein again.
Next, referring to fig. 20 and 21, step S6': the substrate 121 is thinned, a groove 126 exposing the second end of the TSV pillar 125 is formed in the substrate 121, as shown in fig. 21, a second embedded RDL layer 127 is formed in the groove 126, and the second embedded RDL layer 127 is in contact with the second end of the TSV pillar 125. For the preparation, material and the like of the second embedded RDL layer 127, reference may be made to the first embodiment, which is not described herein again.
Next, referring to fig. 22 to 24, step S7': forming a second redistribution structure 420 on the second surface of the substrate 121, wherein the second redistribution structure 420 comprises a second RDL layer 421 and a second dielectric layer 422, the second RDL layer 421 contacts with the second embedded RDL layer 127, the thickness of the second embedded RDL layer 127 is greater than that of the second RDL layer 421, and a second interconnection hole 423 exposing the second RDL layer 421 is formed in the second dielectric layer 422. For the material and the manufacturing method of the second redistribution structure 420, reference may be made to the first embodiment, which is not described herein.
Finally, step S8' is performed: and removing the temporary bonding substrate to obtain the multilayer wiring adapter plate.
As an example, the first embedded RDL layer 124 is formed to have a thickness of 5 μm to 50 μm, such as 5 μm, 10 μm, 25 μm, 50 μm, etc., and the first RDL layer 221 is formed to have a thickness of 1 μm to 5 μm, such as 1 μm, 2 μm, 4 μm, 5 μm, etc.; the thickness of the second embedded RDL layer 127 is 5 μm to 50 μm, such as 5 μm, 10 μm, 25 μm, 50 μm, etc., and the thickness of the second RDL layer 421 is 1 μm to 5 μm, such as 1 μm, 2 μm, 4 μm, 5 μm, etc.
By way of example, M layers of the first RDL layer 221 are included, and M ≧ 2; the second RDL layer 421 comprises N layers, and N is more than or equal to 2.
In summary, according to the multilayer wiring adapter plate and the preparation method thereof, the embedded RDL layer with a larger thickness, which is in contact with the TSV pillar, is prepared in the substrate, so that a large current can pass through the embedded RDL layer, the defect that thick metal cannot be prepared in a previous process can be overcome, and the stress caused by the RDL layer can be greatly reduced by the embedded RDL layer in the substrate, so that the preparation and stress problems of the adapter plate can be solved; the first rewiring structure with multilayer wiring on the front surface of the substrate provides a signal integration effect for the chip again through the metal interconnection structure, so that the number of pins of the chip is greatly reduced; the second rewiring structure on the back side of the substrate provides package level interconnection and terminal drop out functionality for the dropped signals.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A multilayer wiring patch panel, comprising:
the TSV column and the embedded RDL layer are positioned in the substrate, wherein a first end of the TSV column is exposed at a first face of the substrate, the embedded RDL layer is in contact with a second end of the TSV column, and the embedded RDL layer is exposed at a second face of the substrate;
a first redistribution structure on the first side of the substrate, the first redistribution structure comprising a first RDL layer and a first dielectric layer, and the first RDL layer being in contact with the first end of the TSV pillar;
a metal interconnection structure on the first redistribution structure, the metal interconnection structure including a UBM layer and a passivation layer, the UBM layer being in contact with the first RDL layer, and the passivation layer having a first interconnection hole therein exposing the UBM layer;
the second rewiring structure is located on the second face of the substrate and comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the embedded RDL layer, the thickness of the embedded RDL layer is larger than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer.
2. The multilayer wiring patch panel of claim 1 wherein: the thickness of the embedded RDL layer is 5-50 μm; the thickness of the second RDL layer is 1-5 mu m.
3. A multilayer wiring patch panel, comprising:
the TSV column, the first embedded RDL layer and the second embedded RDL layer are positioned in the substrate, wherein the first end of the TSV column is in contact with the first embedded RDL layer, the first embedded RDL layer is exposed out of the first face of the substrate, the second embedded RDL layer is in contact with the second end of the TSV column, and the second embedded RDL layer is exposed out of the second face of the substrate;
a first redistribution structure on the first side of the substrate, the first redistribution structure comprising a first RDL layer and a first dielectric layer, the first RDL layer in contact with the first embedded RDL layer, and the first embedded RDL layer having a thickness greater than a thickness of the first RDL layer;
the metal interconnection structure comprises a UBM layer and a passivation layer, the UBM layer is in contact with the first RDL layer, and a first interconnection hole exposing the UBM layer is formed in the passivation layer;
the second rewiring structure is located on the second face of the substrate and comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the second embedded RDL layer, the thickness of the second embedded RDL layer is larger than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer.
4. The multilayer wiring patch panel of claim 3 wherein: the thickness of the first embedded RDL layer is 5-50 μm, and the thickness of the first RDL layer is 1-5 μm; the thickness of the second embedded RDL layer is 5-50 μm, and the thickness of the second RDL layer is 1-5 μm.
5. The multilayer wiring patch panel of claim 3 wherein: the RDL layer comprises M layers and M is more than or equal to 2; the second RDL layer comprises N layers, and N is more than or equal to 2.
6. A preparation method of a multilayer wiring adapter plate is characterized by comprising the following steps:
providing a substrate;
forming a TSV pillar in the substrate, wherein a first end of the TSV pillar is exposed at a first face of the substrate;
forming a first redistribution structure on the first side of the substrate, wherein the first redistribution structure comprises a first RDL layer and a first dielectric layer, and the first RDL layer is in contact with the first end of the TSV column;
forming a metal interconnection structure on the first re-wiring structure, wherein the metal interconnection structure comprises a UBM layer and a passivation layer, the UBM layer is in contact with the first RDL layer, and the passivation layer is provided with a first interconnection hole for exposing the UBM layer;
providing a temporary bonding substrate, and bonding the temporary bonding substrate and the metal interconnection structure;
thinning the substrate, forming a groove exposing the second end of the TSV column in the substrate, and forming an embedded RDL layer in the groove, wherein the embedded RDL layer is in contact with the second end of the TSV column;
forming a second re-wiring structure on the second surface of the substrate, wherein the second re-wiring structure comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the embedded RDL layer, the thickness of the embedded RDL layer is greater than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer;
and removing the temporary bonding substrate to obtain the multilayer wiring adapter plate.
7. The method of making a multilayer wiring interposer as recited in claim 6, wherein: the thickness of the embedded RDL layer is 5-50 μm; the thickness of the second RDL layer is 1-5 μm.
8. A preparation method of a multilayer wiring adapter plate is characterized by comprising the following steps:
providing a substrate;
forming a first embedded RDL layer and a TSV pillar in the substrate, wherein a first end of the TSV pillar is in contact with the first embedded RDL layer, and the first embedded RDL layer is exposed at a first face of the substrate;
forming a first redistribution structure on the first surface of the substrate, wherein the first redistribution structure comprises a first RDL layer and a first dielectric layer, the first RDL layer is in contact with the first embedded RDL layer, and the thickness of the first embedded RDL layer is greater than that of the first RDL layer;
forming a metal interconnection structure on the first re-wiring structure, wherein the metal interconnection structure comprises a UBM layer and a passivation layer, the UBM layer is in contact with the first RDL layer, and the passivation layer is provided with a first interconnection hole for exposing the UBM layer;
providing a temporary bonding substrate, and bonding the temporary bonding substrate and the metal interconnection structure;
thinning the substrate, forming a groove exposing the second end of the TSV column in the substrate, and forming a second embedded RDL layer in the groove, wherein the second embedded RDL layer is in contact with the second end of the TSV column;
forming a second re-wiring structure on the second surface of the substrate, wherein the second re-wiring structure comprises a second RDL layer and a second dielectric layer, the second RDL layer is in contact with the second embedded RDL layer, the thickness of the second embedded RDL layer is greater than that of the second RDL layer, and a second interconnection hole exposing the second RDL layer is formed in the second dielectric layer;
and removing the temporary bonding substrate to obtain the multilayer wiring adapter plate.
9. The method of claim 8, wherein the step of forming the first embedded RDL layer and TSV pillars in the substrate comprises:
forming a groove in the substrate, and forming a TSV communicated with the groove at the bottom of the groove;
forming a metal layer for filling the TSV hole and the groove by adopting an electroplating method;
and carrying out planarization treatment to obtain the first embedded RDL layer and the TSV column which are positioned in the substrate.
10. The method of making a multilayer wiring interposer as recited in claim 8, wherein: the thickness of the formed first embedded RDL layer is 5-50 μm, and the thickness of the formed first RDL layer is 1-5 μm; the thickness of the formed second embedded RDL layer is 5-50 μm, and the thickness of the formed second RDL layer is 1-5 μm.
CN202110616822.2A 2021-06-03 2021-06-03 Multilayer wiring adapter plate and preparation method thereof Pending CN113078133A (en)

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CN117393523A (en) * 2023-12-07 2024-01-12 浙江集迈科微电子有限公司 Multilayer wiring adapter plate for mounting and preparation method thereof

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JP2004158537A (en) * 2002-11-05 2004-06-03 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
KR20120058114A (en) * 2010-11-29 2012-06-07 삼성전자주식회사 Semiconductor device, fabricating method thereof, and semiconductor package comprising the semiconductor device
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Application publication date: 20210706