CN113078064A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
CN113078064A
CN113078064A CN202010010414.8A CN202010010414A CN113078064A CN 113078064 A CN113078064 A CN 113078064A CN 202010010414 A CN202010010414 A CN 202010010414A CN 113078064 A CN113078064 A CN 113078064A
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Prior art keywords
forming
amorphous silicon
semiconductor device
layer
silicon layer
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Inventor
唐睿智
李波
刘琳
黄豪俊
刘佳磊
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010010414.8A priority Critical patent/CN113078064A/en
Publication of CN113078064A publication Critical patent/CN113078064A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate, wherein a fin part is formed on the substrate and comprises a dense area and a sparse area; forming spacers between adjacent fins of the sparse region; forming a dielectric layer on the substrate and on the side wall and the top of the fin part; forming amorphous silicon layers on the dielectric layer and the side wall of the isolating piece; and removing the amorphous silicon layer by adopting a wet etching process, wherein etching liquid of the wet etching process contains alcohol. When the wet etching process is adopted to remove the amorphous silicon layer, the etching liquid of the wet etching contains alcohol, so that the amorphous silicon layer between the isolating piece and the fin part can be completely or basically eliminated when the amorphous silicon layer is removed, and no residual amorphous silicon layer exists between the fin part and the isolating piece, thereby improving the performance and the quality of the semiconductor device.

Description

Method for forming semiconductor device
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor device.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation structure, wherein the fin part and the isolation structure are positioned on the surface of a semiconductor substrate, the isolation structure covers part of the side wall of the fin part, and the isolation structure is positioned on the substrate and crosses a grid structure of the fin part; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as the size of semiconductor devices is reduced and the device density is increased, the performance of the formed fin field effect transistor is unstable.
Disclosure of Invention
The invention provides a method for forming a semiconductor device, thereby improving the use performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate, wherein a fin part is formed on the substrate and comprises a dense area and a sparse area; forming spacers between adjacent fins of the sparse region; forming a dielectric layer on the substrate and on the side wall and the top of the fin part; forming amorphous silicon layers on the dielectric layer and the side wall of the isolating piece; and removing the amorphous silicon layer by adopting a wet etching process, wherein etching liquid of the wet etching process contains alcohol.
Optionally, the alcohol is isopropanol or ethanol or 1, 6-hexanediol.
Optionally, the etching solution further includes an alkaline aqueous solution.
Optionally, the alkaline aqueous solution is a mixed solution of an alkaline solution and water, and the alkaline solution is NH4OH alkaline solution or TMAH alkaline solution or EDA alkaline solution or KOH alkaline solution.
Optionally, the volume ratio of the alkaline solution to the water is 1: 1-1: 80.
Optionally, the volume ratio of the alkaline solution to the alcohol is 1: 1-1: 5.
Optionally, before removing the amorphous silicon layer, the method further includes: and carrying out heat treatment on the amorphous silicon layer.
Optionally, the heat treatment is a high-temperature annealing treatment.
Optionally, the temperature range adopted by the wet etching process is 25-80 ℃.
Optionally, before forming the spacer, the method further includes: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after the fin part and the spacer are formed on the substrate, a dielectric layer is formed on the substrate and on the side wall and the top of the fin part, and the dielectric layer is used as a grid dielectric layer subsequently; after the dielectric layer is formed, amorphous silicon layers are formed on the dielectric layer and the side walls and the tops of the isolating pieces, and when the amorphous silicon layers are removed by adopting a wet etching process, because the etching liquid of the wet etching process contains alcohol, the amorphous silicon layers between the isolating pieces and the fin parts can be completely removed when the amorphous silicon layers are removed, and no residual amorphous silicon layers exist between the fin parts and the isolating pieces, so that the quality and the performance reliability of the semiconductor device are improved. This is because when the amorphous silicon layer is removed by the wet etching process, a large amount of hydrogen bubbles are generated when the etching solution reacts with the amorphous silicon layer, the hydrogen bubbles are attached to the surface of the amorphous silicon layer to form a pseudo mask, the amorphous silicon layer covered by the pseudo mask is protected, the etching liquid cannot etch the amorphous silicon layer, but because the etching liquid of the wet etching process contains alcohol, the surface tension of the etching liquid is greatly reduced due to the addition of the alcohol, hydrogen bubbles generated on the surface of the amorphous silicon layer during the etching process become fine and can rapidly leave the surface of the amorphous silicon layer, which prevents the hydrogen bubbles from staying and failing to form a dummy mask, therefore, the amorphous silicon layer is etched, the residue of the amorphous silicon layer is eliminated, and the formed semiconductor device has reliable performance and high quality.
Drawings
Fig. 1 to 5 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment;
fig. 6 to 11 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
With the rapid development of semiconductor technology, the size of a semiconductor device is smaller and smaller, and with the increase of the density of the semiconductor device, the performance of the formed semiconductor device is unstable, which limits the use of the semiconductor device, and the specific forming process refers to fig. 1 to 5.
Referring first to fig. 1, a substrate 100 is provided, and a fin 110 is formed on the substrate 100, wherein the fin 110 includes a dense region 111 and a sparse region 112.
Spacers 120 are formed between the fins 110 of the sparse region 112 with reference to figure 2.
Before the spacers 120 are formed, an isolation layer (not shown) is formed on the substrate 100.
Referring to fig. 3, a dielectric layer 130 is formed on the substrate 100, on the sidewalls and on the top of the fin 110.
Referring to fig. 4, an amorphous silicon layer 140 is formed on the dielectric layer 130 and on the sidewalls of the spacers 120.
Referring to fig. 5, the amorphous silicon layer 140 is etched away.
The inventor analyzes and finds that the performance of the semiconductor device formed by the forming method is poor, the use of the semiconductor device is seriously influenced, and from the dotted line of fig. 5, it can be seen that the amorphous silicon layer between the fin and the spacer cannot be removed, so that the amorphous silicon layer is remained, and the performance of the semiconductor device is influenced. The reason why the amorphous silicon layer at the dotted line is not removed is that: on one hand, when the spacer is formed, the spacer can be ideally formed at the position in the middle of the adjacent fin parts, but as the semiconductor size is reduced, the spacer cannot be accurately formed at the position in the middle, so that one side of the spacer is far away from the near point of the fin part, and the other side of the spacer is far away from the far point of the fin part, and the smaller the distance is, the more the amorphous silicon layer is easy to remove; in another aspect: when the amorphous silicon layer is etched, etching liquid reacts with the amorphous silicon layer to generate a large amount of hydrogen bubbles, the hydrogen bubbles are unevenly attached to the surface of the amorphous silicon layer to serve as a pseudo mask to prevent etching, but the generated hydrogen bubbles are less prone to escaping out of the etching liquid due to the fact that the distance between the bottom of the fin portion and the bottom of the isolating piece is small, when the number of the gathered hydrogen bubbles is larger, the blocking effect on etching is stronger, the amorphous silicon layer at the dotted line cannot be etched and removed due to the two aspects, and therefore the amorphous silicon layer is left, and the performance of a formed semiconductor device is affected.
The inventor researches and discovers that alcohol is added into the etching liquid for removing the amorphous silicon layer by etching, and the alcohol is used for reducing the surface tension of the etching liquid, so that hydrogen bubbles generated by reaction in the etching process can quickly run out of the etching liquid, and can not be accumulated on the surface of the amorphous silicon layer, the hydrogen bubbles are prevented from being resident and cannot form a pseudo mask, the amorphous silicon layer is favorably removed by etching, the residue of the amorphous silicon layer is reduced, and the performance of the formed semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 11 are schematic structural views illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring first to fig. 6, a substrate 200 is provided.
In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like.
Referring to fig. 7, a fin 300 is formed on the substrate 200, the fin 300 including a dense region 310 and a sparse region 320.
In this embodiment, the process steps for forming the fin portion 300 include: forming a patterning layer (not shown in the figure) on the substrate 200, wherein the patterning layer corresponds to the position of the fin portion 300 to be formed, etching the substrate 200 with a part of the thickness by using the patterning layer as a mask, forming a plurality of fin portions 300 which are distributed separately on the substrate 200, and removing the patterning layer.
In other embodiments, the process step of forming the fin portion 300 may be further depositing a material layer of the fin portion 300 on the substrate 200, forming a patterned layer on the material layer of the fin portion 300, etching the material layer of the fin portion 300 until the material layer of the fin portion 300 is exposed out of the surface of the substrate 200 by using the patterned layer as a mask, forming a plurality of fin portions 300 distributed separately on the substrate 200, and removing the patterned layer.
In this embodiment, the fin 300 includes the sparse region 320 and the dense region 310. The distance between the adjacent fins 300 of the sparse region 320 is greater than the distance between the adjacent fins 300 of the dense region 310. This is set according to the actual circuit design requirements.
In this embodiment, an isolation layer 210 is formed on the substrate 200, and the isolation layer 210 covers a portion of the sidewall of the fin 300.
In this embodiment, the isolation layer 210 is made of silicon oxide; in other embodiments, the material of the isolation layer 210 is silicon nitride, silicon oxynitride, or the like.
In other embodiments, the isolation layer 210 is not formed on the substrate 200.
In this embodiment, the purpose of forming the isolation layer 210 on the substrate 200 is to ensure that the surface of the substrate 200 is not damaged in the following; on the other hand, the isolation layer 210 isolates the adjacent fin portions, thereby preventing the subsequent phenomena of electric leakage, short circuit and the like.
The method of forming the isolation layer 210 includes: forming an isolation layer film (not shown) on the substrate 200 covering the fin 300; the isolation layer film is etched back to form the isolation layer 210.
The process for forming the barrier film is a deposition process, such as a fluid chemical vapor deposition process. The isolation layer film is formed by adopting a fluid chemical vapor deposition process, so that the filling performance of the isolation layer film is better.
The steps of the fluid chemical vapor deposition process used for forming the barrier film include: forming an isolated fluid layer on the substrate 200; and carrying out water vapor annealing to enable the isolating fluid layer to form an isolating layer film.
The parameters of the water vapor annealing comprise: the adopted gas comprises oxygen, ozone and gaseous water, and the annealing temperature is 350-750 ℃.
Referring to fig. 8, spacers 400 are formed between adjacent ones of the fins of the sparse region 320.
In this embodiment, the spacers 400 formed between adjacent fins 300 in the sparse region 320 are used to distinguish different functional regions.
In this embodiment, the top height of the spacer 400 is higher than the top height of the fin 300.
In this embodiment, the material of the spacer 400 is silicon oxide; in other embodiments, the material of the spacer 400 is silicon nitride, silicon oxynitride, or the like.
In this embodiment, the spacers 400 are formed in a conventional manner and will not be redundantly described here.
Referring to fig. 9, a dielectric layer 500 is formed on the substrate 200, on the sidewalls and on the top of the fin 300.
In this embodiment, since the isolation layer 210 is formed on the substrate 200, the dielectric layer 500 is formed on the isolation layer 210, the sidewalls and the top of the fin 300.
In this embodiment, the dielectric layer 500 is a high-k dielectric layer (dielectric constant greater than 3.9).
In this embodiment, before the dielectric layer 500 is formed, the interface layers 220 are formed on the sidewalls and the top of the fin 300, and the purpose of forming the interface layers 220 is to facilitate the adhesion of the dielectric layer 500 on the top and the sidewalls of the fin 300, so as to form the dielectric layer 500 with good quality and repair the surface of the fin 300.
The material of the interfacial layer 220 includes silicon oxide. The process of forming the interfacial layer 220 includes an oxidation process.
In this embodiment, the interface layer 220 extends onto the substrate 200.
In this embodiment, the dielectric layer 500 is made of hafnium oxide; in other embodiments, the material of the dielectric layer 500 may also be zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
In this embodiment, the dielectric layer 500 is formed by a chemical vapor deposition process; in other embodiments, the dielectric layer 500 may be formed by an atomic layer deposition process or a physical vapor deposition process.
Referring to fig. 10, an amorphous silicon layer 600 is formed on the dielectric layer 500 and on the sidewalls of the spacers 400.
In this embodiment, before forming the amorphous silicon layer 600, the method further includes: a TiN layer 510 is formed on the substrate 200, on the sidewalls and top of the fin 300.
In this embodiment, the TiN layer 510 is formed to: the TiN layer 510 is used as a barrier layer to function as a barrier.
In this embodiment, since the dielectric layer 500 is made of a high-k dielectric layer and the dielectric layer 500 has a lot of vacancy oxygen, the vacancy oxygen needs to be removed, so that the amorphous silicon layer 600 needs to be formed on the sidewalls of the dielectric layer 500 and the spacers 400.
Referring to fig. 11, the amorphous silicon layer 600 is removed by a wet etching process, and an etching solution of the wet etching process contains alcohol.
In this embodiment, the alcohol is isopropyl alcohol; in other embodiments, the alcohol may also be ethanol or 1, 6-hexanediol.
In this embodiment, when the amorphous silicon layer 600 is removed by wet etching, the etching solution of the wet etching contains alcohol, so that the formed amorphous silicon layer 600 can be completely removed, thereby eliminating the residue of the amorphous silicon layer 600 and improving the quality of the formed semiconductor device. The reason is that alcohol is added into the etching solution, the alcohol can reduce the liquid surface tension of the etching solution, and the reduction of the liquid surface tension of the etching solution means that bubbles can quickly escape from the etching solution when the bubbles are generated in the etching solution, so that when the etching solution and the amorphous silicon layer 600 perform a chemical reaction to generate hydrogen bubbles, the hydrogen bubbles can quickly escape from the etching solution and cannot stay on the surface of the amorphous silicon layer 600 to serve as a pseudo mask, the etching reaction process cannot be prevented, the amorphous silicon layer 600 can be well removed, and the method has good compatibility with the CMOS process, is low in cost and improves the performance and reliability of a semiconductor device.
In this embodiment, the etching solution further includes an alkaline aqueous solution, and the alkaline aqueous solution reacts with the amorphous silicon layer 600 to remove a main reaction substance of the amorphous silicon layer 600.
In this embodiment, the alkaline aqueous solution is a mixed solution of an alkaline solution and water.
In this embodiment, the alkaline solution is NH4OH solution; in other embodiments, the alkaline solution may also be a TMAH alkaline solution or an EDA alkaline solution or a KOH alkaline solution.
In this embodiment, the alkaline aqueous solution is NH4A mixed solution of an OH solution and water, and a reaction mechanism of the alkaline aqueous solution and the amorphous silicon layer 600 is Si + NH4OH+H2O→Si(OH)6 2-+H2From the reactorThe silicon etching process shows that a large amount of hydrogen is generated in the amorphous silicon layer 600 in the etching process, the hydrogen is insoluble in water, so that a large amount of hydrogen bubbles are generated in the etching solution, if the surface tension of the etching solution is large, the hydrogen bubbles are not easy to escape from the etching solution, and then an aggregation phenomenon is generated, so that the hydrogen bubbles can play a role of a pseudo mask on the surface of the amorphous silicon layer 600, the etching is prevented from continuing, and the amorphous silicon layer 600 is not easy to remove; however, if the surface tension of the etching solution is reduced, the formed hydrogen bubbles easily escape from the etching solution, and thus the etching process is not prevented, thereby facilitating the etching removal of the amorphous silicon layer 600.
In this embodiment, the reason why the surface tension of the etching solution can be reduced by adding isopropyl alcohol to the etching solution is as follows: isopropyl alcohol also has the effect of significantly reducing the surface tension of the etching solution. In an aqueous solution, hydroxyl groups in isopropanol are tightly bonded with water molecules through hydrogen bonds, and alkyl groups on both sides of the isopropanol are weaker in bonding force with the water molecules. Thus, the interaction force between the water molecules is greatly reduced compared to the water molecules bonded by hydrogen bonds, which causes the surface tension of the etching solution to be lowered.
In this embodiment, the volume ratio of the alkaline solution to the water is in a range of 1:1 to 1:80, that is, the NH4The volume ratio of the OH alkaline solution to the water is 1: 1-1: 80. When said NH is present4When the volume ratio of the OH alkaline solution to the water is more than 1:1, the ratio is NH4The volume of the OH alkaline solution is large, and the concentration of the formed alkaline aqueous solution is too high, so that the TiN layer 510 is damaged when the amorphous silicon layer 600 is etched and removed, the TiN layer 510 cannot be etched in the formation process of the semiconductor device, or the diffused ions can cause damage to the formed fin portion 300; when said NH is present4When the volume ratio of the OH alkaline solution to the water is less than 1:80, the water has a large mass, the concentration of the formed alkaline aqueous solution is too low, and when the amorphous silicon layer 600 is removed by etching, the formed alkaline aqueous solution has too low concentration and cannot be mixed with the amorphous silicon layer600, so that the formed amorphous silicon layer 600 cannot be removed by etching and cannot meet the actual process requirements.
In this example, the NH was used4The ratio of the volume of the OH alkaline solution to the volume of the water is 1:5 to form an alkaline aqueous solution, because this ratio ensures that the TiN layer 510 at the bottom of the amorphous silicon layer 600 is not damaged while ensuring the speed of removing the amorphous silicon layer 600 by etching.
In this embodiment, the volume ratio of the alkaline solution to the alcohol is in a range of 1:1 to 1:5, i.e., the NH4The volume ratio of the OH alkaline solution to the alcohol is 1: 1-1: 5. When said NH is present4When the ratio of the volume of the OH alkaline solution to the volume of the alcohol is more than 1:1, the volume of the alcohol added is small and the NH is4The volume of the OH alkaline solution is large, the reaction is violent at this time, a large amount of hydrogen is generated, but the volume of the added alcohol is small, and the surface tension of the liquid is not sufficiently reduced, so that the generated hydrogen cannot timely escape from the etching liquid, the hydrogen is gathered, a pseudo mask is formed, the etching effect of the amorphous silicon layer 600 is influenced, and the amorphous silicon layer 600 is easily left; when said NH is present4When the ratio of the volume of the OH alkaline solution to the volume of the alcohol is less than 1:5, the amount of the alcohol added is too large and the NH is4The volume of the OH alkaline solution is relatively small, so that there is not enough alkaline substance to react with the amorphous silicon layer 600, thereby slowing down the speed of removing the amorphous silicon layer 600 by etching, which affects the production efficiency.
In this example, the NH was used4The ratio of the volume of the alkaline solution of OH to the volume of the alcohol is 1:1, because this ratio not only ensures the rate of removing the amorphous silicon layer 600, but also allows the surface tension of the etched liquid to be well reduced, allowing the rate of hydrogen formation and the rate of hydrogen escape from the liquid to be balanced.
In this embodiment, the process temperature range of the wet etching process is 25 ℃ to 80 ℃.
In this embodiment, compared with the dry etching, the advantage of performing the wet etching by using the wet etching process parameters is that the interface layer 220 and the fin portion 300 are not damaged by the plasma, so that the formation quality of the interface layer 220 and the fin portion 300 is ensured, and the quality of the formed semiconductor device is improved.
In this embodiment, before removing the amorphous silicon layer 600, the method further includes: the amorphous silicon layer 600 is heat-treated.
In this embodiment, the heat treatment is performed to remove oxygen vacancies in the high-k dielectric layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A method of forming a semiconductor device, comprising the steps of:
providing a substrate, wherein a fin part is formed on the substrate and comprises a dense area and a sparse area;
forming spacers between adjacent fins of the sparse region;
forming a dielectric layer on the substrate and on the side wall and the top of the fin part;
forming amorphous silicon layers on the dielectric layer and the side wall of the isolating piece;
and removing the amorphous silicon layer by adopting a wet etching process, wherein etching liquid of the wet etching process contains alcohol.
2. The method for forming a semiconductor device according to claim 1, wherein the alcohol is isopropyl alcohol or ethyl alcohol or 1, 6-hexanediol.
3. The method for forming a semiconductor device according to claim 1, wherein the etching solution further comprises an alkaline aqueous solution.
4. The method according to claim 3, wherein the aqueous alkaline solution is a mixture of an alkaline solution and water, and wherein the alkaline solution is NH4OH alkaline solution or TMAH alkaline solution or EDA alkaline solution or KOH alkaline solution.
5. The method for forming a semiconductor device according to claim 4, wherein a ratio of a volume of the alkali solution to a volume of the water is in a range of 1:1 to 1: 80.
6. The method for forming a semiconductor device according to claim 4, wherein a ratio of a volume of the alkali solution to a volume of the alcohol is in a range of 1:1 to 1: 5.
7. The method of forming a semiconductor device of claim 1, wherein removing the amorphous silicon layer further comprises: and carrying out heat treatment on the amorphous silicon layer.
8. The method for forming a semiconductor device according to claim 7, wherein the heat treatment is a high-temperature annealing treatment.
9. The method for forming a semiconductor device according to claim 1, wherein the wet etching process uses a temperature in a range of 25 ℃ to 80 ℃.
10. The method of forming a semiconductor device according to claim 1, further comprising, before forming the spacer: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the fin part.
CN202010010414.8A 2020-01-06 2020-01-06 Method for forming semiconductor device Pending CN113078064A (en)

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