CN113076061A - Single RAM multi-module data caching method - Google Patents

Single RAM multi-module data caching method Download PDF

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CN113076061A
CN113076061A CN202110288714.7A CN202110288714A CN113076061A CN 113076061 A CN113076061 A CN 113076061A CN 202110288714 A CN202110288714 A CN 202110288714A CN 113076061 A CN113076061 A CN 113076061A
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ram
data
module data
module
caching
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何磊
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IPGoal Microelectronics Sichuan Co Ltd
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IPGoal Microelectronics Sichuan Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0626—Reducing size or complexity of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
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Abstract

The invention discloses a single RAM multi-module data caching method, which comprises the following steps: a. determining the number N of module data buffered in the RAM, and determining the bit width A required by data transmission in the RAM according to the data transmission speed M in the USB and the actual system clock L; b. adding ACK feedback identifications to N module data according to priority levels, wherein each ACK feedback identification comprises priority level information; c. respectively caching the N module data added with the ACK feedback identification into an RAM; d. and sequentially reading/writing the data of the N modules in the RAM according to the priority level. The single RAM multi-module data caching method realizes caching of multi-module data by the single RAM, reduces the chip area occupied by the RAM, correspondingly reduces the power consumption of the chip and prolongs the service life of the chip.

Description

Single RAM multi-module data caching method
Technical Field
The invention relates to the field of digital IC design, in particular to a single-RAM multi-module data caching method.
Background
Common USB internal cache data is usually stored by using a RAM; however, since a plurality of modules stored inside the USB need to cache data, a common method is to cache one data module on one RAM, so a common method that a plurality of RAMs are used inside the USB to cache multi-module data respectively.
Although the multi-module data can be flexibly managed by using a plurality of RAMs to cache the multi-module data, the form of the plurality of RAMs also occupies more chip area, and is not beneficial to the development of miniaturization and high integration of chips; in addition, the form of a plurality of RAMs can correspondingly increase the power consumption of the chip and influence the service life of the RAMs. For example, in a 130nm technology, the area of a chip can be saved by about 20% by using a larger RAM to cache data of four nodes and four pieces of RAMs to cache data of four nodes in a USB respectively under the same condition, and meanwhile, the power consumption is also greatly reduced. However, the existing single RAM cannot read data of multiple addresses simultaneously, so that the reading efficiency of the data is greatly reduced, and errors are easy to occur in the reading process.
Accordingly, there is a need to overcome the above-mentioned deficiencies by providing an improved single RAM multi-chunk data caching method that can quickly and accurately read/access multi-chunk data within a single RAM.
Disclosure of Invention
The invention aims to provide a single-RAM multi-module data caching method, which realizes the caching of multi-module data by a single RAM, reduces the chip area occupied by the RAM, correspondingly reduces the power consumption of a chip and prolongs the service life of the chip.
In order to achieve the above object, the present invention provides a single RAM multi-module data caching method, which comprises the following steps:
a. determining the number N of module data buffered in the RAM, and determining the bit width A required by data transmission in the RAM according to the data transmission speed M in the USB and the actual system clock L;
b. adding ACK feedback identifications to N module data according to priority levels, wherein each ACK feedback identification comprises priority level information;
c. respectively caching the N module data added with the ACK feedback identification into an RAM;
d. and sequentially reading/writing the data of the N modules in the RAM according to the priority level.
Preferably, the determining the bit width a required for data transmission in the RAM in the step a specifically includes:
Figure BDA0002981522710000021
the data transmission speed M in the USB and the actual system clock L are both constant.
Preferably, in the step b, the priority level on the ACK feedback identifier is respectively from 0 level to N-1 level, and the priority level of 0 level is higher than the priority level of N-1 level.
Preferably, in the step d, when data is read/written, the first clock is input to the module data with the priority of 0, and then the other N-1 hour hands are sequentially input to the other N-1 module data.
Preferably, the value range of N is 1 to 16, and correspondingly, the value range of bit width a is 24-216。
Preferably, the priority level of the module data for which data is continuously read/written is set to the lowest priority.
Compared with the prior art, the single-RAM multi-module data caching method has the advantages that the ACK feedback identifications are added to the N module data according to the priority levels respectively, each ACK feedback identification comprises priority level information, and the N module data are read/written in sequence according to the priority levels, so that after the plurality of module data are stored in the large RAM, the plurality of module data in the RAM can be read/written respectively according to the priority levels, and the reading/writing is carried out according to the priority levels and the clock sequence, the reading/writing accuracy is guaranteed, meanwhile, the caching of the single RAM on the multi-module data is realized, the chip area occupied by the RAM is reduced, the power consumption of a chip is correspondingly reduced, and the service life of the chip is prolonged.
The invention will become more apparent from the following description when taken in conjunction with the accompanying drawings, which illustrate embodiments of the invention.
Drawings
FIG. 1 is a flow chart of a single RAM multi-module data caching method according to the present invention.
Fig. 2 is a timing diagram of 1 module data individually controlling the RAM.
FIG. 3 is a timing diagram of the control of the RAM by the priority level of 2 module data.
Detailed Description
Embodiments of the present invention will now be described with reference to the drawings, wherein like element numerals represent like elements. The single-RAM multi-module data caching method realizes caching of multi-module data by a single RAM, reduces the chip area occupied by the RAM, correspondingly reduces the power consumption of a chip and prolongs the service life of the chip.
Referring to fig. 1, fig. 1 is a flowchart illustrating a single-RAM multi-module data caching method according to the present invention, wherein the single-RAM multi-module data caching method includes the following steps:
step S101, determining the number N of module data buffered in RAM, and determining the bit width A required by data transmission in RAM according to the data transmission speed M in USB and the actual system clock L; in this step, the number N of module data buffered in the current RAM is determined according to the area condition of the chip where the current RAM is located, and if the chip area is large, the value of N may be relatively small, that is, the number of RAMs that can be set on the current chip is large; on the contrary, if the chip area is small, the value of N needs to be relatively large, that is, the number of RAMs that can be set on the current chip is small.
Further, in the preferred embodiment of the present invention, determining the bit width a required for data transmission in the RAM specifically includes:
Figure BDA0002981522710000031
the data transmission speed M in the USB and the actual system clock L are both constant data transmission speed M in the USB. In practical application of the RAM, generally, the data transmission speed M in the USB is 480Mbps, the system clock L is 60M, that is, M/N is a constant of 8, and the bit width a required for data transmission in the RAM can be obtained according to the determination of the actual value of N, so as to ensure the bit width quantity required for data transmission of N modules. In a specific embodiment of the present invention, the value range of N is 1 to 16, and correspondingly, the value range of bit width a is 24-216Of course, the value of N can be flexibly adjusted according to the area of the actual chip, and is within the above range.
Step S102, adding ACK feedback identifications to N module data according to priority levels, wherein each ACK feedback identification comprises priority level information; in the step, each module data is provided with an ACK feedback identifier by adding the ACK feedback identifiers to the N module data according to the priority level, so that the module data can be identified according to the ACK feedback identifiers when the data is read/written, and the accuracy of reading/writing is ensured; in addition, each ACK feedback mark comprises priority level information, so that the ACK feedback marks can be sequentially carried out according to the priority levels when specific reading/writing is carried out subsequently, and the possibility of errors is reduced. As a preferred embodiment of the invention, the priority levels of the ACK feedback identifiers are respectively from 0 level to N-1 level, and the priority level of 0 level is higher than that of N-1 level, that is, the priority level of ACK0 is the highest, and the priority level of ACK1 is the next, until the priority level of ACK (N-1) is the lowest. And the priority level of the module data of continuous data reading/writing can be set as the lowest priority level so as to ensure the accuracy of data transmission.
Step S103, caching the N module data added with the ACK feedback identification into an RAM respectively; in this step, the N module data are respectively cached in the RAM, so that the N module data can respectively perform control operations, i.e., read/write operations, on the RAM.
Step S104, sequentially reading/writing the data of the N modules according to the priority level; in this step, according to the priority level on the ACK feedback identifier of each module data, N module data are sequentially read/written; specifically, in this step, when data is read/written, the first clock is input to the module data with the priority of 0, and then the other N-1 hour hands are sequentially input to the other N-1 module data.
Referring to fig. 2 and fig. 3, an embodiment of the single-RAM multi-module data caching method according to the present invention will be described by way of example.
In this example, as shown in fig. 2, the number N of module data buffered in the RAM is 4, that is, 4 module data operate the RAM simultaneously, and generally, the data transmission speed M in the USB is 480Mbps, and the actual data system clock L is 60M, according to the formula:
Figure BDA0002981522710000041
the data transmission bit width A required by the RAM is 32 bits, which is equivalent to 8 bits transmitted by one bit, and just 4 clocks are needed for data serial-parallel connectionConverting 4 data of 8 bits into 1 data of 32 bits; thus, ACK can input the first clock to the module data with the highest priority, and leave 3 clocks empty, and then can give the remaining 3 clock cycles to the remaining 3 module data, as shown in fig. 3, module 0 data is transmitted to the RAM input at one clock, and then the remaining three clocks can be transmitted to the RAM input by rearranging other modules.
As described above, according to the single RAM multi-module data caching method, the ACK feedback identifiers are added to the N module data according to the priority levels, each ACK feedback identifier includes priority level information, and the N module data are sequentially read/written according to the priority levels, so that after the plurality of module data are stored in one large RAM, the plurality of module data in the RAM can be respectively read/written according to the priority levels, and the plurality of module data are read/written according to the priority levels and the clock sequence, thereby ensuring the reading/writing accuracy, realizing the caching of the plurality of module data by a single RAM, reducing the chip area occupied by the RAM, correspondingly reducing the power consumption of the chip, and prolonging the service life of the chip.
The present invention has been described in connection with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, and is intended to cover various modifications, equivalent combinations, which are made in accordance with the spirit of the present invention.

Claims (6)

1. A single RAM multi-module data caching method is characterized by comprising the following steps:
a. determining the number N of module data buffered in the RAM, and determining the bit width A required by data transmission in the RAM according to the data transmission speed M in the USB and the actual system clock L;
b. adding ACK feedback identifications to N module data according to priority levels, wherein each ACK feedback identification comprises priority level information;
c. respectively caching the N module data added with the ACK feedback identification into an RAM;
d. and sequentially reading/writing the data of the N modules in the RAM according to the priority level.
2. The method for caching data of a single RAM and multiple modules according to claim 1, wherein the determining of the bit width a required for data transmission in the RAM in step a specifically comprises:
Figure FDA0002981522700000011
the data transmission speed M in the USB and the actual system clock L are both constant.
3. The single-RAM multi-module data caching method of claim 2, wherein in the step b, the priority levels on the ACK feedback identifiers are respectively from level 0 to level N-1, and the priority level of the level 0 is higher than the priority level of the level N-1.
4. The single RAM multi-module data caching method of claim 3, wherein in said step d, when data read/write is performed, the first clock is input to the module data with the priority of 0, and then the other N-1 hour hands are sequentially input to the other N-1 module data.
5. The method for caching single-RAM multi-chunk data according to claim 3, wherein the value range of N is 1-16, and correspondingly the value range of bit width A is 24-216。
6. The single-RAM multi-chunk data caching method of claim 4, wherein a priority level of the chunk data for consecutive data reads/writes is set to a lowest priority.
CN202110288714.7A 2021-03-18 2021-03-18 Single RAM multi-module data caching method Pending CN113076061A (en)

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Citations (10)

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US20050165876A1 (en) * 2004-01-26 2005-07-28 Fujitsu Limited Multiple-word multiplication-accumulation circuit and Montgomery modular multiplication-accumulation circuit
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CN105468305A (en) * 2015-12-09 2016-04-06 浪潮(北京)电子信息产业有限公司 Data caching method, apparatus and system
CN107086968A (en) * 2016-02-14 2017-08-22 中兴通讯股份有限公司 Traffic scheduling processing method and processing device
CN108401467A (en) * 2017-02-17 2018-08-14 深圳市大疆创新科技有限公司 The control method of storage device, chip and storage device
CN108958700A (en) * 2017-05-22 2018-12-07 深圳市中兴微电子技术有限公司 A kind of first in first out data buffer and data cached method
CN111124961A (en) * 2019-12-30 2020-05-08 武汉先同科技有限公司 Method for realizing conversion from single-port RAM to pseudo-dual-port RAM in continuous read-write mode

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003271378A (en) * 2002-03-15 2003-09-26 Fuji Xerox Co Ltd Storage device
CN1495621A (en) * 2002-06-24 2004-05-12 �¿���˹�����ɷ����޹�˾ Parallel input/output data transmission controller
US20050165876A1 (en) * 2004-01-26 2005-07-28 Fujitsu Limited Multiple-word multiplication-accumulation circuit and Montgomery modular multiplication-accumulation circuit
JP2006012235A (en) * 2004-06-23 2006-01-12 Fuji Xerox Co Ltd Storage device
CN1858695A (en) * 2006-01-24 2006-11-08 华为技术有限公司 Method for increasing RAM utilizing efficiency
CN105468305A (en) * 2015-12-09 2016-04-06 浪潮(北京)电子信息产业有限公司 Data caching method, apparatus and system
CN107086968A (en) * 2016-02-14 2017-08-22 中兴通讯股份有限公司 Traffic scheduling processing method and processing device
CN108401467A (en) * 2017-02-17 2018-08-14 深圳市大疆创新科技有限公司 The control method of storage device, chip and storage device
CN108958700A (en) * 2017-05-22 2018-12-07 深圳市中兴微电子技术有限公司 A kind of first in first out data buffer and data cached method
CN111124961A (en) * 2019-12-30 2020-05-08 武汉先同科技有限公司 Method for realizing conversion from single-port RAM to pseudo-dual-port RAM in continuous read-write mode

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