CN113052095B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN113052095B CN113052095B CN202110343317.5A CN202110343317A CN113052095B CN 113052095 B CN113052095 B CN 113052095B CN 202110343317 A CN202110343317 A CN 202110343317A CN 113052095 B CN113052095 B CN 113052095B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention discloses a display panel and a display device. The display panel includes: the device comprises a fingerprint identification unit, Q first grid driving circuits, a driving chip, a first decoding circuit and M first signal lines; the driving chip comprises M first signal output ends; the first decoding circuit comprises M first signal input ends, a second signal input end and N signal output ends; the first signal output end and the first signal input end are electrically connected through a first signal line; the second signal output end and the second signal input end are electrically connected through a second signal line; each first grid driving circuit is connected with a signal output end; the first signal output end outputs a pulse signal, and the pulse signal comprises a first level signal and a second level signal; the second signal output end outputs a third level signal, the potential of the first level signal is higher than that of the second level signal, and the potential of the second level signal is higher than that of the third level signal. Thus, the bezel width can be reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of science and technology, more and more functions are integrated into a display device, for example, a variety of display devices with fingerprint identification functions, such as mobile phones, tablet computers, smart wearable devices, and the like, are currently on the market.
With the increase of application scenes of the fingerprint identification function, the fingerprint identification area is gradually pushed from partial area to full-screen fingerprint identification. In the existing full-screen fingerprint identification technology, a fingerprint identification unit is usually partitioned in a display device, the fingerprint identification units in different areas are driven by different driving circuits, and at least one signal line is arranged between each driving circuit and each driving chip, so that the frame of the display device is wider, and the display device is not favorable for realizing narrow frames.
Disclosure of Invention
The invention provides a display panel and a display device, which are used for realizing a narrow frame.
In a first aspect, an embodiment of the present invention provides a display panel, including: a display area and a non-display area surrounding the display area;
the display area comprises a plurality of fingerprint identification units which are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are crossed;
the non-display area comprises Q first grid driving circuits and driving chips which are arranged along the second direction, and the driving chips are positioned on one side of the display area along the second direction;
the first grid driving circuit is electrically connected with at least two rows of fingerprint identification units extending along the first direction;
the driving chip comprises M first signal output ends;
the non-display area further comprises a first decoding circuit and M first signal lines, wherein the first decoding circuit comprises M first signal input ends, a second signal input end and N signal output ends; wherein M is more than or equal to 1 and Q is more than or equal to N, and M, Q and N are positive integers;
the first signal output ends correspond to the first signal input ends one by one, and the first signal output ends are electrically connected with the first signal input ends corresponding to the first signal output ends through one first signal wire; the second signal output end and the second signal input end are electrically connected through a second signal line; each first grid driving circuit is correspondingly connected to one signal output end of the first decoding circuit;
the first signal output end is used for outputting a pulse signal, and the pulse signal comprises a first level signal and a second level signal; the second signal output end is used for outputting a third level signal, the electric potential of the first level signal is higher than that of the second level signal, and the electric potential of the second level signal is higher than that of the third level signal.
In a second aspect, an embodiment of the present invention further provides a display device, where the display device includes the display panel according to any embodiment of the present invention.
The display panel provided by the embodiment of the invention has the advantages that the non-display area comprises Q first grid driving circuits, the driving chip, the first decoding circuit and M first signal lines, the driving chip comprises M first signal output ends, the first decoding circuit comprises M first signal input ends and N signal output ends, the first signal output ends are electrically connected with the first signal input ends corresponding to the first signal output ends through one first signal line, each first grid driving circuit is correspondingly connected with one signal output end of the first decoding circuit, and Q is more than or equal to 1 and less than or equal to N, so that the driving chip provides signals for a large number of first grid driving circuits through a small number of first signal lines, the number of the signal lines is effectively reduced, the problem of wider frame caused by more signal lines in the prior art is solved, and the effect of narrow frame is realized.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first decoding circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a decoding unit according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another decoding unit according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a decoding unit according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of an inverter according to an embodiment of the present invention;
FIG. 7 is a circuit diagram of another decoding unit according to an embodiment of the present invention;
FIG. 8 is a circuit diagram of another inverter according to an embodiment of the present invention;
FIG. 9 is a simulation of the output of the inverter of FIG. 8 as a function of threshold voltage;
FIG. 10 is a circuit diagram of a decoding unit according to another embodiment of the present invention;
FIG. 11 is a circuit diagram of another inverter according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a voltage boosting circuit according to an embodiment of the present invention;
FIG. 13 is a circuit diagram of a boost circuit according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of a display panel according to another embodiment of the present invention;
FIG. 15 is a schematic diagram of a display panel according to another embodiment of the present invention;
fig. 16 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 17 is a schematic diagram of another display panel according to an embodiment of the present invention;
fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
In view of the technical problems mentioned in the background, embodiments of the present invention provide a display panel including a display area and a non-display area surrounding the display area; the display area comprises a plurality of fingerprint identification units which are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are crossed; the non-display area comprises Q first grid driving circuits and driving chips which are arranged along a second direction, and the driving chips are positioned on one side of the display area along the second direction; the first grid driving circuit is electrically connected with at least two rows of fingerprint identification units extending along a first direction; the driving chip comprises M first signal output ends; the non-display area also comprises a first decoding circuit and M first signal lines, wherein the first decoding circuit comprises M first signal input ends, a second signal input end and N signal output ends; wherein M is more than or equal to 1 and Q is more than or equal to N, and M, Q and N are positive integers; the first signal output ends correspond to the first signal input ends one by one, and the first signal output ends are electrically connected with the first signal input ends corresponding to the first signal output ends through a first signal wire; the second signal output end and the second signal input end are electrically connected through a second signal line; each first grid driving circuit is correspondingly connected to one signal output end of the first decoding circuit; the first signal output end is used for outputting a pulse signal, and the pulse signal comprises a first level signal and a second level signal; the second signal output end is used for outputting a third level signal, the potential of the first level signal is higher than that of the second level signal, and the potential of the second level signal is higher than that of the third level signal. By adopting the technical scheme, the driving chip can provide signals for a large number of first gate driving circuits through a small number of first signal lines, the number of the signal lines is effectively reduced, the problem of wide frame caused by a large number of signal lines in the prior art is solved, and the effect of narrow frame is realized. Further, since the potential of the second level signal is higher than the potential of the third level signal, the waveform stability of the output signal of the first decoding circuit can be improved.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to fig. 1, the display panel includes a display area AA and a non-display area DA surrounding the display area AA; the display area AA includes a plurality of fingerprint identification units 10 arranged in an array along a first direction Y and a second direction X, where the first direction Y intersects with the second direction X; the non-display area DA includes Q first gate driving circuits 20 and driving chips 30 arranged along the second direction X, and the driving chips 30 are located at one side of the display area AA along the second direction X; the first gate driving circuit 20 is electrically connected to at least two rows of fingerprint identification units 10 extending along the first direction Y; the driving chip 30 includes M first signal output terminals STV; the non-display area DA further includes a first decoding circuit 40 and M first signal lines 51, the first decoding circuit 40 including M first signal input terminals 401, a second signal input terminal 402, and N signal output terminals 403; wherein M is more than or equal to 1 and Q is more than or equal to N, and M, Q and N are positive integers; the first signal output ends STV correspond to the first signal input ends 401 one by one, and the first signal output ends STV are electrically connected with the corresponding first signal input ends 401 through a first signal line 51; the second signal output terminal VGL2 and the second signal input terminal 402 are electrically connected through a second signal line 52; each first gate driving circuit 20 is correspondingly connected to one signal output end 403 of the first decoding circuit 40; the first signal output terminal STV is used for outputting a pulse signal, and the pulse signal comprises a first level signal and a second level signal; the second signal output terminal VGL2 is used for outputting a third level signal, the potential of the first level signal is higher than that of the second level signal, and the potential of the second level signal is higher than that of the third level signal.
Specifically, the display area AA has a display function for displaying a to-be-displayed picture, and the non-display area DA has no display function for placing a circuit and the like.
Specifically, the fingerprint identification unit 10 is used for implementing a fingerprint identification function, and a specific embodiment thereof may be set by a person skilled in the art according to practical situations, and is not limited herein. Illustratively, the fingerprinting unit 10 may include a "3T1D" fingerprinting circuit. The fingerprint identification units 10 are arranged in a row along a first direction Y and a row along a second direction X, wherein the first direction Y intersects with the second direction X, and optionally the first direction Y is perpendicular to the second direction X.
Specifically, the first gate driving circuit 20 is used to provide a driving signal to the fingerprint identification unit 10 electrically connected to the first gate driving circuit, and the specific implementation of the first gate driving circuit 20 and the number of rows of the fingerprint identification unit 10 connected to each first gate driving circuit 20 can be set by those skilled in the art according to practical situations, and are not limited herein.
Specifically, the driving chip 30 includes M first signal output terminals STV, for example, fig. 1 shows that the M first signal output terminals STV are the first signal output terminal STV1, the first signal output terminal STV2, the first signal output terminal STV3, the first signal output terminal STV4 and the first signal output terminal STV5, respectively, the first decoding circuit 40 includes M first signal input terminals 401, and the M first signal output terminals STV and the M first signal input terminals 401 correspond to each other one by one and are electrically connected through the first signal line 51. The first signal output terminal STV is used for outputting a pulse signal including a first level signal (high level) and a second level signal (low level), and the waveforms of the M pulse signals output by the M first signal output terminals STV may be set by those skilled in the art according to practical situations, and are not limited herein. The driving chip 30 further includes a second signal output terminal VGL2, the first decoding circuit 40 further includes a second signal input terminal 402 and N signal output terminals 403, and the second signal input terminal 402 and the second signal output terminal VGL2 are electrically connected through a second signal line 52. The second signal output terminal VGL2 is configured to output a third level signal (low level), and the first decoding circuit 40 is configured to generate N enable signals according to the M pulse signals and the third level signal, wherein each enable signal is output by one signal output terminal 403. For each first gate driving circuit 20, when the received enable signal is at an effective level, the first gate driving circuit 20 starts to operate, and drives the fingerprint identification unit 10 electrically connected with the first gate driving circuit to perform fingerprint identification; when it receives the enable signal at the inactive level, the first gate driving circuit 20 is not turned on, and the fingerprint recognition unit 10 electrically connected thereto does not perform fingerprint recognition. In other words, the driving chip 30 realizes the function of controlling some of the first gate driving circuits 20 to start operation through the first decoding circuit 40.
It can be understood that, the number of the first signal lines 51 between the driving chip 30 and the first decoding circuit 40 is M, and the number of the first gate driving circuits 20 is Q, where M < Q, that is, by providing the first decoding circuit 40, the driving chip 30 provides the enable signal for a greater number of the first gate driving circuits 20 through a smaller number of the first signal lines 51, so as to effectively reduce the number of the signal lines, which is beneficial to implement the narrow frame of the display panel.
It is also understood that since the potential of the second level signal is higher than the potential of the third level signal, the waveform stability of the output signal of the first decoding circuit 40 can be improved.
It should be noted that the number of the first gate driving circuits 20 is Q, the number of the signal output terminals 403 of the first decoding circuit 40 is N, Q is less than or equal to N, fig. 1 exemplarily shows that the number of the signal output terminals 403 of the first decoding circuit 40 is the same as that of the first gate driving circuits 20, and the signal output terminals 403 of the first decoding circuit 40 are connected in a one-to-one correspondence manner, in other embodiments of the present invention, the number of the signal output terminals 403 of the first decoding circuit 40 may also be greater than that of the first gate driving circuits 20, and each first gate driving circuit 20 is connected to one signal output terminal 403 of the first decoding circuit 40. Further, fig. 1 exemplarily shows that the number of the first signal lines 51 is 5, but the invention is not limited thereto, and the number of the first signal lines 51 may also be other values in other embodiments of the invention.
In the display panel provided by the embodiment of the invention, the first decoding circuit 40 is arranged, so that the driving chip 30 provides enable signals to a large number of first gate driving circuits 20 through the first decoding circuit 40 by using a small number of first signal lines 51, and thus, the number of signal lines can be effectively reduced, the problem of wider frame caused by a large number of signal lines in the prior art is solved, and the effect of narrow frame is realized. Further, since the potential of the second level signal is higher than the potential of the third level signal, the waveform stability of the output signal of the first decoding circuit can be improved.
Specifically, the following description is made of typical examples of the first decoding circuit 40, but the present invention is not limited thereto.
Fig. 2 is a schematic structural diagram of a first decoding circuit according to an embodiment of the present invention. Referring to fig. 2, optionally, the first decoding circuit 40 includes N decoding units 410, and the decoding units 410 include M first sub-signal input terminals, a second sub-signal input terminal, and a signal output terminal 403; in the same decoding unit 410, the first sub-signal input ends correspond to the first signal lines 51 one to one, and the first sub-signal input ends are electrically connected to the corresponding first signal lines 51; the second sub-signal input terminal of each decoding unit 410 is electrically connected to the second signal line 52; each first gate driving circuit 20 is correspondingly connected to a signal output terminal 403 of one decoding unit 410.
Specifically, each decoding unit 410 includes M first sub-signal input ends, a second sub-signal input end, and a signal output end 403, the M first sub-signal input ends in the same decoding unit 410 are electrically connected to the M first signals in a one-to-one correspondence manner, the first sub-signal input ends are used for receiving pulse signals, the second sub-signal input end of each decoding unit 410 is electrically connected to the second signal line 52, and the second sub-signal input end is used for receiving a third level signal. In this way, each decoding unit 410 generates an enable signal from the M pulse signals it receives, and the third level signal, and outputs the enable signal from the signal output terminal 403.
Fig. 3 is a schematic structural diagram of a decoding unit according to an embodiment of the present invention. Referring to fig. 3, optionally, the decoding unit 410 includes a nor gate 411 and M inverters 412, the nor gate 411 includes M first gate modules 4111 and one second gate module 4112; a first terminal of the second gating module 4112 is electrically connected to the fourth level signal terminal VGH, and a second terminal of the second gating module 4112 is electrically connected to the signal output terminal 403 of the decoding unit 410; the first gating modules 4111 correspond to the first signal lines 51 one to one, the control terminals of the first gating modules 4111 are electrically connected to the corresponding first signal lines 51, the first terminals of the first gating modules 4111 are electrically connected to the second signal lines 52, and the second terminals of the first gating modules 4111 are electrically connected to the signal output terminals 403 of the decoding units 410; the control terminal of the first gating module 4111 is electrically connected to the corresponding first signal line 51 through an inverter 412, or directly electrically connected to the corresponding first signal line 51.
Specifically, the decoding unit 410 includes M first gating modules 4111, one second gating module 4112, and M inverters 412, a control terminal of the first gating module 4111 is electrically connected to a corresponding first signal line 51 through one inverter 412, or is directly electrically connected to the corresponding first signal line 51, and connection conditions between the control terminal of the first gating module 4111 in each decoding unit 410 in the first decoding circuit 40 and the first signal line 51 are different, so that each decoding unit 410 in the first decoding circuit 40 can be controlled by fewer first signal lines 51 to output an enable signal to the first gate driving circuit 20 in a time-sharing manner.
It should be noted that fig. 3 only exemplarily shows a schematic structure of one of the decoding units 410 in the first decoding circuit 40, and the structures of the other decoding units 410 in the first decoding circuit 40 may be configured with reference to fig. 3, which is not repeated herein.
Fig. 4 is a schematic structural diagram of another decoding unit according to an embodiment of the present invention. Referring to fig. 4, optionally, each decoding unit 410 in the decoding circuit shares M inverters 412. Thus, the number of inverters 412 can be reduced, the frame can be further narrowed, and the cost can be reduced.
Fig. 5 is a circuit diagram of a decoding unit according to an embodiment of the present invention. Referring to fig. 5, optionally, the first gating module 4111 includes a first switch T1, and the second gating module 4112 includes a second switch T2; a gate and a first pole of the second switch T2 are both electrically connected to the fourth level signal terminal VGH, and a second pole of the second switch T2 is electrically connected to the signal output terminal 403 of the decoding unit 410; the first switches T1 correspond to the first signal lines 51 one to one, the gates of the first switches T1 are electrically connected to the corresponding first signal lines 51, the first poles of the first switches T1 are electrically connected to the second signal lines 52, and the second poles of the first switches T1 are electrically connected to the signal output end 403 of the decoding unit 410; the gate of the first switch T1 is electrically connected to the corresponding first signal line 51 through one inverter 412, or is directly electrically connected to the corresponding first signal line 51.
Optionally, the fourth level signal output by the fourth level signal terminal VGH is the same as the first level signal. Therefore, the first level signal and the fourth level signal can be generated by the same circuit module inside the driving chip 30, which is beneficial to simplifying the circuit structure inside the driving chip 30 and reducing the size of the driving chip 30.
Specifically, the embodiment of the inverter 412 can be set by a person skilled in the art according to practical situations, and is not limited herein. Illustratively, fig. 6 is a circuit element diagram of an inverter according to an embodiment of the present invention. Referring to fig. 6, the inverter 412 includes a fifth switch T5 and a sixth switch T6, a gate of the fifth switch T5 is electrically connected to the corresponding first signal line 51, a first pole of the fifth switch T5 is electrically connected to the sixth level signal terminal VGL1, and a second pole of the fifth switch T5 is the output terminal 4121 of the inverter 412; a gate and a first pole of the sixth switch T6 are electrically connected to the fourth level signal terminal VGH, and a second pole of the sixth switch T6 is electrically connected to a second pole of the fifth switch T5. Optionally, the sixth level signal output by the sixth level signal terminal VGL1 is the same as the second level signal. Thus, the second level signal and the sixth level signal can be generated by the same circuit module inside the driving chip 30, which is beneficial to simplifying the circuit structure inside the driving chip 30 and reducing the size of the driving chip 30.
In particular, with continued reference to fig. 5, the decoding unit 410 operates as follows: when at least one first switch T1 is turned on, the signal output terminal 403 of the decoding unit 410 outputs a third level signal, and when the first switch T1 is turned off completely, the signal output terminal 403 of the decoding unit 410 outputs a signal of the fourth level signal terminal VGH.
It can be understood that, when the first switch T1 is in the off state, since the voltage of the third level signal is lower than the potential of the second level signal, even if the threshold voltage of the first switch T1 fluctuates, the first switch T1 can be in the off state, the high level of the signal output terminal 403 of the decoding unit 410 will not be pulled down, i.e. the problem of high voltage dip will not be caused, and finally the waveform of the signal output terminal 403 of the decoding unit 410 is more stable.
It should be noted that fig. 5 only exemplarily shows a circuit schematic diagram of one decoding unit 410 in the first decoding circuit 40, and the circuit structures of other decoding units 410 in the first decoding circuit 40 may be configured with reference to fig. 5, which is not repeated herein.
Fig. 7 is a circuit diagram of another decoding unit according to an embodiment of the present invention. Referring to fig. 7, optionally, the second gating module 4112 further includes a third switch T3 and a first capacitor C1; a gate and a first pole of the third switch T3 are both electrically connected to the fourth level signal terminal VGH, and a second pole of the third switch T3 is electrically connected to the first plate of the first capacitor C1 and the gate of the second switch T2, respectively; the second plate of the first capacitor C1 is electrically connected to the signal output terminal 403 of the decoding unit 410.
Illustratively, fig. 8 is a circuit element diagram of another inverter provided in an embodiment of the present invention. Referring to fig. 8, optionally, the inverter 412 further includes a seventh switch T7 and a third capacitor C3, a gate and a first pole of the seventh switch T7 are electrically connected to the fourth level signal terminal VGH, and a second pole of the third switch T3 is electrically connected to the first plate of the third capacitor C3 and the gate of the sixth switch T6, respectively; the second plate of the third capacitor C3 is electrically connected to the second pole of the sixth switch T6. It can be understood that, since the third capacitor C3 can pull up the gate voltage of the sixth switch T6, the sixth switch T6 can be in a fully-on state, that is, the sixth switch T6 can be in a relatively stable on state, so that even if the threshold voltage of the fifth switch T5 fluctuates, the influence of the fifth switch T5 on the sixth switch T6 is small, and the stability of the waveform of the signal output by the output terminal of the inverter 412 is not affected. Illustratively, FIG. 9 is a simulation of the output of the inverter of FIG. 8 as a function of threshold voltage. It can be seen from fig. 9 that the threshold voltage fluctuation of the fifth switch T5 has little influence on the output of the inverter 412, and the output stability of the inverter 412 is good.
It can be understood that, based on the same principle as the inverter 412 shown in fig. 8, by arranging the second gating module 4112 further including the third switch T3 and the first capacitor C1, the second switch T2 can be in a fully-on state and in a relatively stable on state, so that even if the threshold voltage of the first switch T1 fluctuates, the influence of the first switch T1 on the second switch T2 is small and will not affect the stability of the waveform of the signal output from the signal output terminal 403 of the signal decoding unit 410. It can be seen that the signal waveform output by the signal output terminal 403 of the decoding unit 410 can be further stabilized by adding the third switch T3 and the first capacitor C1.
It should be noted that fig. 7 only exemplarily shows a circuit schematic diagram of one decoding unit 410 in the first decoding circuit 40, and the circuit structures of other decoding units 410 in the first decoding circuit 40 may be configured with reference to fig. 7, which is not repeated herein.
Fig. 10 is a circuit element diagram of another decoding unit according to an embodiment of the present invention. Referring to fig. 10, optionally, the first gating module 4111 includes a first switch T1, and the second gating module 4112 includes a first resistor R1; a first end of the first resistor R1 is electrically connected to the fourth level signal end VGH, and a second end of the first resistor R1 is electrically connected to the signal output end 403 of the decoding unit 410; the first switches T1 correspond to the first signal lines 51 one to one, and the gates of the first switches T1 are electrically connected to the corresponding first signal lines 51, the first poles of the first switches T1 are electrically connected to the second signal lines 52, and the second poles of the first switches T1 are electrically connected to the signal output terminals 403 of the decoding units 410; the gate of the first switch T1 is electrically connected to the corresponding first signal line 51 through one inverter 412, or is directly electrically connected to the corresponding first signal line 51.
Illustratively, fig. 11 is a circuit element diagram of another inverter according to an embodiment of the present invention. Referring to fig. 11, the inverter 412 includes a fifth switch T5 and a second resistor R2, a gate of the fifth switch T5 is electrically connected to the corresponding first signal line 51, a first pole of the fifth switch T5 is electrically connected to the sixth level signal terminal VGL1, and a second pole of the fifth switch T5 is the output terminal 4121 of the inverter 412; one end of the second resistor R2 is electrically connected to the fourth level signal terminal VGH, and the other end is electrically connected to the second pole of the fifth switch T5. It is understood that when the gate of the fifth switch T5 receives the first level signal, the fifth switch T5 is turned on, and the output end 4121 of the inverter 412 outputs a signal with a potential of: vgl1+ (r 1/(r 1+ r 2)), (vgh-vgl 1); when the gate of the fifth switch T5 receives the second level signal, the fifth switch T5 is turned off, and the potential of the signal output by the output terminal 4121 of the inverter 412 is about vgh-I × R2, where vgl1 is the voltage of the sixth level signal, vgh is the voltage of the fourth level signal, R1 is the resistance of the fifth switch T5, R2 is the resistance of the second resistor R2, and I is the leakage current generated when the fifth switch T5 is turned off. Since the leakage current of the fifth switch T5 is small when it is turned off, the potential of the signal output from the output terminal 4121 of the inverter 412 is close to vgh, that is, the output of the inverter 412 is not affected by the fifth switch T5, and therefore, when the fifth switch T5 is in the off state, even if the threshold voltage of the fifth switch T5 fluctuates, the waveform stability of the signal output from the output terminal 4121 of the inverter 412 is not affected.
Specifically, the first decoding unit 410 operates as follows: when at least one first switch T1 is turned on, the signal output terminal 403 of the decoding unit 410 outputs a third level signal, and when the first switches T1 are all turned off, the signal output terminal 403 of the decoding unit 410 outputs a signal of the fourth level signal terminal VGH.
It can be understood that, based on the same principle as the inverter 412 shown in fig. 11, by providing the decoding unit 410 including the first resistor R1, the output of the decoding unit 410 can be made unaffected by the first switch T1, and therefore, when the first switch T1 is in the off state, even if the threshold voltage of the first switch T1 fluctuates, the waveform stability of the output signal of the signal output terminal 403 of the decoding unit 410 is not affected. Moreover, when the first switch T1 is in the off state, since the voltage of the third level signal is lower than the potential of the second level signal, even if the threshold voltage of the first switch T1 fluctuates, the first switch T1 can be in the off state, the high level of the signal output end 403 of the decoding unit 410 is not pulled down, that is, the problem of sudden high voltage drop is not caused, and finally, the waveform of the signal output end 403 of the decoding unit 410 is more stable.
It should be noted that fig. 10 only exemplarily shows a circuit schematic diagram of one decoding unit 410 in the first decoding circuit 40, and the circuit structures of other decoding units 410 in the first decoding circuit 40 may be configured with reference to fig. 10, which is not repeated here.
On the basis of the above technical solution, fig. 12 is a schematic structural diagram of a voltage boost circuit according to an embodiment of the present invention. Referring to fig. 12, optionally, the display panel further includes a voltage boost circuit 60, the control terminal of the voltage boost circuit 60 is electrically connected to the fourth level signal terminal VGH, the first input terminal of the voltage boost circuit 60 is electrically connected to the fifth level signal terminal Vd, the second input terminal of the voltage boost circuit 60 is electrically connected to the sixth level signal terminal VGL1, and the output terminal of the voltage boost circuit 60 is the second signal output terminal VGL2. In this way, the signal output by the sixth level signal terminal VGL1 can be boosted to obtain the third level signal.
Fig. 13 is a circuit element diagram of a voltage boost circuit according to an embodiment of the present invention. Referring to fig. 13, optionally, the voltage boost circuit 60 includes a fourth switch T4 and a second capacitor C2; a gate of the fourth switch T4 is electrically connected to the fourth level signal terminal VGH, a first pole of the fourth switch T4 is electrically connected to the second signal line 52, and a second pole of the fourth switch T4 is electrically connected to the sixth level signal terminal VGL 1; a first pole plate of the second capacitor C2 is electrically connected to a first pole of the fourth switch T4, and a second pole of the second capacitor C2 is electrically connected to the fifth level signal terminal Vd. Thus, the booster circuit 60 having a simple structure can be obtained. It can also be understood that, when the voltage boost circuit 60 is located outside the driver chip 30, a pin used as the sixth level signal terminal VGL1 may be reserved on the driver chip 30, and a pin used as the second signal output terminal VGL2 does not need to be reserved on the driver chip 30, and the voltage boost circuit 60 disposed on the driver chip 30 may boost a signal output by the sixth level signal terminal VGL1 to obtain the third level signal, in other words, the third level signal and the sixth level signal may be provided through the same pin on the driver chip 30. Meanwhile, since the driving chip does not need to output the third level signal, the power consumption of the driving chip 30 can be reduced.
Fig. 14 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 14, optionally, the boost circuit 60 is integrated in the driver chip 30, and the second signal output terminal VGL2 is located on the driver chip 30. Therefore, the circuit structures used for generating the sixth level signal in the boost circuit 60 and the driving chip 30 can be electrically connected through the processes of punching, patterning the conductive layer and the like in the preparation process of the driving chip 30, and a signal line which is positioned outside the driving chip 30 and electrically connected with the boost circuit 60 and the driving chip 30 can be omitted, so that the integration of the circuit structures used for generating the sixth level signal in the boost circuit 60 and the driving chip 30 is better, the occupied area is smaller, and the frame narrowing is facilitated.
It should be noted that fig. 14 is not illustrated for convenience, and a specific connection relationship between the M inverters 412 in the decoding unit 410 and the nor gate 411 is not illustrated, which can be understood by those skilled in the art from the foregoing description, and is not described herein again.
With continued reference to fig. 14, optionally, the decoding units 410 are arranged along the second direction X and located at one side of the first gate driving circuit 20 electrically connected thereto. Thus, the plurality of decoding units 410 and the plurality of first gate driving circuits 20 are regularly arranged, which is beneficial to reducing the wiring difficulty and further beneficial to realizing the narrow frame of the display panel.
Fig. 15 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 15, optionally, the voltage boost circuit 60 is located outside the driver chip 30, and the voltage boost circuit 60 and the first decoding circuit 40 are arranged along the second direction X and located on a side of the first decoding circuit 40 close to the driver chip 30. Thus, the number of signal terminals (pins) of the driving chip 30 can be reduced, and the traces for transmitting the third level signal and the sixth level signal in the lower bezel region can be multiplexed, which is beneficial to reducing the width of the lower bezel along the second direction X.
Fig. 16 is a schematic structural diagram of a display panel according to an embodiment of the present invention. With continued reference to fig. 15 and 16, optionally, each decoding unit 410 shares M inverters 412; the nor gates 411 of the decoding units 410 are arranged along the second direction X and located at one side of the first gate driving circuit 20 electrically connected thereto; the M inverters 412 are located on a side of the nor gate 411 closest to the driving chip 30, which is close to the driving chip 30. Thus, the number of inverters 412 can be reduced, the frame can be further narrowed, and the cost can be reduced.
Fig. 17 is a schematic structural diagram of another display panel according to an embodiment of the present invention. Referring to fig. 17, optionally, the non-display area DA further includes Q second gate driving circuits 70 arranged in the second direction X; the second gate driving circuit 70 is electrically connected to at least two rows of fingerprint identification units 10 extending along the first direction Y; the driving chip 30 further includes M third signal output terminals stv; the non-display area DA further includes a second decoding circuit 80 and M third signal lines 53, the second decoding circuit 80 including M third signal input terminals, a fourth signal input terminal, and N signal output terminals; the second decoding circuit 80 is the same as the first decoding circuit 40; the third signal output end stv corresponds to the third signal input end one by one, and the third signal output end stv is electrically connected with the third signal input end corresponding to the third signal output end stv through a third signal line 53; the fourth signal output end and the fourth signal input end are electrically connected through a fourth signal line 54; each second gate driving circuit 70 is correspondingly connected to one signal output end of the second decoding circuit 80; the third signal output terminal stv is used for outputting a pulse signal, and the fourth signal output terminal is used for outputting a third level signal.
Specifically, the second gate driving circuit 70 is used to provide a driving signal to the fingerprint identification unit 10 electrically connected thereto, and the specific implementation of the second gate driving circuit 70 and the number of rows of the fingerprint identification units 10 connected to each second gate driving circuit 70 can be set by those skilled in the art according to practical situations, and are not limited herein.
Specifically, the driving chip 30 includes M third signal output terminals stv, for example, in fig. 17, the M third signal output terminals stv are respectively a third signal output terminal stv1, a third signal output terminal stv2, a third signal output terminal stv3, a third signal output terminal stv4, and a third signal output terminal stv5, the first decoding circuit 40 includes M third signal input terminals, and the M third signal output terminals stv and the M third signal input terminals are in one-to-one correspondence and electrically connected through a third signal line 53. The third signal output terminal stv is used for outputting a pulse signal including a first level signal (high level) and a second level signal (low level), and the waveforms of the M pulse signals output by the M third signal output terminals stv may be set by those skilled in the art according to practical situations, and are not limited herein. The driving chip 30 further includes a fourth signal output terminal Vgl2, and the first decoding circuit 40 further includes a fourth signal input terminal and N signal output terminals, and the fourth signal input terminal is electrically connected to the fourth signal output terminal Vgl2 through a fourth signal line 54. The fourth signal output terminal Vgl2 is used for outputting a third level signal (low level), and the first decoding circuit 40 is used for generating N enable signals according to the M pulse signals and the third level signal, wherein each enable signal is output by one signal output terminal. For each second gate driving circuit 70, when the received enable signal is at an effective level, the second gate driving circuit 70 is turned on to drive the fingerprint identification unit 10 electrically connected thereto to perform fingerprint identification; when it receives the enable signal as an invalid level, the second gate driving circuit 70 is not turned on, and the fingerprint recognition unit 10 electrically connected thereto does not perform fingerprint recognition. In other words, the driving chip 30 realizes the function of controlling some of the second gate driving circuits 70 to start operation through the second decoding circuit 80.
It can be understood that the number of the third signal lines 53 between the driving chip 30 and the second decoding circuit 80 is M, the number of the second gate driving circuits 70 is Q, and M < Q, that is, by providing the second decoding circuit 80, the driving chip 30 provides the enable signals to the greater number of second gate driving circuits 70 through the smaller number of third signal lines 53, so as to effectively reduce the number of the signal lines, which is beneficial to realizing the narrow frame of the display panel.
It is also understood that since the potential of the second level signal is higher than the potential of the third level signal, the waveform stability of the output signal of the second decoding circuit 80 can be improved.
It should be noted that the number of the second gate driving circuits 70 is Q, the number of the signal output terminals of the second decoding circuit 80 is N, Q is less than or equal to N, fig. 17 exemplarily shows that the number of the signal output terminals of the second decoding circuit 80 is the same as that of the second gate driving circuits 70, and the signal output terminals are connected in a one-to-one correspondence manner, in other embodiments of the present invention, the number of the signal output terminals of the second decoding circuit 80 may also be greater than that of the second gate driving circuits 70, and each second gate driving circuit 70 is only required to be correspondingly connected to one signal output terminal of the second decoding circuit 80. Also, fig. 1 exemplarily shows that the number of the third signal lines 53 is 5, but the invention is not limited thereto, and the number of the third signal lines 53 may also be other values in other embodiments of the invention.
With reference to fig. 17, optionally, the first gate driving circuit 20 and the second gate driving circuit 70 are respectively located at two sides of the display area AA along the first direction Y.
It can be understood that the first gate driving circuit 20 and the second gate driving circuit 70 are respectively located at two sides of the display area AA along the first direction Y, so as to prevent the first gate driving circuit 20 and the second gate driving circuit 70 from being both disposed at the same side of the display area AA, which is further beneficial to realizing a narrow frame of the display panel.
With continued reference to fig. 17, optionally, the first gate driving circuits 20 and the second gate driving circuits 70 are in one-to-one correspondence, and the first gate driving circuits 20 and the second gate driving circuits 70 corresponding thereto are electrically connected to the same fingerprint identification unit 10.
It can be understood that the first gate driving circuit 20 and the corresponding second gate driving circuit 70 are electrically connected to the same fingerprint identification unit 10, and the driving methods of the first gate driving circuit 20 and the second gate driving circuit 70 in the display panel are the same, so that the driving capability of the display panel is effectively improved, and the power consumption is reduced.
Based on the above inventive concept, an embodiment of the present invention further provides a display device, and fig. 18 is a schematic structural diagram of the display device according to the embodiment of the present invention. Referring to fig. 18, the display device 200 includes the display panel 100 provided in the above embodiment. Therefore, the display device 200 provided by the embodiment of the invention also has the beneficial effects described in the above embodiments, and the description thereof is omitted here. For example, the display device 200 may include a display device such as a mobile phone, a computer, and a smart wearable device, which is not limited in the embodiment of the present invention.
It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.
Claims (14)
1. A display panel characterized by comprising a display area and a non-display area surrounding the display area;
the display area comprises a plurality of fingerprint identification units which are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are crossed;
the non-display area comprises Q first grid driving circuits and driving chips which are arranged along the second direction, and the driving chips are positioned on one side of the display area along the second direction;
the first grid driving circuit is electrically connected with at least two rows of the fingerprint identification units extending along the first direction;
the driving chip comprises M first signal output ends and a second signal output end;
the non-display area also comprises a first decoding circuit and M first signal lines, wherein the first decoding circuit comprises M first signal input ends, a second signal input end and N signal output ends; wherein M is more than or equal to 1 and Q is more than or equal to N, and M, Q and N are positive integers;
the first signal output ends are in one-to-one correspondence with the first signal input ends, and the first signal output ends are electrically connected with the first signal input ends corresponding to the first signal output ends through one first signal wire; the second signal output end and the second signal input end are electrically connected through a second signal line; each first grid driving circuit is correspondingly connected to one signal output end of the first decoding circuit;
the first signal output end is used for outputting a pulse signal, and the pulse signal comprises a first level signal and a second level signal; the second signal output end is used for outputting a third level signal, the electric potential of the first level signal is higher than that of the second level signal, and the electric potential of the second level signal is higher than that of the third level signal;
the display panel further comprises a booster circuit, a control end of the booster circuit is electrically connected with a fourth level signal end, a first input end of the booster circuit is electrically connected with a fifth level signal end, a second input end of the booster circuit is electrically connected with a sixth level signal end, and an output end of the booster circuit is a second signal output end;
the boost circuit comprises a fourth switch and a second capacitor;
a grid electrode of the fourth switch is electrically connected with the fourth level signal end, a first electrode of the fourth switch is electrically connected with the second signal line, and a second electrode of the fourth switch is electrically connected with the sixth level signal end;
the first pole plate of the second capacitor is electrically connected with the first pole of the fourth switch, and the second pole of the second capacitor is electrically connected with the fifth level signal end.
2. The display panel according to claim 1,
the first decoding circuit comprises N decoding units, and each decoding unit comprises M first sub-signal input ends, a second sub-signal input end and a signal output end;
in the same decoding unit, the first sub-signal input ends correspond to the first signal lines one to one, and the first sub-signal input ends are electrically connected with the first signal lines corresponding to the first sub-signal input ends;
the second sub-signal input end of each decoding unit is electrically connected with the second signal line;
and each first grid driving circuit is correspondingly connected to the signal output end of one decoding unit.
3. The display panel according to claim 2,
the decoding unit comprises a NOR gate and M inverters, wherein the NOR gate comprises M first gating modules and one second gating module;
the first end of the second gating module is electrically connected with a fourth level signal end, and the second end of the second gating module is electrically connected with the signal output end of the decoding unit;
the first gating modules correspond to the first signal lines one to one, the control ends of the first gating modules are electrically connected with the first signal lines corresponding to the control ends of the first gating modules, the first ends of the first gating modules are electrically connected with the second signal lines, and the second ends of the first gating modules are electrically connected with the signal output ends of the decoding units;
the control end of the first gating module is electrically connected with the first signal line corresponding to the first gating module through one inverter or directly electrically connected with the first signal line corresponding to the first gating module.
4. The display panel according to claim 3,
the first gating module comprises a first switch, and the second gating module comprises a second switch;
the grid electrode and the first electrode of the second switch are both electrically connected with the fourth level signal end, and the second electrode of the second switch is electrically connected with the signal output end of the decoding unit;
the first switches correspond to the first signal lines one to one, the grid electrodes of the first switches are electrically connected with the first signal lines corresponding to the grid electrodes, the first poles of the first switches are electrically connected with the second signal lines, and the second poles of the first switches are electrically connected with the signal output ends of the decoding units;
the grid of the first switch is electrically connected with the first signal line corresponding to the first switch through one inverter or directly electrically connected with the first signal line corresponding to the first switch.
5. The display panel according to claim 4,
the second gating module further comprises a third switch and a first capacitor;
the grid electrode and the first electrode of the third switch are electrically connected with the fourth level signal end, and the second electrode of the third switch is electrically connected with the first polar plate of the first capacitor and the grid electrode of the second switch respectively;
and the second polar plate of the first capacitor is electrically connected with the signal output end of the decoding unit.
6. The display panel according to claim 3,
the first gating module comprises a first switch, and the second gating module comprises a first resistor;
the first end of the first resistor is electrically connected with the fourth level signal end, and the second end of the first resistor is electrically connected with the signal output end of the decoding unit;
the first switches correspond to the first signal lines one to one, the grid electrodes of the first switches are electrically connected with the first signal lines corresponding to the grid electrodes, the first poles of the first switches are electrically connected with the second signal lines, and the second poles of the first switches are electrically connected with the signal output ends of the decoding units;
the grid of the first switch is electrically connected with the first signal line corresponding to the first switch through one inverter or directly electrically connected with the first signal line corresponding to the first switch.
7. The display panel according to claim 1,
the booster circuit is integrated in the driving chip, and the second signal output end is positioned on the driving chip.
8. The display panel according to claim 1,
the boost circuit is located outside the driving chip, and the boost circuit and the first decoding circuit are arranged along the second direction and located on one side of the first decoding circuit close to the driving chip.
9. The display panel according to claim 3,
the decoding units are arranged along the second direction and are positioned at one side of the first grid driving circuit electrically connected with the decoding units.
10. The display panel according to claim 3,
each decoding unit shares M inverters;
the NOR gates of the decoding units are arranged along the second direction and are positioned on one side of the first gate drive circuit electrically connected with the NOR gates;
the M inverters are positioned on one side, close to the driving chip, of the NOR gate closest to the driving chip.
11. The display panel according to claim 3,
the non-display area further comprises Q second grid driving circuits arranged along the second direction;
the second grid driving circuit is electrically connected with at least two rows of fingerprint identification units extending along the first direction;
the driving chip also comprises M third signal output ends and a fourth signal output end;
the non-display area further comprises a second decoding circuit and M third signal lines, wherein the second decoding circuit comprises M third signal input ends, a fourth signal input end and N signal output ends; the second decoding circuit is the same as the first decoding circuit;
the third signal output ends correspond to the third signal input ends one by one, and the third signal output ends are electrically connected with the third signal input ends corresponding to the third signal output ends through one third signal wire; the fourth signal output end and the fourth signal input end are electrically connected through a fourth signal line; each second gate driving circuit is correspondingly connected to one signal output end of the second decoding circuit;
the third signal output end is used for outputting the pulse signal, and the fourth signal output end is used for outputting the third level signal.
12. The display panel according to claim 11,
the first gate driving circuit and the second gate driving circuit are respectively located at two sides of the display area along the first direction.
13. The display panel according to claim 12,
the first grid driving circuit and the second grid driving circuit are in one-to-one correspondence, and the first grid driving circuit and the second grid driving circuit corresponding to the first grid driving circuit are electrically connected with the same fingerprint identification unit.
14. A display device characterized by comprising the display panel according to any one of claims 1 to 13.
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| CN114550633A (en) * | 2022-02-28 | 2022-05-27 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114429759A (en) * | 2022-03-01 | 2022-05-03 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN114663928A (en) * | 2022-03-31 | 2022-06-24 | 上海天马微电子有限公司 | Fingerprint detection device and fingerprint detection method |
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