CN113031862B - Storage system for controlling SATA disk based on NVME protocol - Google Patents
Storage system for controlling SATA disk based on NVME protocol Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0689—Disk arrays, e.g. RAID, JBOD
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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Abstract
The invention discloses a storage system for controlling SATA disks based on NVME protocol, which comprises a processor and an FPGA module, wherein the processor is connected with the FPGA module through a PCIE bus, the processor is mounted with a first memory, the FPGA module is mounted with a second memory and a SATA storage array, and the SATA storage array comprises a plurality of SATA disks. The processor sends a read-write instruction to the FPGA module and controls the FPGA module to read and write data to the SATA storage array. The storage system combines the high performance of NVME protocol and the expandability of SATA protocol, solves the problem of insufficient SATA interface supported by the prior processor, realizes continuous high-bandwidth read-write of the storage system, can flexibly modify the number and security level of SATA disks, and has low power consumption, low cost, good stability of high-low temperature working environment and good compatibility.
Description
Technical Field
The invention belongs to the technical field of data storage, and particularly relates to a storage system for controlling a SATA disk based on an NVME protocol.
Background
With the rapid development of flash memory technology, field programmable logic array technology and SoC technology, a storage system in the field of computer embedding is gradually constructed. Wherein a solid-state disk composed of a control unit and a flash memory becomes one of the core components of the storage system. Currently, SATA solid state disks follow the SATA protocol with a theoretical maximum bandwidth of 600MB/s, using the AHCI protocol at the software application layer. When a high-performance storage system is built, a plurality of SATA discs are needed, and a plurality of SATA interfaces are needed. With the proposal and development of the NVMe specification, compared with the AHCI protocol, the NVMe specification fully utilizes the low delay, high performance and parallelism of PCIE channels, and greatly improves the read-write performance of the solid state disk.
At present, a storage system in the prior art adopts the following technical scheme: 1) The storage system based on the embedded processor and the SATA disk only supports a small amount of SATA interfaces, and the SATA interfaces are generally used as the system disk, the embedded processor is limited by the number of the SATA interfaces and the protocol types, the delay is larger, and the speed is low; 2) The storage system based on the embedded processor, the PCIE-to-SATA bridge and the SATA disk is relatively poor in safety and flexibility; 3) Based on the embedded processor, PCIE exchange and NVMe disk storage system, the NVMe disk in the market at present falls fast at higher temperature and is easy to damage at low temperature. The technical scheme is difficult to meet the requirements of high standard, high customization and expandability of the storage system in the field of security and confidentiality.
Disclosure of Invention
The invention aims to solve the problems, and provides a storage system for controlling SATA disks based on NVME protocol, which combines the high performance of NVME protocol and the expandability of SATA protocol, solves the problem that the prior processor supports SATA interface, realizes continuous high-bandwidth read-write of the storage system, can flexibly modify the number of SATA disks, and has low power consumption, low cost, good stability of high-low temperature working environment and good compatibility.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
the invention provides a storage system for controlling SATA disks based on NVME protocol, comprising a processor and an FPGA module, wherein the processor is connected with the FPGA module through a PCIE bus, the processor is mounted with a first memory, the FPGA module is mounted with a second memory and a SATA storage array, and the SATA storage array comprises a plurality of SATA disks, wherein:
the processor is used for sending a read-write instruction to the FPGA module and managing data in the SATA storage array, wherein the read-write instruction is an NVME protocol instruction, and when the read-write instruction is a write instruction, the processor receives first data through a first external interface and issues the write instruction and the first data to the first memory, and the FPGA module receives second data through a second external interface and issues the second data to the second memory; when the data in the SATA storage array is read, the processor issues the read instruction and the data in the SATA storage array to a first memory, and the data in the first memory is externally sent through a first external interface, and the FPGA module issues the data in the SATA storage array to a second memory and externally sends the data in the second memory through a second external interface;
the FPGA module is used for acquiring the read-write instruction in the first memory and analyzing the read-write instruction into an SATA protocol instruction, and controlling data interaction between the SATA storage array and the first memory or the second memory according to the SATA protocol instruction;
the first memory is used for caching first data or data read out from the SATA storage array;
the second memory is used for caching second data or data read out from the SATA storage array;
and the SATA storage array is used for storing the first data and the second data.
Preferably, the processor is an embedded processor.
Preferably, the FPGA module includes a protocol conversion module for implementing conversion from NVME protocol to SATA protocol, and a RAID module for controlling parallel reading and writing of multiple SATA disks, where the protocol conversion module is connected to the RAID module, and the RAID module is connected to each SATA disk.
Preferably, the FPGA module further comprises an encryption and decryption module, the protocol conversion module, the encryption and decryption module and the RAID module are sequentially connected, and the encryption and decryption module is used for encrypting and decrypting data in the SATA storage array.
Compared with the prior art, the invention has the beneficial effects that:
1) The NVME protocol is adopted to control the SATA storage array, so that the read-write speed of the SATA disk is higher than that of a pure SATA protocol storage system, and meanwhile, the high-speed parallel characteristic of the FPGA is utilized to enable the storage system to meet high-performance requirements, such as continuous read-write performance not lower than 6.4GB/s, the storage performance is high, the compatibility is good, the design is simple, and the use is convenient and quick;
2) The SATA system related components can be avoided, the power consumption and the cost are greatly reduced, and simultaneously, the SATA disk is used as a storage body, so that the characteristics of low power consumption and wide working temperature range of the SATA disk are reserved, stable working can be realized in an environment of-55 ℃ to +70 ℃, and the miniaturization of the board card is facilitated;
3) The FPGA module is used for controlling a plurality of SATA disks, RAID model level can be modified at will according to requirements, encryption and decryption characteristics can be carried out, safety is improved, autonomous control is realized, and system flexibility is high;
4) One PCIE interface can be used for controlling a plurality of SATA disks, so that the problem that the prior processor is insufficient in supporting the SATA interface is solved.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a memory system according to the present invention;
fig. 2 is a schematic diagram of the internal structure of the FPGA module according to the present invention.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
It is noted that unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
1-2, a storage system for controlling SATA disks based on NVME protocol includes a processor and an FPGA module, the processor is connected with the FPGA module through PCIE bus, the processor is mounted with a first memory, the FPGA module is mounted with a second memory and a SATA storage array, the SATA storage array includes a plurality of SATA disks, wherein:
the processor is used for sending a read-write instruction to the FPGA module and managing data in the SATA storage array, wherein the read-write instruction is an NVME protocol instruction, and when the read-write instruction is a write instruction, the processor receives first data through a first external interface and issues the write instruction and the first data to the first memory, and the FPGA module receives second data through a second external interface and issues the second data to the second memory; when the data in the SATA storage array is read, the processor issues the read instruction and the data in the SATA storage array to a first memory, and the data in the first memory is externally sent through a first external interface, and the FPGA module issues the data in the SATA storage array to a second memory and externally sends the data in the second memory through a second external interface;
the FPGA module is used for acquiring the read-write instruction in the first memory and analyzing the read-write instruction into an SATA protocol instruction, and controlling data interaction between the SATA storage array and the first memory or the second memory according to the SATA protocol instruction;
the first memory is used for caching first data or data read out from the SATA storage array;
the second memory is used for caching second data or data read out from the SATA storage array;
and the SATA storage array is used for storing the first data and the second data.
The SATA disk is controlled and managed by the FPGA module and is read and written, and under the control of the FPGA module, data interaction between the first memory and the second memory and the SATA storage array can be realized, so that continuous high-bandwidth reading and writing of the storage system can be realized. The processor is provided with a file system, can manage the data in the SATA storage array in a standard file system mode, and is convenient to use. And meanwhile, the processor can acquire the number, the initialization state and the capacity information of the SATA disk.
The storage system uses NVME protocol to control SATA storage array, greatly optimizes software design and data flow, makes the read-write speed of SATA disk higher than that of pure SATA protocol storage system, and simultaneously utilizes the high-speed parallel characteristic of FPGA to make the storage system meet high performance requirement, and continuous read-write performance is not lower than 6.4GB/s, and has high storage performance, good compatibility and convenient quick application. The use of SATA related components can be avoided, and the power consumption and hardware cost are greatly reduced. Meanwhile, the SATA disk is used as a storage body, so that the characteristics of low power consumption and wide working temperature range of the SATA disk are maintained, and the SATA disk can stably work in an environment of-55 ℃ to +70 ℃ and is beneficial to miniaturization of the board card. The method is convenient for realizing one PCIE interface to control a plurality of SATA disks, and solves the problem that the prior processor has insufficient SATA interface support.
In one embodiment, the processor is an embedded processor.
The embedded processor has higher working stability, lower power consumption, strong environmental adaptability and good integration level, and is suitable for the field of security and confidentiality.
In an embodiment, the FPGA module includes a protocol conversion module for implementing conversion from NVME protocol to SATA protocol, and a RAID module for controlling parallel reading and writing to multiple SATA disks, where the protocol conversion module is connected to the RAID module, and the RAID module is connected to each SATA disk.
As shown in FIG. 2, the protocol conversion module can convert the read-write command issued by the processor, i.e. NVME protocol command, into SATA protocol command, so as to control the SATA storage array by using NVME protocol, so that the read-write speed of the SATA disk is higher than that of a pure SATA protocol storage system, and the software design is simpler. The RAID module is in the prior art and is used for controlling parallel reading and writing of a plurality of SATA disks to realize autonomous control, and comprises a plurality of different grades, such as RAID0, RAID1, RAID5, RAID10, RAID50 and the like, different speeds, safety and cost performance can be respectively provided, and proper RAID level can be selected according to actual conditions so as to meet the requirements of users on the availability, performance and capacity of the storage system.
In an embodiment, the FPGA module further includes an encryption/decryption module, and the protocol conversion module, the encryption/decryption module, and the RAID module are sequentially connected, where the encryption/decryption module is configured to encrypt and decrypt data in the SATA storage array.
The FPGA module is provided with an encryption and decryption module, for example, when the processor issues a write instruction, the FPGA module analyzes and reorganizes the NVME protocol instruction into an SATA protocol instruction. The data flow is a FIFO interface in a common FPGA, an encryption and decryption module can be added, the data is encrypted and decrypted through the FPGA module, and then the SATA storage array is read and written, so that the safety is further improved, the system flexibility is further improved, the NVME protocol or the SATA protocol can be prevented from being processed, and the operation efficiency is improved.
The workflow of the storage system is as follows:
process of external data writing to SATA storage array:
1) The FPGA module receives the second data and caches the second data into a second memory, and the data in the second memory is written into the SATA storage array through the FPGA module.
Specifically, the processor calls the driving module of the FPGA module through the character device (such as a keyboard, a mouse, etc.) to inform the FPGA module to start recording, that is, the FPGA module starts to receive the second data from the second external interface (such as a high-speed serial interface) and convey the second data to the second memory for caching, the FPGA module reports an interrupt signal to inform the processor after the caching is completed, the processor writes a file after receiving the interrupt signal, and the write address is the address of the second memory. The processor issues a write instruction to the first memory, the write instruction is an NVME protocol instruction, the FPGA module analyzes the write instruction in the first memory into an SATA protocol instruction after acquiring the write instruction, carries data from the second memory according to source address information in the SATA protocol instruction, stores the carried data in the second memory into a sector of a designated SATA storage array according to target address information in the SATA protocol instruction, returns completion information to the processor after the storage is completed, and ends the operation after the processor checks the completion information.
2) And after the processor receives the first data and caches the first data in the first memory, the FPGA module is informed to write the data in the first memory into the SATA storage array.
Specifically, the processor receives first data (such as network data) through a first external interface, buffers the first data into a first memory, reports an interrupt signal to the processor after buffering is completed, writes a file after receiving the interrupt signal, and writes an address which is the address of the first memory. The processor sends a write instruction to the FPGA module, wherein the write instruction is an NVME protocol instruction. The FPGA module obtains a write instruction in the first memory, analyzes the write instruction into an SATA protocol instruction, conveys data from the first memory according to source address information in the SATA protocol instruction, and stores the conveyed data in the first memory into a sector of a designated SATA storage array according to target address information in the SATA protocol instruction. After the storage is completed, the FPGA module returns the completion information to the processor, and the processor finishes the operation after checking the completion information.
Process of data read to outside in SATA storage array:
1) The processor controls the FPGA module to read the data in the SATA storage array to the second memory, and the FPGA module sends the data in the second memory to a second external interface of the FPGA module.
Specifically, the processor calls the driving module of the FPGA module through the character device (such as a keyboard, a mouse, etc.), and notifies the FPGA module to start the playback request. The processor issues a read instruction to the first memory, the read instruction is an NVME protocol instruction, the FPGA module analyzes the read instruction in the first memory into an SATA protocol instruction, carries data from the SATA storage array according to source address information in the SATA protocol instruction, stores the carried data in the SATA storage array into a second memory according to target address information in the SATA protocol instruction, the data in the second memory is sent out through a second external interface of the FPGA module, and generates an interrupt signal to inform the processor of finishing reading the data.
2) The processor controls the FPGA module to read the data in the SATA storage array to the first memory, and the data in the first memory is sent out through a first external interface of the processor.
Specifically, the processor issues a read command to the first memory, the read command is an NVME protocol command, the FPGA module obtains the read command in the first memory and then analyzes the read command into an SATA protocol command, carries data from the SATA storage array according to source address information in the SATA protocol command, stores the carried data in the SATA storage array into the first memory according to target address information in the SATA protocol command, and sends the data in the first memory to an external device such as an opposite PC through a first external interface (such as a network interface) of the processor, and reports an interrupt signal to notify the processor after writing is completed.
Further, when power is on, the processor loads a driving module of the FPGA module, initializes the FPGA module, and creates an admin queue and an IO queue in the FPGA module according to a read-write instruction of the processor:
the processor initializes the NVME registers of the FPGA module and configures AQA, ASQ, ACQ.
ADMIN queue: updating an FPGA module DB ring in the first memory, and refreshing SQ0TDBL; the FPGA module detects that the SQ0TDBL value changes, and initiates reading of ADMIN_SQ information to the first memory; after receiving the feedback data, the FPGA module analyzes the data content to finish IDENTIFY command, create io sq command and create io cq command, namely, the physical addresses of the cache io sq and io cq; update ADMIN CQ and upload interrupt signal to the processor that this time processing is complete.
IO queues: updating an FPGA module DB ring in the first memory, and refreshing SQ1TDBL; the FPGA module detects that the SQ1TDBL value changes, and initiates reading of IO_SQ information to the first memory; after receiving the feedback data, the FPGA module analyzes the data content and completes DMA reading and DMA writing operation, namely the interactive realization of the first memory data and the SATA data is realized; update IO CQ and upload interrupt signal to inform the processor that this time processing is complete.
DMA reading: extracting a read address SADR, a SATA disk write address DADR and a data length LEN of first memory data from the IO_SQ information; the FPGA module reads the data quantity of the data length LEN from the reading address SADR of the first memory data, and writes the data quantity of 4KB into each SATA disk in a rotating way; the SATA disk automatically writes the received data to the SATA disk write address DADR, thereby completing the DMA read operation.
DMA write: extracting a write address DADR, a SATA disk read address SADR and a data length LEN of first memory data from the IO_SQ information; the FPGA module sends the data length LEN to each SATA disk; the SATA disk automatically reads the data quantity of the data length LEN from the SATA disk read address SADR, sequentially synthesizes the received data in a 4KB round-robin mode, and then writes the synthesized data into the write address DADR position of the first memory data, so that DMA write operation is completed.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above embodiments are presented only to describe more specific and detailed embodiments of the present application and should not therefore be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (4)
1. A storage system for controlling SATA disks based on NVME protocols, characterized by: the storage system based on NVME protocol control SATA disk comprises a processor and an FPGA module, wherein the processor is connected with the FPGA module through a PCIE bus, the processor is loaded with a first memory, the FPGA module is loaded with a second memory and a SATA storage array, the SATA storage array comprises a plurality of SATA disks, wherein:
the processor is configured to send a read-write instruction to the FPGA module and manage data in the SATA storage array, where the read-write instruction is an NVME protocol instruction, and when the read-write instruction is a write instruction, the processor receives first data through a first external interface and issues the write instruction and the first data to the first memory, and the FPGA module receives second data through a second external interface and issues the second data to the second memory; when the data in the SATA storage array is read, the processor issues the read instruction and the data in the SATA storage array to the first memory, and externally transmits the data in the first memory through the first external interface, and the FPGA module issues the data in the SATA storage array to the second memory, and externally transmits the data in the second memory through the second external interface;
the FPGA module is used for acquiring the read-write instruction in the first memory and analyzing the read-write instruction into an SATA protocol instruction, and controlling data interaction between the SATA storage array and the first memory or the second memory according to the SATA protocol instruction;
the first memory is used for caching the first data or the data read out from the SATA storage array;
the second memory is configured to cache the second data or data read out from the SATA storage array;
the SATA storage array is used for storing the first data and the second data.
2. The storage system for controlling SATA disks based on NVME protocol as recited in claim 1 wherein: the processor is an embedded processor.
3. The storage system for controlling SATA disks based on NVME protocol as recited in claim 1 wherein: the FPGA module comprises a protocol conversion module for converting NVME protocol into SATA protocol and a RAID module for controlling parallel reading and writing of each SATA disk, wherein the protocol conversion module is connected with the RAID module, and the RAID module is connected with each SATA disk.
4. The storage system for controlling SATA disks based on NVME protocol as recited in claim 3 wherein: the FPGA module further comprises an encryption and decryption module, the protocol conversion module, the encryption and decryption module and the RAID module are sequentially connected, and the encryption and decryption module is used for conducting encryption and decryption processing on data in the SATA storage array.
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| NVMe高速存储的FPGA实现;崔丹丹;宫永生;;微电子学与计算机;20190605(第06期);全文 * |
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