CN113013169A - Method for forming NOR FLASH - Google Patents
Method for forming NOR FLASH Download PDFInfo
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- CN113013169A CN113013169A CN202110209862.5A CN202110209862A CN113013169A CN 113013169 A CN113013169 A CN 113013169A CN 202110209862 A CN202110209862 A CN 202110209862A CN 113013169 A CN113013169 A CN 113013169A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a forming method of NOR FLASH, comprising the following steps: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent; sequentially forming a flash memory oxide layer, a floating gate layer and a nitride layer on the surface of the substrate, wherein the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area; sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein a filler of the shallow trench isolation structure is an oxide; removing the nitride layer of the flash memory area, performing ion implantation and annealing on the floating gate layers of the flash memory area and the logic area, and enabling part of ions to enter the floating gate layer through the side wall of the shallow trench isolation structure; forming an interlayer dielectric layer on the floating gate layer of the flash memory area; and removing the interlayer dielectric layer and the floating gate layer in the logic area to form a gate structure of the flash memory area. The invention can reduce the area of the flash memory unit and can ensure uniform erasing at the same time.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of NOR FLASH.
Background
Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, electrical programmability, and easy erasure. At present, the flash memory unit is mainly carried out at a 65 nanometer technology node, and with the requirement on a high-capacity flash memory, the number of chips on each silicon chip is reduced by utilizing the node in the prior art. Meanwhile, with the increasing maturity of new technology nodes, flash memory cells are also urged to be produced by high-node technology. This means that the size of the flash memory cell needs to be reduced, however, reducing the width of the active area and the length of the channel of the flash memory cell affects the performance of the flash memory cell.
The current lateral scaling from 65nm NOR FLASH to 55nm NOR FLASH, and thus to 50nm NOR FLASH, is primarily achieved by scaling down the active area of the FLASH memory cell, and by scaling down the distance between the active area and the active area. The conventional floating gate is mainly performed by Fowerll-Norhei (Fowler-Nordheim) tunneling in a channel mode, and depends on the effective areas of the floating gate and the flash memory cell. Due to the reduced area, the number of silicon dioxide silicon energy valleys generated by phosphorus doping contained in the silicon dioxide interface between the floating gate and the flash memory oxide layer in each flash memory unit is reduced, so that the erasing uniformity is reduced.
Disclosure of Invention
The invention provides a method for forming NOR FLASH, which can reduce the area of FLASH memory unit and keep the uniform erasing.
In order to achieve the above object, the present invention provides a method for forming a NOR FLASH, comprising:
providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent;
sequentially forming a flash memory oxide layer, a floating gate layer and a nitride layer on the surface of the substrate, wherein the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area;
sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein a filler of the shallow trench isolation structure is an oxide;
removing the nitride layer of the flash memory area, performing ion implantation and annealing on the floating gate layers of the flash memory area and the logic area, and enabling part of ions to enter the floating gate layer through the side wall of the shallow trench isolation structure;
forming an interlayer dielectric layer on the floating gate layer of the flash memory area;
and removing the interlayer dielectric layer and the floating gate layer in the logic area to form a gate structure of the flash memory area.
Optionally, in the method for forming the NOR FLASH, before forming the FLASH memory oxide layer, the floating gate layer, and the nitride layer on the surface of the substrate in sequence, the method further includes: and forming a HVNW region and a CELL VT region in the substrate, and forming a HVPW region separating the HVNW region and the CELL VT region.
Optionally, in the forming method of the NOR FLASH, a surface of the shallow trench isolation structure is lower than a surface of the nitride layer.
Optionally, in the method for forming the NOR FLASH, after removing the remaining nitride layer, the method further includes: the surface of the floating gate layer is flush with the surface of the shallow trench isolation structure.
Optionally, in the method for forming the NOR FLASH, the FLASH memory oxide layer is made of silicon dioxide.
Optionally, in the method for forming the NOR FLASH, the oxide is made of silicon dioxide.
Optionally, in the forming method of the NOR FLASH, the material of the nitride layer is silicon nitride.
Optionally, in the method for forming NOR FLASH, the doped ions include phosphorus ions.
Optionally, in the forming method of the NOR FLASH, the interlayer dielectric layer includes an ONO layer.
Optionally, in the method for forming the NOR FLASH, after removing the nitride layer above the FLASH memory region and performing ion implantation and annealing on the floating gate layer, the method further includes: and etching the shallow trench isolation structure of the flash memory area to enable the surface of the shallow trench isolation structure to be lower than the surface of the floating gate layer.
The forming method of NOR FLASH provided by the invention comprises the following steps: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent; sequentially forming a flash memory oxide layer, a floating gate layer and a nitride layer on the surface of the substrate, wherein the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area; sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein a filler of the shallow trench isolation structure is an oxide; removing the nitride layer of the flash memory area, and performing ion implantation and annealing on the floating gate layers of the flash memory area and the logic area, wherein ions enter the floating gate layers through the side wall of the shallow trench isolation structure; forming an interlayer dielectric layer on the floating gate layer of the flash memory area; and removing the interlayer dielectric layer and the floating gate layer in the logic area to form a gate structure of the flash memory area. And part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure, and the oxide carried by the part of ions prevents the polysilicon at the bottom of the floating gate layer from being rapidly crystallized, so that the doping of the polysilicon in contact with silicon dioxide is reduced, the corresponding grain size is also reduced, the occupied size of grains is reduced, the more the grain boundary is, the more uniform the erasing is.
Drawings
FIG. 1 is a flow chart of a method of forming NOR FLASH in accordance with an embodiment of the present invention;
fig. 2 to 6 are schematic structural views of a NOR FLASH forming method according to an embodiment of the present invention;
in the figure: 110-substrate, 110A-flash memory area, 110B-logic area, 111-HVNW area, 112-HVPW area, 113-CELL VT area, 120-flash memory oxide layer, 130-floating gate layer, 140-nitride layer, 150-shallow trench isolation structure and 160-interlayer dielectric layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The inventor researches and discovers that one method for forming NOR FLASH in the prior art is to respectively form a FLASH memory oxide layer and a floating gate layer on a substrate, then carry out annealing, then carry out formation of a shallow trench isolation structure, and etch the floating gate layer to form a gate structure after the formation of the shallow trench isolation structure. Through further research by the inventor, the crystal grains of the polycrystalline silicon in the floating gate layer are annealed after being implanted with the doped phosphorus ions, so that the size of the crystal grains is increased, and then the crystal grains are further increased in the formation of a later gate structure, so that the number of silicon energy valleys which are few per se is further reduced. Moreover, as the capacity of the flash memory cell increases, the influence of the reduction of the area of the flash memory cell becomes more serious, resulting in more and more uneven erasing.
Referring to fig. 1, the present invention provides a method for forming a NOR FLASH, including:
s11: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent;
s12: sequentially forming a flash memory oxide layer, a floating gate layer and a nitride layer on the surface of the substrate, wherein the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area;
s13: sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein a filler of the shallow trench isolation structure is an oxide;
s14: removing the nitride layer of the flash memory area, performing ion implantation and annealing on the floating gate layers of the flash memory area and the logic area, and enabling part of ions to enter the floating gate layer through the side wall of the shallow trench isolation structure;
s15: forming an interlayer dielectric layer on the floating gate layer of the flash memory area;
s16: and removing the interlayer dielectric layer and the floating gate layer in the logic area to form a gate structure of the flash memory area.
Specifically, referring to fig. 2, first, a substrate 110 is provided, and the substrate 100 includes a flash memory region 110A and a logic region 110B. The substrate 110 may be a silicon substrate or a germanium substrate, and in the embodiment of the present invention, a silicon substrate is used, for example, a wafer is used. An HVNW region 111, an HVPW region 112, and a CELL VT region 113 are formed within the substrate 110, respectively, with the HVPW region 112 separating the HVNW region 111 and the CELL VT region 113. The HVNW region 111 is the N-well of the high voltage 5V device, the HVPW region 112 is the P-well of the high voltage 5V device, and the CELL VT region 113 is the well of the trim storage region. The HVNW region 111, the HVPW region 112 and the CELL VT region 113 are formed by conventional methods, and are not described herein.
Next, referring to fig. 3, a flash memory oxide layer 120 is formed on the surface of the substrate 110, the flash memory oxide layer 120 may be an oxide, specifically, silicon dioxide, a floating gate layer 130 is formed on the flash memory oxide layer 120, the floating gate layer 130 may be polysilicon, and a nitride layer 140 is formed on the floating gate layer 130, the nitride layer 140 may be silicon nitride. The flash oxide layer 120, the floating gate layer 130, and the nitride layer 140 are formed on the flash area 110A and the logic area 110B.
Next, referring to fig. 4, the nitride layer 140, the floating gate layer 130 and the flash memory oxide layer 120 in the flash memory region 110A and the logic region 110B are etched to form shallow trenches, and an oxide such as silicon dioxide is filled into the shallow trenches to form the shallow trench isolation structure 150, that is, the shallow trench isolation structure 150 is formed by filling the oxide such as silicon dioxide, and the surface of the shallow trench isolation structure 150 is lower than the surface of the remaining nitride layer 140.
Next, referring to fig. 5, the remaining nitride layer 140 above the flash memory region 120A is removed, ion implantation is performed on the floating gate layer 130 in the flash memory region 110A and the logic region 110B to dope the floating gate layer 130, and then annealing is performed, wherein the implanted ions may be phosphorus ions, the energy of the implanted phosphorus ions is 10KeV to 25KeV, and the concentration of the implanted phosphorus ions is 2E15 atom/cm2 to 7E15atom/cm 2. When ions are injected into the floating gate layer 130, part of the ions are injected into the shallow trench isolation structure 150, and when annealing is performed, part of phosphorus ions are doped in silicon dioxide, and during annealing, the part of the phosphorus ions carry oxide (silicon dioxide) to enter the junction between the side wall of the shallow trench isolation structure 150 and the floating gate layer 130 and the junction between the bottom wall of the shallow trench isolation structure 150 and the floating gate layer 130, the oxide (silicon dioxide) is used for limiting the growth of crystal grains of the floating gate layer 130 at the junction, when phosphorus ions of the floating gate layer 130 in other regions outside the junction enter the bottom of the floating gate layer 130, the bottom crystal grains are competed by the crystal grains at the junction, the crystal grains are slower than those of the original crystal grains to be grown, the size of the crystal grains is also reduced, the occupied size of the crystal grains is reduced, the number of the crystal grains. That is, the silicon dioxide enters the floating gate layer 130 through the sidewall of the shallow trench isolation structure 150, which prevents the polysilicon at the bottom of the floating gate layer 130 from being rapidly crystallized, so that the doping of the polysilicon in contact with the silicon dioxide is reduced, the corresponding grain size is also reduced, the occupied size of the grain is reduced, and the more the grain boundary is, the more uniform the erasure is. One method of forming NOR FLASH in the prior art is to form a FLASH memory oxide layer and a floating gate layer on a substrate, respectively, then anneal, then form a shallow trench isolation structure, and etch the floating gate layer after the formation of the shallow trench isolation structure to form a gate structure. Through further research by the inventor, the crystal grains of the polycrystalline silicon in the floating gate layer are annealed after being implanted with the doped phosphorus ions, so that the size of the crystal grains is increased, and then the crystal grains are further increased in the formation of a later gate structure, so that the number of silicon energy valleys which are few per se is further reduced. Moreover, as the capacity of the flash memory cell increases, the influence of the reduction of the area of the flash memory cell becomes more serious, resulting in more and more uneven erasing. The embodiment of the invention changes the sequence of the forming method of the ion implantation step and the annealing step in the NOR FLASH, and can overcome the problem.
Next, referring to fig. 6, the shallow trench isolation structure 150 in the flash memory region 110A is etched to make the surface lower than the surface of the floating gate layer 130, an interlayer dielectric layer 160 is formed on the remaining floating gate layer 130 in the flash memory region 110A, and the interlayer dielectric layer 160 is located in the ONO layer;
next, the interlayer dielectric layer 160 and the floating gate layer 130 in the logic region 110B are removed to form a gate structure of the flash memory region 110A.
In summary, the method for forming the NOR FLASH according to the embodiment of the present invention includes: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent; sequentially forming a flash memory oxide layer, a floating gate layer and a nitride layer on the surface of the substrate, wherein the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area; sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein a filler of the shallow trench isolation structure is an oxide; removing the nitride layer of the flash memory area, and performing ion implantation and annealing on the floating gate layers of the flash memory area and the logic area, wherein ions enter the floating gate layers through the side wall of the shallow trench isolation structure; forming an interlayer dielectric layer on the floating gate layer of the flash memory area; and removing the interlayer dielectric layer and the floating gate layer in the logic area to form a gate structure of the flash memory area. And part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure, and the oxide carried by the part of ions prevents the polysilicon at the bottom of the floating gate layer from being rapidly crystallized, so that the doping of the polysilicon in contact with silicon dioxide is reduced, the corresponding grain size is also reduced, the occupied size of grains is reduced, the more the grain boundary is, the more uniform the erasing is.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for forming NOR FLASH is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent;
sequentially forming a flash memory oxide layer, a floating gate layer and a nitride layer on the surface of the substrate, wherein the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area;
sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein a filler of the shallow trench isolation structure is an oxide;
removing the nitride layer of the flash memory area, performing ion implantation and annealing on the floating gate layers of the flash memory area and the logic area, and enabling part of ions to enter the floating gate layer through the side wall of the shallow trench isolation structure;
forming an interlayer dielectric layer on the floating gate layer of the flash memory area;
and removing the interlayer dielectric layer and the floating gate layer in the logic area to form a gate structure of the flash memory area.
2. The method of forming NOR FLASH of claim 1, wherein before forming the FLASH memory oxide layer, the floating gate layer, and the nitride layer on the surface of the substrate in sequence, further comprising: and forming a HVNW region and a CELL VT region in the substrate, and forming a HVPW region separating the HVNW region and the CELL VT region.
3. The method of forming NOR FLASH of claim 1 wherein the shallow trench isolation structure has a surface that is lower than a surface of the nitride layer.
4. The method of forming NOR FLASH of claim 1, further comprising, after removing the remaining nitride layer: the surface of the floating gate layer is flush with the surface of the shallow trench isolation structure.
5. The method of claim 1, wherein the FLASH memory oxide layer is silicon dioxide.
6. The method of claim 1, wherein the oxide is silicon dioxide.
7. The method of claim 1, wherein the nitride layer is made of silicon nitride.
8. The method of claim 1, wherein the doped ions comprise phosphorous ions.
9. The method of claim 1, wherein the interlevel dielectric layer comprises an ONO layer.
10. The method of forming NOR FLASH of claim 1, wherein after removing the nitride layer over the FLASH memory region and performing ion implantation and annealing on the floating gate layer, further comprising: and etching the shallow trench isolation structure of the flash memory area to enable the surface of the shallow trench isolation structure to be lower than the surface of the floating gate layer.
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| US6207504B1 (en) * | 1998-07-29 | 2001-03-27 | United Semiconductor Corp. | Method of fabricating flash erasable programmable read only memory |
| US20070293029A1 (en) * | 2006-06-14 | 2007-12-20 | Fujitsu Limited | Method for fabricating semiconductor device |
| CN102263110A (en) * | 2011-08-12 | 2011-11-30 | 上海先进半导体制造股份有限公司 | Electrically erasable programmable read-only memory (EEPROM) core structure formed by process embedded into monolithic integration process of manufacturing bipolar transistor, complementary metal oxide semiconductor (CMOS) device and double-diffusion metal oxide semiconductor (DMOS) device on identical chip (BCD) and forming method |
| CN108039350A (en) * | 2017-11-30 | 2018-05-15 | 上海华力微电子有限公司 | Improve the technology integrating method of flash memory mesohigh device grids oxide layer reliability |
| CN108091658A (en) * | 2017-11-16 | 2018-05-29 | 上海华力微电子有限公司 | The technique integrated morphology and method of flash memory |
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- 2021-02-24 CN CN202110209862.5A patent/CN113013169B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207504B1 (en) * | 1998-07-29 | 2001-03-27 | United Semiconductor Corp. | Method of fabricating flash erasable programmable read only memory |
| US20070293029A1 (en) * | 2006-06-14 | 2007-12-20 | Fujitsu Limited | Method for fabricating semiconductor device |
| CN102263110A (en) * | 2011-08-12 | 2011-11-30 | 上海先进半导体制造股份有限公司 | Electrically erasable programmable read-only memory (EEPROM) core structure formed by process embedded into monolithic integration process of manufacturing bipolar transistor, complementary metal oxide semiconductor (CMOS) device and double-diffusion metal oxide semiconductor (DMOS) device on identical chip (BCD) and forming method |
| CN108091658A (en) * | 2017-11-16 | 2018-05-29 | 上海华力微电子有限公司 | The technique integrated morphology and method of flash memory |
| CN108039350A (en) * | 2017-11-30 | 2018-05-15 | 上海华力微电子有限公司 | Improve the technology integrating method of flash memory mesohigh device grids oxide layer reliability |
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