CN113013064A - Compound semiconductor wafer manufacturing process based on silicon-based carrier plate - Google Patents
Compound semiconductor wafer manufacturing process based on silicon-based carrier plate Download PDFInfo
- Publication number
- CN113013064A CN113013064A CN202110212840.4A CN202110212840A CN113013064A CN 113013064 A CN113013064 A CN 113013064A CN 202110212840 A CN202110212840 A CN 202110212840A CN 113013064 A CN113013064 A CN 113013064A
- Authority
- CN
- China
- Prior art keywords
- compound semiconductor
- silicon
- carrier plate
- semiconductor substrate
- based carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 150000001875 compounds Chemical class 0.000 title claims abstract description 85
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 50
- 239000010703 silicon Substances 0.000 title claims abstract description 50
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 65
- 239000011521 glass Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000012790 adhesive layer Substances 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 8
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 abstract description 31
- 230000008901 benefit Effects 0.000 abstract description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000001883 metal evaporation Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Abstract
The invention belongs to the field of semiconductor manufacturing, and discloses a compound semiconductor wafer manufacturing process based on a silicon-based carrier plate, which comprises the following steps: s1, permanently bonding the back surfaces of the compound semiconductor substrates on the silicon-based carrier plate; s2, completing the wafer process of the front surface of the compound semiconductor substrate; s3, temporarily bonding the glass carrier plate after the front surface of the compound semiconductor substrate is flattened; s4, turning over the glass carrier plate, removing the silicon-based carrier plate through grinding and etching, and finishing the thinning of the back of the compound semiconductor substrate; s5, completing the back wafer process of the compound semiconductor substrate; s6, removing the glass carrier plate by debonding, and removing the adhesive layer to complete the compound semiconductor element. The invention permanently bonds the small-size compound semiconductor substrate on the silicon-based carrier plate, realizes the mass production of compound semiconductor elements by using the existing production line of the major-size silicon wafer, can manufacture a plurality of compound semiconductor wafers at one time, and improves the production line benefit of the compound semiconductor wafers.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a compound semiconductor wafer manufacturing process based on a silicon-based carrier plate.
Background
Semiconductor materials can be classified into elementary semiconductors such as semiconductors formed of silicon (Si), germanium (Ge), and the like, and compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like. While semiconductors have been mainly changed in the third generation in the past, gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) semiconductors, which are representative of the second and third generation semiconductors, are much more excellent in high-frequency performance and high-temperature performance than the first generation semiconductors, and are more expensive to manufacture, and are therefore new and expensive in semiconductors.
The compound semiconductor can show excellent performance on ultrahigh voltage (8000V) IGBT and ultrahigh frequency (300 KHz) MOSFET elements, but the current mass production technology of the crystal growth material can only limit the substrate size to 6 inches and below 6 inches, and is incompatible with the 8 inch/12 inch process of the existing silicon chip. Because most of the processing processes are similar, if the sizes are consistent, a few processing devices special for the SiC or GaN process can be embedded into the production line of the 8-inch silicon wafer to implement mass production, and the benefit is much higher than that of the newly-established production line of the SiC or GaN with small sizes. Therefore, there is a need for a manufacturing process suitable for small compound semiconductor wafers to achieve mass production thereof.
Disclosure of Invention
In order to solve the above-mentioned drawbacks of the prior art, the present invention provides a process for manufacturing a compound semiconductor wafer based on a silicon-based carrier, wherein a small-sized compound semiconductor substrate is permanently bonded to the silicon-based carrier, after the previous process is completed, the front surface of the compound semiconductor substrate is temporarily bonded to a glass carrier, the silicon-based carrier is completely removed by grinding, the back surface of the compound semiconductor substrate is thinned, a stress damage layer is removed by wet etching, back metal evaporation and sputtering are performed, the compound semiconductor substrate and the glass carrier are finally debonded and bonded, and an adhesive is cleaned, thereby completing the manufacture of a compound semiconductor substrate device.
The purpose of the invention can be realized by the following technical scheme:
a compound semiconductor wafer manufacturing process based on a silicon-based carrier plate comprises the following steps:
s1, permanently bonding the back surfaces of the compound semiconductor substrates on the silicon-based carrier plate;
s2, completing the wafer process of the front surface of the compound semiconductor substrate;
s3, temporarily bonding the glass carrier plate after the front surface of the compound semiconductor substrate is flattened;
s4, turning over the glass carrier plate, removing the silicon-based carrier plate through grinding and etching, and finishing the thinning of the back of the compound semiconductor substrate;
s5, completing the back wafer process of the compound semiconductor substrate;
and S6, debonding by laser, UV or heat treatment, removing the glass carrier, and cleaning to remove the adhesive layer to obtain the compound semiconductor element.
Further preferably, the compound semiconductor substrate includes a gallium arsenide substrate, a gallium nitride substrate and a silicon carbide substrate, and when the compound semiconductor substrate is the silicon carbide substrate, the high temperature process is completed before the silicon-based carrier is permanently bonded in step S1.
Further preferably, the thickness of the compound semiconductor substrate and the silicon-based carrier after the compound semiconductor substrate and the silicon-based carrier are permanently bonded in step S1 is less than 1500 μm, and the diameter of the silicon-based carrier is larger than that of the compound semiconductor substrate.
Further preferably, the front wafer process in step S2 includes a photolithography process, an ILD process, an ion implantation process, a metal process and an etching process.
Further preferably, the back side wafer process in step S5 includes a photolithography process, an ion implantation process, and a metal process.
The invention has the beneficial effects that:
the process of the invention is characterized in that a small-size compound semiconductor substrate is permanently bonded on a silicon-based carrier plate, after the front-stage process is completed, the front surface of the compound semiconductor substrate is temporarily bonded on a glass carrier plate, the silicon-based carrier plate is completely removed by a grinding technology, the back surface of the compound semiconductor substrate is thinned, a stress damage layer is removed by a wet etching technology, back surface metal evaporation and sputtering are carried out, the compound semiconductor substrate and the glass carrier plate are bonded, and after an adhesive is cleaned, the manufacture of a plurality of small-size compound semiconductor substrates is completed. The process realizes the mass production of the compound semiconductor substrate element by utilizing the production line of the existing main size silicon wafer, can manufacture a plurality of compound semiconductor wafers at one time, and improves the production line benefit of the compound semiconductor wafers.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic view of a bonding structure of a silicon-based carrier and a small-sized compound semiconductor substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken at the location A-A of FIG. 1 in accordance with the present invention;
FIG. 3 is a schematic view of the molding in step S2 according to example 1 of the present invention;
FIG. 4 is a schematic view of the molding in step S3 according to example 1 of the present invention;
fig. 5 is a schematic diagram of the forming in step S4 in example 1 of the present invention.
In the figure:
1-8 inches of silicon-based carrier plate, 2-4 inches of compound semiconductor substrate, 3-3 inches of compound semiconductor substrate, 4-12 inches of silicon-based carrier plate, 5-6 inches of compound semiconductor substrate and 6-glass carrier plate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "opening," "upper," "lower," "thickness," "top," "middle," "length," "inner," "peripheral," and the like are used in an orientation or positional relationship that is merely for convenience in describing and simplifying the description, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the present invention.
Example 1
A compound semiconductor wafer manufacturing process based on a silicon-based carrier plate comprises the following steps:
s1, permanently bonding the silicon-based carrier plate on the back of the compound semiconductor substrate;
s2, completing the wafer process of the front surface of the compound semiconductor substrate;
s3, temporarily bonding the glass carrier plate after the front surface of the compound semiconductor substrate is flattened;
s4, turning over the glass carrier plate, removing the silicon-based carrier plate through grinding and etching, and finishing the thinning of the back of the compound semiconductor substrate;
s5, completing the back wafer process of the compound semiconductor substrate;
and S6, debonding by laser, UV or heat treatment, removing the glass carrier, and cleaning to remove the adhesive layer to obtain the compound semiconductor element.
The compound semiconductor substrate is a gallium nitride substrate.
The total thickness of the bonded wafer and the silicon-based carrier in the step S1 is 700 μm, wherein the thickness of the silicon-based carrier is 450 μm, the thickness of the compound semiconductor substrate is 250 μm, the thickness of the silicon-based carrier in the step S1 is 8-inch carrier, the number of the compound semiconductor substrates is four, and the four compound semiconductor substrates include two 3-inch substrates and two 4-inch substrates, and the four compound semiconductor substrates are horizontally arranged and bonded on the surface of the silicon-based carrier, as shown in fig. 1 (a).
The front wafer process of step S2 includes a photolithography process, an ILD process, an ion implantation process, a metal process, and an etching process.
The back wafer process of step S5 includes a photolithography process, an ion implantation process, and a metal process.
Example 2
A compound semiconductor wafer manufacturing process based on a silicon-based carrier plate comprises the following steps:
s1, permanently bonding the silicon-based carrier plate on the back of the compound semiconductor substrate;
s2, completing the wafer process of the front surface of the compound semiconductor substrate;
s3, temporarily bonding the glass carrier plate after the front surface of the compound semiconductor substrate is flattened;
s4, turning over the glass carrier plate, removing the silicon-based carrier plate through grinding and etching, and finishing the thinning of the back of the compound semiconductor substrate;
s5, completing the back wafer process of the compound semiconductor substrate;
and S6, debonding by laser, UV or heat treatment, removing the glass carrier, and cleaning to remove the adhesive layer to obtain the compound semiconductor element.
The compound semiconductor substrate is a silicon carbide substrate, and in step S1, a high temperature process is performed before bonding the silicon-based carrier.
The total thickness of the bonded wafer and the silicon-based carrier in the step S1 is 800 μm, wherein the thickness of the silicon-based carrier is 500 μm, the thickness of the compound semiconductor substrate is 300 μm, the silicon-based carrier in the step S1 is a 12-inch carrier, the number of the compound semiconductor substrates is four, and the four compound semiconductor substrates include two 4-inch substrates and two 6-inch substrates, and the four compound semiconductor substrates are horizontally arranged and bonded on the surface of the silicon-based carrier, as shown in fig. 1 (b).
The front wafer process of step S2 includes a photolithography process, an ILD process, an ion implantation process, a metal process, and an etching process.
The back wafer process of step S5 includes a photolithography process, an ion implantation process, and a metal process.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (5)
1. A compound semiconductor wafer manufacturing process based on a silicon-based carrier plate is characterized by comprising the following steps:
s1, permanently bonding the back surfaces of the compound semiconductor substrates on the silicon-based carrier plate;
s2, completing the wafer process of the front surface of the compound semiconductor substrate;
s3, temporarily bonding the glass carrier plate after the front surface of the compound semiconductor substrate is flattened;
s4, turning over the glass carrier plate, removing the silicon-based carrier plate through grinding and etching, and finishing the thinning of the back of the compound semiconductor substrate;
s5, completing the back wafer process of the compound semiconductor substrate;
and S6, debonding by laser, UV or heat treatment, removing the glass carrier, and cleaning to remove the adhesive layer to obtain the compound semiconductor element.
2. The process of claim 1, wherein the compound semiconductor substrate comprises a GaAs substrate, a GaN substrate and a SiC substrate, and the compound semiconductor substrate is made by performing a high temperature process prior to the step of permanently bonding the Si-based carrier in step S1.
3. The process for manufacturing a compound semiconductor wafer based on a silicon-based carrier plate as claimed in claim 1, wherein the thickness of the compound semiconductor substrate and the silicon-based carrier plate after permanent bonding in step S1 is less than 1500 μm, and the diameter of the silicon-based carrier plate is larger than that of the compound semiconductor substrate.
4. The silicon-based carrier-based compound semiconductor wafer fabrication process of claim 1, wherein the front side wafer process of step S2 comprises a photolithography process, an ILD process, an ion implantation process, a metal process and an etching process.
5. The silicon-based carrier-based compound semiconductor wafer fabrication process of claim 1, wherein the backside wafer process of step S5 comprises a photolithography process, an ion implantation process and a metal process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110212840.4A CN113013064A (en) | 2021-02-23 | 2021-02-23 | Compound semiconductor wafer manufacturing process based on silicon-based carrier plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110212840.4A CN113013064A (en) | 2021-02-23 | 2021-02-23 | Compound semiconductor wafer manufacturing process based on silicon-based carrier plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113013064A true CN113013064A (en) | 2021-06-22 |
Family
ID=76386027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110212840.4A Pending CN113013064A (en) | 2021-02-23 | 2021-02-23 | Compound semiconductor wafer manufacturing process based on silicon-based carrier plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113013064A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109592A (en) * | 1991-06-20 | 1993-04-30 | Fujitsu Ltd | Wafer for compound semiconductor device and manufacture thereof |
| JPH1187200A (en) * | 1997-09-05 | 1999-03-30 | Toshiba Corp | Semiconductor substrate and manufacture of semiconductor device |
| JP2000277405A (en) * | 1999-03-29 | 2000-10-06 | Meidensha Corp | Method for producing semiconductor device |
| US20020123204A1 (en) * | 2001-03-01 | 2002-09-05 | Torvik John Tarje | Method of making a hybrid substrate having a thin silicon carbide membrane layer |
| US20040007763A1 (en) * | 2002-03-14 | 2004-01-15 | Commonwealth Scientific And Industrial Research Organization Campbell, Australia | Method and resulting structure for manufacturing semiconductor substrates |
| JP2007180273A (en) * | 2005-12-28 | 2007-07-12 | Toyota Central Res & Dev Lab Inc | Method of manufacturing semiconductor device |
| US20100124798A1 (en) * | 2008-11-18 | 2010-05-20 | Samsung Electronics Co., Ltd. | Method of manufacturing light emitting device |
| JP2011071196A (en) * | 2009-09-24 | 2011-04-07 | Sumitomo Electric Ind Ltd | Method of manufacturing semiconductor substrate |
| CN105938794A (en) * | 2015-03-06 | 2016-09-14 | 英飞凌科技奥地利有限公司 | Method of manufacturing semiconductor devices, composite wafer and semiconductor device |
| WO2020181815A1 (en) * | 2019-03-13 | 2020-09-17 | 电子科技大学 | Preparation method for spliced small-sized single crystal thin film, single crystal thin film and resonator |
-
2021
- 2021-02-23 CN CN202110212840.4A patent/CN113013064A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109592A (en) * | 1991-06-20 | 1993-04-30 | Fujitsu Ltd | Wafer for compound semiconductor device and manufacture thereof |
| JPH1187200A (en) * | 1997-09-05 | 1999-03-30 | Toshiba Corp | Semiconductor substrate and manufacture of semiconductor device |
| JP2000277405A (en) * | 1999-03-29 | 2000-10-06 | Meidensha Corp | Method for producing semiconductor device |
| US20020123204A1 (en) * | 2001-03-01 | 2002-09-05 | Torvik John Tarje | Method of making a hybrid substrate having a thin silicon carbide membrane layer |
| US20040007763A1 (en) * | 2002-03-14 | 2004-01-15 | Commonwealth Scientific And Industrial Research Organization Campbell, Australia | Method and resulting structure for manufacturing semiconductor substrates |
| JP2007180273A (en) * | 2005-12-28 | 2007-07-12 | Toyota Central Res & Dev Lab Inc | Method of manufacturing semiconductor device |
| US20100124798A1 (en) * | 2008-11-18 | 2010-05-20 | Samsung Electronics Co., Ltd. | Method of manufacturing light emitting device |
| JP2011071196A (en) * | 2009-09-24 | 2011-04-07 | Sumitomo Electric Ind Ltd | Method of manufacturing semiconductor substrate |
| CN105938794A (en) * | 2015-03-06 | 2016-09-14 | 英飞凌科技奥地利有限公司 | Method of manufacturing semiconductor devices, composite wafer and semiconductor device |
| WO2020181815A1 (en) * | 2019-03-13 | 2020-09-17 | 电子科技大学 | Preparation method for spliced small-sized single crystal thin film, single crystal thin film and resonator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230253383A1 (en) | Techniques for joining dissimilar materials in microelectronics | |
| TWI809092B (en) | Dbi to si bonding for simplified handle wafer | |
| US7420226B2 (en) | Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates | |
| US20060084197A1 (en) | Wafer-level diamond spreader | |
| JP6319849B2 (en) | Pseudo substrate with improved utilization efficiency of single crystal material | |
| TW201342494A (en) | Composite wafer for fabrication of semiconductor devices | |
| CN104781907B (en) | Group III nitride composite substrate and manufacture method, the group III nitride composite substrate of stacking, Group III nitride semiconductor device and manufacture method thereof | |
| CN107195627A (en) | A kind of gallium nitride transistor and the integrated method of silicon transistor | |
| CN106981423A (en) | Process based on Si substrate epitaxial SiC base GaN HEMT | |
| CN111900200A (en) | Diamond-based gallium nitride composite wafer and bonding preparation method thereof | |
| US7297613B1 (en) | Method of fabricating and integrating high quality decoupling capacitors | |
| CN111540710B (en) | Preparation method of high-heat-conductivity gallium nitride high-power HEMT device | |
| CN113013064A (en) | Compound semiconductor wafer manufacturing process based on silicon-based carrier plate | |
| US20130154049A1 (en) | Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology | |
| CN113903656A (en) | Silicon carbide wafer processing technology | |
| CN113013062A (en) | Permanent bonding method of compound semiconductor substrate and silicon-based carrier plate | |
| CN113013061B (en) | Method for processing compound semiconductor by using organic film | |
| CN113013063A (en) | Front processing method of compound semiconductor wafer based on silicon-based carrier plate | |
| CN108428669B (en) | Three-dimensional heterogeneous integrated system and manufacturing method thereof | |
| CN112368828A (en) | Technique for joining dissimilar materials in microelectronics | |
| CN113903658A (en) | SiC wafer processing technology using secondary bonded silicon-based carrier plate | |
| EP4138116B1 (en) | Method for manufacturing semiconductor element | |
| CN115662933A (en) | Method for fixing compound semiconductor substrate and graphite carrier plate | |
| CN113113294B (en) | Composite substrate, preparation method thereof and preparation method of radio frequency integrated chip | |
| CN113113306A (en) | High-temperature tempering process for compound semiconductor wafer by using high-temperature-resistant tray |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |