CN113012750B - Testing device and method for memory chip - Google Patents

Abstract

The invention provides a testing device and method of a memory chip, and relates to the technical field of mobile phone memory. The test device comprises: the test main board is provided with a Central Processing Unit (CPU), a programmable logic device (FPGA), a SOCKET clamp and at least one memory chip eMMC particle; the eMMC particles are placed in the SOCKET clamp, and the FPGA is connected with one eMMC particle through one passage. According to the scheme, batch nondestructive testing of eMMC particles is realized, testing verification efficiency is improved, DATA and CLK signals between a CPU and the eMMC particles are transmitted and buffered through an FPGA, phase shifting processing is carried out on time sequence, time sequence boundaries of setup time and hold time in an abnormal state are recorded respectively, a digitized time sequence margin window signal of the eMMC particles is obtained, and traditional oscilloscope UT testing is replaced.

Description

Testing device and method for memory chip

Technical Field

The invention relates to the technical field of mobile phone storage, in particular to a device and a method for testing a storage chip.

Background

With the rapid development of the communication industry, mobile phones are increasingly widely used. Wherein, eMMC (Embedded Multi Media Card, memory chip) is as the large capacity memory cell among the cell-phone, as the memory cell of system firmware and APP software in the middle of the cell-phone system operation. Because eMMC is used as a storage particle of consumer, process upgrades of various manufacturers are very frequent, and when eMMC is upgraded and replaced, UT test (using an oscilloscope to test a timing signal of a single board) and function verification consume a great deal of workload, which brings a great challenge to life cycle management of a product.

In the prior art, the eMMC test is generally based on an oscilloscope for carrying out UT test and is matched with a whole machine for carrying out function test, and the two test methods inevitably require that eMMC particles are welded on a circuit board, so that the loss is serious.

In addition, when performing the eMMC read-write test, only whether the existing eMMC is functionally tested to pass or fail can be detected, and whether the timing margin of the current eMMC particles is sufficient or not and the timing margin comparison before and after the test is replaced cannot be estimated.

Disclosure of Invention

The embodiment of the invention provides a testing device and a testing method for a memory chip, which are used for solving the problems that the memory chip is worn in the eMMC particle testing process and a timing margin window signal cannot be evaluated.

In order to solve the technical problems, the embodiment of the invention provides the following technical scheme:

a test apparatus for a memory chip, comprising:

the test main board is provided with a Central Processing Unit (CPU), a programmable logic device (FPGA), a SOCKET clamp and at least one memory chip eMMC particle; the CPU is connected with the FPGA, the at least one eMMC particle is placed in the SOCKET clamp, and the FPGA is connected with one eMMC particle through a passage respectively;

the FPGA transmits and caches a DATA bus DATA signal and a clock bus CLK signal between the CPU and the at least one eMMC particle, controls the CLK signal to carry out phase shift processing on a sampling point of the DATA signal on time sequence according to a preset instruction of the CPU, and acquires a time sequence margin window signal delta T of the at least one eMMC particle by recording a time sequence boundary delta Ta of an establishment time Tsu and a time sequence boundary delta Tb of a holding time Thd under an abnormal state.

Optionally, the test motherboard further includes:

the memory comprises at least one DDR3 memory particle, wherein the at least one DDR3 memory particle is connected with the CPU and the FPGA;

caching FLASH, wherein the FLASH is connected with the CPU;

the CPU is started by the FLASH, and runs a program in the DDR3 particles;

the DDR3 particles are hung on the FPGA, and the DATA signals and the CLK signals between the CPU and the at least one eMMC particle are transmitted and cached in the DDR3 particles.

Optionally, the socks fixture includes:

an upper cover;

the upper cover covers the base;

and the spring thimble is connected with the base.

Optionally, one end of the spring thimble contacts with a ball grid array package BGA pin of the at least one eMMC particle; the other end of the spring thimble is welded to the test main board.

Optionally, the test device of the memory chip further includes:

the serial port for outputting the time sequence margin window signal delta T is completed, and the serial port is connected with an upper computer;

and the power supply is used for supplying power to the test main board.

The embodiment of the invention also provides a testing method of the memory chip, which is applied to the testing device of the memory chip, and comprises the following steps:

according to a preset instruction, the programmable logic device FPGA carries out phase shift processing on the sampling point of the DATA bus DATA signal by the clock bus CLK signal in time sequence;

acquiring a time sequence boundary delta Ta of the set-up time Tsu and a time sequence boundary delta Tb of the hold time Thd in an abnormal state through the phase shift processing of the FPGA;

obtaining a timing margin window signal delta T of at least one memory chip eMMC particle according to the delta Ta and the delta Tb;

outputting the timing margin window signal delta T.

Optionally, before the FPGA performs the time-sequence phase shift processing on the sampling point of the DATA signal by using the CLK signal according to a preset instruction, the method may further include:

and the cache FLASH starts a central processing unit CPU, and runs a test program in the memory DDR3 particles, and the FPGA gates a passage through internal logic to test the at least one eMMC particle respectively.

Optionally, after testing the at least one eMMC particle, further comprising:

the DATA signal and the CLK signal between the CPU and the at least one eMMC particle are transmitted through the FPGA and buffered in the DDR3 particle.

Optionally, the FPGA performs timing phase shift according to a preset instruction, to obtain a timing boundary, including:

the FPGA controls the CLK signal to carry out time sequence phase shift processing on the sampling point of the DATA signal according to the preset instruction of the CPU;

a time sequence moves forward, before the rising edge of the CLK signal arrives, the DATA signal is stable and unchanged, the time Tsu is established, and the time sequence boundary delta Ta of the Tsu in an abnormal state is recorded;

moving backward in time sequence, after the rising edge of the CLK signal comes, the DATA signal is held for a steady holding time Thd, and a time sequence boundary Δtb of the Thd in an abnormal state is recorded.

Optionally, obtaining a timing margin window signal Δt of the at least one eMMC particle according to the Δta and the Δtb, including:

the timing margin window signal Δt of the at least one eMMC particle is obtained by the formula Δt=Δta+Δtb.

The technical scheme of the invention has at least the following beneficial effects:

according to the testing device for the memory chip, disclosed by the embodiment of the invention, the nondestructive testing of the eMMC particles is realized by placing at least one eMMC particle in the SOCKET SOCKET clamp, and the eMMC particles are not required to be welded on a testing main board; the programmable logic device FPGA is connected with one eMMC particle through one passage respectively, and batch nondestructive testing of the eMMC particles is realized through the use of the SOCKET clamp and logic gating in the FPGA, so that the testing verification efficiency is greatly improved; the DATA bus DATA signal and the clock bus CLK signal between the CPU and at least one eMMC particle are transmitted and buffered through the FPGA, the sampling point of the DATA signal is controlled to carry out phase shift processing on time sequence according to the preset instruction of the CPU by the CLK signal, and the time sequence boundary delta Ta of the set-up time Tsu and the time sequence boundary delta Tb of the hold time Thd under abnormal state are recorded to obtain the time sequence margin window signal of the at least one eMMC particle, so that the digitalized time sequence margin window information is obtained, and the traditional oscilloscope UT test is replaced.

Drawings

FIG. 1 is a schematic diagram showing a structure of a testing apparatus for a memory chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram showing a structure of a SOCKET clamp according to an embodiment of the present invention;

FIG. 3 is a flow chart showing a method for testing a memory chip according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a data cache of a programmable logic device FPGA according to an embodiment of the present invention;

FIG. 5 is a timing reference diagram of an eMMC particle of a memory chip according to an embodiment of the present invention;

FIG. 6 is a diagram showing a CLK phase shift value in a critical state for acquisition setup time Tsu according to an embodiment of the invention;

FIG. 7 is a diagram showing the CLK phase shift values in the critical state of the acquisition hold time Thd according to an embodiment of the present invention.

Reference numerals illustrate:

100-testing a main board; 1-a central processing unit CPU; 2-caching FLASH; 3-a programmable logic device FPGA; 4-memory DDR3 particles; 5-memory chip eMMC particles; 600-socket eMMC fixture; 7-way; 8-an upper cover; 9-a base; 10-spring thimble.

Detailed Description

The present invention will be described in detail below with reference to the drawings and the specific embodiments thereof in order to make the objects, technical solutions and advantages of the present invention more apparent.

The invention provides a testing device and a testing method of a memory chip, aiming at the problems that eMMC particles are worn in the testing process and a timing margin window signal cannot be evaluated.

As shown in fig. 1 to 2, an embodiment of the present invention provides a test apparatus for a memory chip, including:

the test main board 100, wherein the test main board 100 is provided with a Central Processing Unit (CPU) 1, a programmable logic device (FPGA) 3, a SOCKET clamp 600 and at least one memory chip eMMC particle 5; the CPU1 is connected with the FPGA3, the at least one eMMC particle 5 is placed in the SOCKET clamp 600, and the FPGA3 is connected with one eMMC particle 5 through a passage 7 respectively;

the FPGA3 transmits and buffers the DATA bus DATA signal and the clock bus CLK signal between the CPU1 and the at least one eMMC particle 5, and controls the CLK signal to perform phase shift processing on the sampling point of the DATA signal in time sequence according to a preset instruction of the CPU1, and obtains the time sequence margin window signal Δt of the at least one eMMC particle 5 by recording the time sequence boundary Δta of the setup time Tsu and the time sequence boundary Δtb of the hold time Thd in an abnormal state.

In this embodiment of the present invention, the eMMC particles 5 do not need to be soldered on the test motherboard 100, so as to realize nondestructive testing of the eMMC particles 5; through the use of SOCKET anchor clamps 600 to and the inside logic gate of FPGA3, realized the batch nondestructive test of eMMC granule 5, reduced the work load that uses the oscilloscope to test the chronogenesis signal of veneer, promoted the eMMC granule 5 because of the accuracy of substitution test such as technology upgrading, greatly promote test verification efficiency.

In an alternative embodiment of the present invention, the test motherboard 100 further includes:

at least one memory DDR3 granule 4, said at least one DDR3 granule 4 being connected to said CPU (1) and said FPGA 3;

a FLASH2 is cached, and the FLASH2 is connected with the CPU 1;

the CPU1 is started by the FLASH2, and runs a program in the DDR3 particles 4;

the FPGA3 is externally hung on the DDR3 granule 4, and the DATA signal and the CLK signal between the CPU1 and the at least one eMMC granule 5 are transmitted and buffered in the DDR3 granule 4.

In this embodiment of the present invention, the memory DDR3 granule 4 serves as a program running buffer, and as shown in fig. 4, as a transmission buffer for the DATA bus DATA signal and the clock bus CLK signal, for a relatively adjusted FIFO (First Input First Output, simply referred to as a first-in first-out) buffer space.

In an alternative embodiment of the present invention, the SOCKET jig 600 includes:

an upper cover 8;

a base 9, wherein the upper cover 8 covers the base 9;

and a spring thimble 10 connected with the base 9.

Here, one end of the spring thimble 10 contacts with the ball grid array package BGA pins of the at least one eMMC particle 5; the other end of the spring pin 10 is welded to the test motherboard 100.

In this embodiment of the present invention, the spring pins 10 are in contact with the BGA pins of the eMMC particles 5, realizing a non-destructive test.

In an alternative embodiment of the present invention, the test device for a memory chip further includes:

the serial port for outputting the time sequence margin window signal delta T is completed, and the serial port is connected with an upper computer;

and a power supply for supplying power to the test motherboard 100.

In the embodiment of the invention, the acquired timing margin window signal delta T is reported to the upper computer through the serial port, so that the digitized timing margin window of eMMC particles is realized, and recording and evaluation are performed.

As shown in fig. 3, an embodiment of the present invention further provides a testing method of a memory chip, where the testing method is applied to the testing apparatus of a memory chip as set forth in any one of the above, and the method includes:

step S1, a programmable logic device FPGA3 performs phase shift processing on time sequence according to a preset instruction on sampling points of a clock bus CLK signal to a DATA bus DATA signal;

step S2, acquiring a time sequence boundary Δta of the setup time Tsu and a time sequence boundary Δtb of the hold time Thd in an abnormal state through the phase shift process of the FPGA 3;

step S3, obtaining a timing margin window signal delta T of at least one memory chip eMMC particle 5 according to the delta Ta and the delta Tb;

and S4, outputting the timing margin window signal delta T.

In this embodiment of the present invention, nondestructive testing can be performed without soldering eMMC particles 5 to a single board; the digital timing margin window information is obtained by using the FPGA3 through a clock and data phase shifting method, so that the traditional oscilloscope UT test is replaced; through the use of the SOCKET clamp 600 and the logic gating inside the FPGA3, the batch nondestructive testing of eMMC particles 5 is realized, and the testing verification efficiency is greatly improved.

Here, before the FPGA3 performs the phase shift processing on the sampling point of the DATA signal in the time sequence by using the CLK signal according to a preset instruction, the method may further include:

the cache FLASH2 starts the CPU1 and runs the test program in the DDR3 granules 4, and the FPGA3 gates a path 7 through internal logic to test the at least one eMMC granule 5.

Here, after the at least one eMMC particle 5 is tested, it further includes:

the DATA signal and the CLK signal between the CPU1 and the at least one eMMC particle 5 are transmitted through the FPGA3 and buffered in the DDR3 particle 4.

In this embodiment of the present invention, as shown in fig. 4, the DATA buffering of 8bit DATA and 1bit CLK in the FPGA3 is shown, DDR3 particles 4 are used as a DATA buffering space to assist in completing FIFO buffer management of clock and DATA, and the FPGA3 is controlled by the CPU1 to complete adjustment control of timing phase.

Here, in step S1 and step S2, the FPGA3 performs timing phase shift according to a preset instruction, and obtains a timing boundary, including:

the FPGA3 controls the CLK signal to carry out time sequence phase shift processing on the sampling point of the DATA signal according to the preset instruction of the CPU 1;

a time sequence moves forward, before the rising edge of the CLK signal arrives, the DATA signal is stable and unchanged, the time Tsu is established, and the time sequence boundary delta Ta of the Tsu in an abnormal state is recorded;

moving backward in time sequence, after the rising edge of the CLK signal comes, the DATA signal is held for a steady holding time Thd, and a time sequence boundary Δtb of the Thd in an abnormal state is recorded.

Here, step S3, obtaining a timing margin window signal Δt of the at least one eMMC particle 5 according to the Δta and the Δtb, includes:

the timing margin window signal Δt of the at least one eMMC particle 5 is obtained by the formula Δt=Δta+Δtb.

In this embodiment of the present invention, taking the write timing of eMMC particles 5 as an example, the CLK signal samples the DATA signal in double edges, which establish hold times Tsu and Thd, respectively, as shown in fig. 5.

Inside the FPGA3, the CPU1 is sent to 8bit data [0:7] and 1bit CLK of the eMMC granule 5, respectively, and buffering processing is performed in the DDR3 granule 4.

The timing relationship between CLK and DATA [0:7] is adjusted such that the sampling positions of the CLK to DATA [0:7] signals reach Tsu and Thd thresholds, respectively, as shown in FIGS. 6 and 7.

By the phase shift as shown in fig. 6 and 7, Δta where Tsu is at the boundary value and Δtb where Thd is at the boundary value are obtained.

The quantization timing margin window of the eMMC grain 5 is Δt=Δta+Δtb.

The transverse comparison can be performed by comparing the timing margin window signals delta T of different manufacturers and different models of the same manufacturer, the digitized timing margin window information of different manufacturers and models is obtained through quantized values, and under the condition that the timing margin window information is not tested by an oscilloscope UT, the timing margin window information can be effectively verified, so that the testing efficiency is greatly improved.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the principles of the present invention, and such modifications and changes are intended to be within the scope of the present invention.

Claims (9)

1. A memory chip testing apparatus, comprising:

the test device comprises a test main board (100), wherein a Central Processing Unit (CPU) (1), a programmable logic device (FPGA) (3), a SOCKET clamp (600) and at least one memory chip eMMC particle (5) are arranged on the test main board (100); the CPU (1) is connected with the FPGA (3), the at least one eMMC particle (5) is placed in the SOCKET clamp (600), and the FPGA (3) is connected with one eMMC particle (5) through a passage (7) respectively;

the FPGA (3) transmits and caches DATA bus DATA signals and clock bus CLK signals between the CPU (1) and the at least one eMMC particle (5), controls the CLK signals to carry out phase shift processing on sampling points of the DATA signals in time sequence according to preset instructions of the CPU (1), and acquires a time sequence margin window signal delta T, delta T=delta Ta+delta Tb of the at least one eMMC particle (5) by recording a time sequence boundary delta Ta of an establishment time Tsu and a time sequence boundary delta Tb of a holding time Thd in an abnormal state.

2. The device for testing a memory chip according to claim 1, wherein the test motherboard (100) further comprises:

the memory DDR3 particles (4) are arranged, and the DDR3 particles (4) are connected with the CPU (1) and the FPGA (3);

the FLASH (2) is cached, and the FLASH (2) is connected with the CPU (1);

the CPU (1) is started by the FLASH (2) and runs a program in the DDR3 particles (4);

the FPGA (3) is externally hung with the DDR3 particles (4), and the DATA signals and the CLK signals between the CPU (1) and the at least one eMMC particle (5) are transmitted and cached in the DDR3 particles (4).

3. The memory chip testing device according to claim 1, wherein the SOCKET clamp (600) comprises:

an upper cover (8);

a base (9), wherein the upper cover (8) covers the base (9);

and a spring thimble (10) connected with the base (9).

4. A device for testing a memory chip according to claim 3, wherein one end of the spring pin (10) is in contact with a ball array package BGA pin of the at least one eMMC particle (5); the other end of the spring thimble (10) is welded to the test main board (100).

5. The memory chip testing device of claim 1, further comprising:

the serial port for outputting the time sequence margin window signal delta T is completed, and the serial port is connected with an upper computer;

and a power supply for supplying power to the test motherboard (100).

6. A method of testing a memory chip, wherein the method is applied to the apparatus for testing a memory chip according to any one of claims 1 to 5, the method comprising:

according to a preset instruction, the programmable logic device FPGA (3) carries out phase shift processing on the time sequence on sampling points of the DATA bus DATA signals by the clock bus CLK signals;

acquiring a time sequence boundary delta Ta of the set-up time Tsu and a time sequence boundary delta Tb of the hold time Thd in an abnormal state through the phase shift processing of the FPGA (3);

obtaining a timing margin window signal deltat of at least one memory chip eMMC particle (5) by the formula deltat = deltata + deltatb;

outputting the timing margin window signal delta T.

7. The method for testing a memory chip according to claim 6, wherein before the FPGA (3) performs the phase shift processing on the sampling point of the DATA signal in the time sequence on the CLK signal according to a preset instruction, the method further comprises:

the cache FLASH (2) starts a central processing unit CPU (1) and runs a test program in a memory DDR3 particle (4), and the FPGA (3) gates a passage (7) through internal logic to test at least one eMMC particle (5) respectively.

8. The method of testing a memory chip according to claim 7, further comprising, after testing the at least one eMMC particle (5):

the DATA signal and the CLK signal between the CPU (1) and the at least one eMMC particle (5) are transmitted through the FPGA (3) and buffered in the DDR3 particle (4).

9. The method for testing a memory chip according to claim 6, wherein the FPGA (3) performs timing phase shift according to a preset instruction to obtain a timing boundary, comprising:

the FPGA (3) controls the sampling point of the CLK signal to the DATA signal according to the preset instruction of the CPU (1) to perform phase shift processing on time sequence;

a time sequence moves forward, before the rising edge of the CLK signal arrives, the DATA signal is stable and unchanged, the time Tsu is established, and the time sequence boundary delta Ta of the Tsu in an abnormal state is recorded;

moving backward in time sequence, after the rising edge of the CLK signal comes, the DATA signal is held for a steady holding time Thd, and a time sequence boundary Δtb of the Thd in an abnormal state is recorded.