CN112992221B - SRAM (static random Access memory) storage unit based on back gate structure, SRAM memory and power-on method - Google Patents

SRAM (static random Access memory) storage unit based on back gate structure, SRAM memory and power-on method Download PDF

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CN112992221B
CN112992221B CN202110213230.6A CN202110213230A CN112992221B CN 112992221 B CN112992221 B CN 112992221B CN 202110213230 A CN202110213230 A CN 202110213230A CN 112992221 B CN112992221 B CN 112992221B
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inverter
transistor
back gate
gate structure
sram
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CN112992221A (en
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李博
苏泽鑫
宿晓慧
刘凡宇
杨灿
罗家俊
韩郑生
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Institute of Microelectronics of CAS
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention discloses an SRAM memory cell based on a back gate structure, an SRAM memory and a power-on method, and belongs to the field of semiconductors. The technical problem that when a certain storage unit stores fixed data for a long time, BT I aging effects of different degrees occur on two symmetrical transistors to generate permanent threshold voltage mismatch, and therefore an SRAM storage unit is powered on, and a power-on initial value opposite to an original storage value is read out with a certain probability is solved. The SRAM storage unit based on the back gate structure comprises a first inverter and a second inverter; the transistors in the first inverter and the second inverter are both back gate transistors; the back gate of the transistor in the first inverter has a first connection mode, the back gate of the transistor in the second inverter has a second connection mode, and when the SRAM storage unit based on the back gate structure is powered on, the threshold voltage of the transistor in the first inverter is different from the threshold voltage of the transistor in the second inverter.

Description

SRAM (static random Access memory) storage unit based on back gate structure, SRAM memory and power-on method
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SRAM memory cell based on a back gate structure, an SRAM memory and a power-on method.
Background
An SRAM (static-Random-Access Memory) is a Memory having a static Access function, and can store data stored therein without a refresh circuit. When SRAM is used in a chip, the system-on-chip may power off the SRAM to prevent an attacker from stealing data when the system-on-chip detects unauthorized access. However, the SRAM has a problem of information remaining, and the information stored before the power failure can be partially restored by the method of aging stamp extraction. The aging imprint extraction means that when a certain memory cell stores fixed data for a long time, two symmetrical transistors will generate different degrees of BTI (Bias Temperature Instability) aging effects to generate permanent threshold voltage mismatch, so that the SRAM memory cell has a certain probability (about 10% -20%) of reading a power-on initial value opposite to an original stored value after being powered on.
Disclosure of Invention
Based on this, the invention aims to provide an SRAM memory cell based on a back gate structure, an SRAM memory and a power-on method, so as to solve the technical problem that when the SRAM memory cell stores fixed data for a long time, two symmetrical transistors will generate different degrees of BTI aging effect, generate a permanent threshold voltage mismatch, and cause a power-on initial value opposite to an original stored value to be read out with a certain probability after the SRAM memory cell is powered on.
In a first aspect, the present invention provides a back gate structure based SRAM memory cell comprising a first inverter and a second inverter cross-coupled. The transistors in the first inverter and the second inverter are both back gate transistors;
the back gate of the transistor in the first inverter has a first connection mode, the back gate of the transistor in the second inverter has a second connection mode, and when the SRAM storage unit based on the back gate structure is powered on, the threshold voltages of the transistor in the first inverter and the transistor in the second inverter are different.
Compared with the prior art, the SRAM storage unit based on the back-gate structure comprises the first inverter and the second inverter which are both back-gate transistors, the back gate of the transistor in the first inverter has a first connection mode, the back gate of the transistor in the second inverter has a second connection mode, and when the SRAM storage unit based on the back-gate structure is electrified, the threshold voltage of the transistor in the first inverter is different from the threshold voltage of the transistor in the second inverter. In practical applications, when the SRAM memory cell is powered on, the threshold voltages of the transistors in the first inverter and the transistors in the second inverter are different, so that the turn-on time of the transistors in the first inverter is different from that of the transistors in the second inverter. Based on this, the power-on potential of one of the two storage nodes in the SRAM memory cell tends to be "0", and the power-on potential of the other storage node tends to be "1". At the moment, two storage nodes in the SRAM storage unit have fixed power-on potentials, so that the technical problem that when the SRAM storage unit stores fixed data for a long time, the two symmetrical transistors generate BTI aging effects of different degrees to generate permanent threshold voltage mismatch, and the SRAM storage unit reads a power-on initial value opposite to an original storage value at a certain probability after being powered on is solved.
In a second aspect, the invention also discloses an SRAM memory, which includes the above SRAM memory cell based on the back gate structure.
In a third aspect, the present invention also discloses a power-on method, including:
connecting the back gates of the transistors in the first inverter by adopting a first connection mode, and connecting the back gates of the transistors in the second inverter by adopting a second connection mode;
and controlling the SRAM storage unit based on the back gate structure to be powered on, wherein the threshold voltage of the transistor in the first inverter is larger than or smaller than that of the transistor in the second inverter.
The beneficial effects of the second and third aspects of the present invention are the same as those of the first aspect, and are not described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not limit the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating a main circuit of an SRAM memory cell provided by an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a circuit structure of an SRAM memory cell based on a back gate structure according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of another SRAM memory cell based on a back gate structure according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram illustrating another SRAM memory cell based on a back gate structure according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a circuit structure of another SRAM memory cell based on a back gate structure according to an embodiment of the present invention;
fig. 6 shows a read-write timing diagram of an SRAM memory cell based on a back gate structure according to an embodiment of the present invention;
FIG. 7 is a graph illustrating static noise margin mismatch for a back gate structure based SRAM cell structure provided by an embodiment of the present invention;
fig. 8 is a static noise tolerance mismatch diagram of another SRAM cell structure based on a back gate structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Various schematic diagrams of embodiments of the invention are shown in the drawings, which are not drawn to scale. Wherein certain details are exaggerated and possibly omitted for clarity of understanding. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.
In the present invention, unless expressly stated or limited otherwise, the term "coupled" is to be interpreted broadly, e.g., "coupled" may be fixedly coupled, detachably coupled, or integrally formed; may be directly connected or indirectly connected through an intermediate.
An SRAM (static-Random-Access Memory) is a Memory having a static Access function, and can store data stored therein without a refresh circuit. When SRAM is used in a chip, the system-on-chip may power off the SRAM to prevent an attacker from stealing data when the system-on-chip detects unauthorized access. However, the SRAM has a problem of information remaining, and the information stored before the power failure can be partially restored by the method of aging stamp extraction. The aging imprinting extraction means that when a certain storage unit stores fixed data for a long time, two symmetrical transistors generate different degrees of BTI aging effect to generate permanent threshold voltage mismatch, so that the SRAM storage unit has a certain probability (about 10% -20%) of reading an initial power-on value opposite to an original storage value after being powered on.
In the related art, referring to fig. 1, an sram memory cell includes a first inverter 11 and a second inverter 12 which are cross-coupled; the first inverter 11 and the second inverter 12 are cross-coupled to form a first storage node Q and a second storage node QB. The first storage node Q and the second storage node QB are used to store one bit of binary information 0 or 1.
For example, the SRAM memory cell provided by the embodiment of the present invention may be a six-pipe SRAM memory cell. The six-tube SRAM memory cell is a trigger formed by cross coupling of two MOS inverters, and one memory cell stores a one-bit binary number. The six-tube SRAM memory cell has two stable states, and the storage information of the first storage node and the second storage node of the six-tube SRAM memory cell are always opposite to each other. For example, if the storage information of the first storage node indicates 0, the storage information of the second storage node indicates 1. For another example, if the storage information of the first storage node indicates 1, the storage information of the second storage node indicates 0.
Specifically, referring to fig. 1, the circuit structures of the first inverter 11 and the second inverter 12 are axisymmetric along the central axis of the memory cell.
The first inverter 11 includes a first P-type transistor P1 and a first N-type transistor N1; the source of the first P-type transistor P1 is electrically connected to the power supply terminal VDD, the drain of the first P-type transistor P1 and the drain of the first N-type transistor N1 are electrically connected to the first storage node Q, the source of the first N-type transistor N1 is grounded (electrically connected to the ground terminal GND), and the gate of the first P-type transistor P1 and the gate of the first N-type transistor N1 are electrically connected to the second storage node QB.
The second inverter comprises 12 a second P-type transistor P2 and a second N-type transistor N2; the source of the second P-type transistor P2 is electrically connected to the power supply terminal VDD, the drain of the second P-type transistor P2 and the drain of the second N-type transistor N2 are electrically connected to the second storage node QB, the source of the second N-type transistor N2 is grounded (electrically connected to the ground terminal GND), and the gate of the second P-type transistor P2 and the gate of the second N-type transistor N2 are electrically connected to the first storage node Q.
Referring to fig. 1, the memory cell further includes a third N-type transistor N3 and a fourth N-type transistor N4; the source of the third N-type transistor N3 is electrically connected to the first storage node, the drain is connected to the bit line BLB, and the gate is electrically connected to the word line. The source of the fourth N-type transistor N4 is electrically connected to the second storage node, the drain is connected to the bit line BL, and the gate is electrically connected to the word line.
The P-type transistor and the N-type transistor applied in the memory cell are both metal oxide semiconductor field effect transistors. Since the mosfet has a high input impedance, direct coupling is facilitated in the circuit, and a large-scale integrated circuit can be easily manufactured, the mosfet is applied to the first inverter and the second inverter in the embodiment of the present invention, and the integrated circuit can be easily formed in the subsequent process.
Based on this, in the related art, it is assumed that the storage node in the first inverter stores data at a high level and the storage node in the second inverter stores data at a low level. At this time, the first P-type transistor P1 and the first N-type transistor N1 in the first inverter are in a negative bias state and a positive bias state, respectively, and if the states are in the states for a long time, the BTI effect is likely to occur in the first P-type transistor P1 and the first N-type transistor N1. After that, if the SRAM memory cell performs a restart operation, since the first P-type transistor P1 and the first N-type transistor N1 in the first inverter are more difficult to turn on than the second P-type transistor P2 and the second N-type transistor N2 in the second inverter, the storage node in the second inverter is charged by the power supply voltage first, and the storage node in the first inverter is discharged by the second transistor, so that the data stored in the storage node in the first inverter and the storage node in the second inverter are more likely to be "0" and "1" in a steady state. Therefore, the SRAM memory cell has non-volatility due to the BTI aging effect, the power-on data has certain correlation with the previously stored data, and the safety is greatly reduced.
Based on the above, the embodiment of the invention discloses an SRAM memory cell based on a back gate structure, which comprises a first inverter and a second inverter which are cross-coupled. The transistors in the first inverter and the second inverter are both back gate transistors. The back gate of the transistor in the first inverter has a first connection mode, the back gate of the transistor in the second inverter has a second connection mode, and when the SRAM storage unit based on the back gate structure is powered on, the threshold voltages of the transistor in the first inverter and the transistor in the second inverter are different.
It will be appreciated that the first inverter and the second inverter are cross-coupled to form a first storage node and a second storage node. In practical applications, when the SRAM memory cell is powered on, the threshold voltages of the transistors in the first inverter and the transistors in the second inverter are different, so that the turn-on time of the transistors in the first inverter is different from that of the transistors in the second inverter. Based on this, the power-on potential of one of the two storage nodes in the SRAM memory cell tends to be "0", and the power-on potential of the other storage node tends to be "1". At the moment, two storage nodes in the SRAM storage unit have fixed power-on potentials, so that the technical problem that when the SRAM storage unit stores fixed data for a long time, the two symmetrical transistors generate BTI aging effects of different degrees to generate permanent threshold voltage mismatch, and the SRAM storage unit reads a power-on initial value opposite to an original storage value at a certain probability after being powered on is solved.
In some embodiments, the back gate of the transistor in the first inverter is electrically connected to a first potential terminal, and the back gate of the transistor in the second inverter is electrically connected to a second potential terminal; wherein the potential of the first potential terminal and the potential of the second potential terminal are different. It is understood that the potential of the first potential terminal and the potential of the second potential terminal are different including: the potential of the first potential terminal is greater than the potential of the second potential terminal, or the potential of the first potential terminal is less than the potential of the second potential terminal.
When the potential of the first potential terminal is greater than that of the second potential terminal, the first potential terminal may be a power supply terminal and the second potential terminal may be a ground terminal.
Fig. 2 shows a circuit configuration diagram of the SRAM memory cell based on the back gate structure in such a case as described above. Referring to fig. 2, the back gates of the P-type back gate MOS transistor P1 and the N-type back gate MOS transistor N1 in the first inverter are both electrically connected to the power supply terminal VDD. The back gates of the P-type back gate MOS transistor P2 and the N-type back gate MOS transistor N2 in the second inverter are both electrically connected to the ground GND.
It can be understood that, for an N-type MOS transistor with a back gate and a P-type MOS transistor, when a positive voltage is applied to the back gate, the threshold voltage of the N-type MOS transistor becomes smaller, and the threshold voltage of the P-type MOS transistor becomes larger.
Referring to fig. 2, when the back gates of the P1 transistor and the N1 transistor are connected to the power supply, the threshold voltage of the P1 transistor is greater than that of the P2 transistor, and the threshold voltage of the N1 transistor is less than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on, the P1 transistor is more difficult to turn on, the power supply first charges the storage node QB through the P2 transistor, so that the storage node Q reaches a high level first and is balanced, so that the storage node Q is more inclined to "0" after power on, and the storage node QB is more inclined to "1".
When the potential of the first potential terminal is greater than that of the second potential terminal, and the SRAM memory cell based on the back gate structure is powered on, and the word line is at a high potential, the first potential terminal may be a word line terminal, and the second potential terminal may be a ground terminal. Fig. 3 shows a circuit configuration diagram of the SRAM memory cell based on the back gate structure in this case.
Referring to fig. 3, the back gates of the P-type back gate MOS transistor P1 and the N-type back gate MOS transistor N1 in the first inverter are both electrically connected to the word line WL. The back gates of the P-type back gate MOS transistor P2 and the N-type back gate MOS transistor N2 in the second inverter are both electrically connected to the ground GND. When the back gates of the P1 transistor and the N1 transistor are connected to the word line WL, the threshold voltage of the P1 transistor is greater than that of the P2 transistor, and the threshold voltage of the N1 transistor is less than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on, the P1 transistor is more difficult to turn on, a power supply firstly charges the storage node QB through the P2 transistor, so that the storage node Q reaches a high level first and is balanced, so that the storage node Q is more inclined to "0" after the power on, and the storage node QB is more inclined to "1". Compared with the way that the back gates of the P1 transistor and the N1 transistor are connected to the power supply, the back gates of the P1 transistor and the N1 transistor are connected to the word line WL, the back gate bias of the P1 transistor and the back gate bias of the N1 transistor are enabled only when the word line WL is activated, and the stability of the SRAM memory cell is maintained in the memory stage.
When the potential of the first potential terminal is less than that of the second potential terminal, the first potential terminal may be a ground terminal and the second potential terminal may be a power source terminal.
Fig. 4 shows a circuit configuration diagram of the SRAM memory cell based on the back gate structure in this case. Referring to fig. 4, the back gates of the P-type back gate MOS transistor P1 and the N-type back gate MOS transistor N1 in the first inverter are both electrically connected to the ground GND. The back gates of the P-type back gate MOS tube P2 and the N-type back gate MOS tube N2 in the second inverter are electrically connected with a power supply end VDD.
It can be understood that, for an N-type MOS transistor with a back gate and a P-type MOS transistor, when a positive voltage is applied to the back gate, the threshold voltage of the N-type MOS transistor becomes smaller, and the threshold voltage of the P-type MOS transistor becomes larger.
Referring to fig. 4, when the back gates of the P1 transistor and the N1 transistor are connected to the ground, the threshold voltage of the P1 transistor is less than that of the P2 transistor, and the threshold voltage of the N1 transistor is greater than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on, the P1 transistor is more easily turned on, and the power supply first charges the storage node Q through the P1 transistor, so that the storage node Q reaches a high level first and is balanced, so that the storage node Q is more inclined to "1" after being powered on, and the storage node QB is more inclined to "0".
When the potential of the first potential terminal is less than that of the second potential terminal, and the SRAM memory cell based on the back gate structure is powered on, and the word line is at a high potential, the first potential terminal may be a ground terminal, and the second potential terminal may be a word line terminal. Fig. 5 shows a circuit configuration diagram of the SRAM memory cell based on the back gate structure in this case.
Referring to fig. 5, the back gates of the P-type back gate MOS transistor P1 and the N-type back gate MOS transistor N1 in the first inverter are both electrically connected to the ground GND. The back gates of the P-type back gate MOS transistor P2 and the N-type back gate MOS transistor N2 in the second inverter are both electrically connected to the word line WL. When the back gates of the P2 transistor and the N2 transistor are connected to the word line WL, the threshold voltage of the P1 transistor is smaller than that of the P2 transistor, and the threshold voltage of the N1 transistor is larger than that of the N2 transistor, so that when the SRAM memory cell based on the back gate structure is powered on, the P1 transistor is more easily turned on, the power supply first charges the storage node Q through the P1 transistor, so that the storage node Q reaches a high level first and is balanced, so that the storage node Q is more inclined to "1" after power-on, and the storage node QB is more inclined to "0". Compared with the way that the back gates of the P2 transistor and the N2 transistor are connected to the power supply, the back gates of the P2 transistor and the N2 transistor are connected to the word line WL, the back gate bias of the P2 transistor and the N2 transistor can be guaranteed to be effective only when the word line WL is activated, and the stability of the SRAM memory cell is maintained in the storage phase.
Fig. 6 shows a waveform diagram of a read/write timing of an SRAM memory cell according to an embodiment of the present invention, where the functions of write 1, read 1, write 0, and read 0 of the SRAM memory cell circuit of the present invention are all normal. The basic time sequence is the same as that of the traditional SRAM memory unit, when WL is high level, BL is high level and BLB is low level, 1 writing is carried out, Q point level is raised, and 1 writing is successful. When WL is high level, BL and BLB are both high level, reading operation is carried out, BLB line discharges through QB point, electric potential drops, reading 1 succeeds; when WL is high level, BLB is high level, BL is low level, write 0 operation is carried out, QB point level is raised, write 0 is successful; when WL is high level, BL and BLB are both high level, reading operation is carried out, BL line discharges through Q point, potential drops, reading 0 succeeds.
In any case, when the SRAM memory cell based on the back gate structure is powered on, the first storage node is biased to '0' or '1', which is represented by a mismatch of the static noise tolerance.
Fig. 7 shows a static noise margin mismatch diagram of an SRAM cell, and referring to fig. 7, curves 1 to 4 are input/output characteristic curves of one of two inverters constituting the SRAM, wherein the abscissa and ordinate of curve 3 are the output voltage and the input voltage of one of the inverters respectively in the case of the SRAM memory cell in the related art. The abscissa and ordinate of curve 4 are the input voltage and the output voltage, respectively, of one of the inverters in the prior art SRAM memory cell. The abscissa and the ordinate of the curve 1 are respectively the output voltage and the input voltage of one of the inverters when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used. The abscissa and the ordinate of curve 2 are the input voltage and the output voltage of one of the inverters when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used, respectively.
Referring to fig. 7, the ranges of the left and right graphs enclosed by the curves 3 and 4 are the same, that is, in the prior art, at the time of power-up, the probability that the power-up initial value of the inverter in the SRAM memory cell is 0 or 1 is equal.
Referring to fig. 7, the ranges of the left and right patterns enclosed by the curves 1 and 2 are different. The method specifically comprises the following steps: the area of the left figure is smaller than the area of the right figure. The area of the left graph is used for representing the probability that the power-on initial value of the inverter in the SRAM storage unit is 0 when the SRAM storage unit is powered on, and the area of the left graph is used for representing the probability that the power-on initial value of the inverter in the SRAM storage unit is 1 when the SRAM storage unit is powered on. That is, in the SRAM memory cell based on the back gate structure, at the time of power-on, the probability that the power-on initial value of the inverter in the SRAM memory cell based on the back gate structure is 1 is greater than the probability that the power-on initial value is. Based on this, the probability of the power-on initial value '1' of the SRAM memory cell based on the back gate structure provided by the embodiment of the invention is obviously greater than the probability of the power-on initial value '0', so that the large probability is fixed as '1' during power-on, and the threat of data security brought by aging imprinting can be relieved. Therein, curves 1 and 2 of fig. 7 correspond to the input-output characteristic curves of the SRAM memory cell based on the back gate structure in fig. 4 and 5.
Fig. 8 shows another SRAM cell static noise margin mismatch diagram, and referring to fig. 8, curves 5 to 8 are input/output characteristic curves of one of two inverters constituting an SRAM, wherein the abscissa and ordinate of the curve 5 are the output voltage and the input voltage of one of the inverters when the SRAM memory cell in the related art is used, respectively. The abscissa and ordinate of curve 6 are the input voltage and the output voltage, respectively, of another inverter in the case of a prior art SRAM memory cell. The abscissa and the ordinate of the curve 7 are the output voltage and the input voltage of one of the inverters when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used, respectively. The abscissa and ordinate of the curve 8 are the input voltage and the output voltage of another inverter when the SRAM memory cell based on the back gate structure in the embodiment of the present invention is used, respectively.
Referring to fig. 8, the ranges of the left and right graphs enclosed by the curves 5 and 6 are the same, that is, in the SRAM memory cell of the prior art, the probability that the power-on initial value of the inverter in the SRAM memory cell is 0 or 1 is equal when the power-on is performed.
Referring to fig. 8, the ranges of the left and right patterns enclosed by the curves 7 and 8 are different. The method specifically comprises the following steps: the area of the left figure is larger than the area of the right figure. The area of the left graph is used for representing the probability that the power-on initial value of the inverter in the SRAM storage unit based on the back gate structure is 0 when the SRAM storage unit is powered on, and the area of the right graph is used for representing the probability that the power-on initial value of the inverter in the SRAM storage unit based on the back gate structure is 1 when the SRAM storage unit based on the back gate structure is powered on. That is, in the SRAM memory cell based on the back gate structure, at the time of power-on, the probability that the power-on initial value of the inverter in the SRAM memory cell based on the back gate structure is 1 is smaller than the probability that the power-on initial value is 0. Based on this, the probability of the power-on initial value '0' of the SRAM memory cell based on the back gate structure provided by the embodiment of the invention is obviously greater than the probability of the power-on initial value '1', so that the large probability is fixed as '0' during power-on, and the threat of data security brought by aging imprinting can be relieved. Among them, curves 7 and 8 of fig. 8 correspond to the input-output characteristic curves of the SRAM memory cell based on the back gate structure in fig. 2 and 3.
It is noted that the power-on initial value of the back-gate structure-based SRAM memory cell mentioned in the embodiment of the present invention refers to the power-on initial value of Q in the back-gate structure-based SRAM memory cell.
The embodiment of the invention also discloses an SRAM memory, which comprises the SRAM memory cell based on the back gate structure.
The SRAM memory has the same technical effect as the SRAM memory cell based on the back gate structure provided in the embodiment of the present invention, and details are not described here.
The invention also discloses a power-on method, which comprises the following steps:
connecting the back gates of the transistors in the first inverter by adopting a first connection mode, and connecting the back gates of the transistors in the second inverter by adopting a second connection mode;
and controlling the SRAM storage unit based on the back gate structure to be powered on, wherein the threshold voltage of the transistor in the first inverter is larger than or smaller than that of the transistor in the second inverter.
The power-on method provided by the embodiment of the invention has the same technical effect as the SRAM memory cell provided by the embodiment of the invention, and is not described herein again.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (7)

1. An SRAM memory cell based on a back gate structure is characterized by comprising a first inverter and a second inverter which are cross-coupled; the transistors in the first inverter and the second inverter are both back gate transistors;
the back gate of the transistor in the first inverter has a first connection mode, the back gate of the transistor in the second inverter has a second connection mode, and when the SRAM storage unit based on the back gate structure is powered on, the threshold voltage of the transistor in the first inverter is different from the threshold voltage of the transistor in the second inverter;
a back gate of the transistor in the first inverter is electrically connected to a first potential terminal, and a back gate of the transistor in the second inverter is electrically connected to a second potential terminal; wherein the first potential terminal and the second potential terminal have different potentials;
the first potential end is a high potential end, and the second potential end is a low potential end;
or, the first potential end is a low potential end, and the second potential end is a high potential end; the high potential end is a power supply end or a word line end, and the low potential end is a ground end.
2. The back-gate structure based SRAM memory cell of claim 1, wherein said first potential terminal is said power supply terminal and said second potential terminal is said ground terminal.
3. The back-gate structure based SRAM memory cell of claim 1, wherein when the back-gate structure based SRAM memory cell is powered on and the word line is at a high potential, the first potential terminal is the word line terminal, and the second potential terminal is the ground terminal.
4. The back-gate structure-based SRAM memory cell of claim 1, wherein the first potential terminal is the ground terminal and the second potential terminal is the power supply terminal.
5. The back-gate structure based SRAM memory cell of claim 1, wherein when the back-gate structure based SRAM memory cell is powered on and a word line is at a high potential, the first potential terminal is the ground terminal and the second potential terminal is the word line terminal.
6. An SRAM memory comprising the back gate structure based SRAM memory cell of any one of claims 1-5.
7. A power-up method applied to the back gate structure based SRAM memory cell according to any one of claims 1 to 5, the power-up method comprising:
connecting the back gate of the transistor in the first inverter by adopting a first connection mode, and connecting the back gate of the transistor in the second inverter by adopting a second connection mode;
controlling the SRAM storage unit based on the back gate structure to be powered on, wherein the threshold voltage of the transistor in the first inverter is larger than or smaller than the threshold voltage of the transistor in the second inverter.
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