CN112948298A

CN112948298A - Message processing method and device

Info

Publication number: CN112948298A
Application number: CN202110407969.0A
Authority: CN
Inventors: 郭建华
Original assignee: New H3C Security Technologies Co Ltd
Current assignee: New H3C Security Technologies Co Ltd
Priority date: 2021-04-15
Filing date: 2021-04-15
Publication date: 2021-06-11

Abstract

The embodiment of the application provides a message processing method and device. The scheme is as follows: sending a plurality of reading requests carrying labels to a CPU (central processing unit) so that the CPU feeds back a data completion message carrying the labels included in each reading request to a logic chip; receiving a data completion message carrying a label and fed back by a CPU; caching the received data completion message to a storage space corresponding to the value of the label carried by the data completion message; and processing a data completion message in a storage space corresponding to a label carried by each read request according to the sending sequence of the plurality of read requests. By applying the technical scheme provided by the embodiment of the application, the communication speed between the CPU and the logic chip is improved.

Description

Message processing method and device

Technical Field

The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for processing a packet.

Background

PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, and is widely used for communication between a CPU (Central Processing Unit) and a logic chip on a computer.

Because the PCIE protocol does not require that the peer device respond to CplD (Completion with Data) packets of the read request, in order to meet the requirement of the communication protocol on the packet sequence, when the CPU and the logic chip communicate based on the PCIE protocol, the peer device sends the read request to the peer device, and then sends the next read request after receiving the CplD packet of the peer device responding to the read request.

The communication mode is realized by a Direct Memory Access (DMA), that is, the sending end must receive the CpID message sent by the receiving end to initiate the next read request, which results in that the batch processing capability of the CPU is not fully utilized, and the communication rate between the CPU and the logic chip is greatly limited.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method and an apparatus for processing a packet, so as to improve a communication rate between a CPU and a logic chip. The specific technical scheme is as follows:

the embodiment of the application provides a message processing method, which is applied to a logic chip, wherein the logic chip is connected with a CPU (central processing unit) through a PCIE (peripheral component interface express) protocol, the logic chip comprises a preset number of storage spaces, and each storage space has a corresponding label value, and the method comprises the following steps:

sending a plurality of reading requests carrying labels to the CPU, so that the CPU feeds back a data completion message carrying the labels included in each reading request to the logic chip;

receiving a data completion message carrying a label and fed back by the CPU;

caching the received data completion message to a storage space corresponding to the value of the label carried by the data completion message;

and processing a data completion message in a storage space corresponding to a label carried by each read request according to the sending sequence of the plurality of read requests.

Optionally, the step of sending a plurality of read requests carrying tags to the CPU includes:

for each read request carrying a label, detecting whether a token exists in a preset token bucket, wherein the preset token bucket comprises a preset number of tokens;

if yes, taking out the token from the preset token bucket;

sending the read request carrying the label to the CPU according to the taken token;

the method further comprises the following steps:

and when a data completion message corresponding to a read request is processed, generating a token, and adding the generated token into the preset token bucket.

Optionally, the method further includes:

when a read request is acquired, adding a tag to the read request, and adding 1 to the value of the tag;

and when the value of the label is the maximum value of the label, updating the value of the label to be 0.

Optionally, the logic chip includes preset variables, a maximum value of the preset variables is the preset number, and values of the preset variables correspond to the storage space one to one;

the step of processing the data completion packet in the storage space corresponding to the tag included in each read request according to the sending sequence of the plurality of read requests includes:

processing a data completion message stored in a storage space corresponding to the value of the preset variable, and adding 1 to the value of the preset variable;

and when the value of the preset variable is the preset number, updating the value of the preset variable to be 0.

Optionally, the data completion message is a fragment message;

the step of processing the data completion packet stored in the storage space corresponding to the value of the preset variable and adding 1 to the value of the preset variable includes:

detecting whether a last data completion message is stored in a storage space corresponding to the value of the preset variable, wherein the last data completion message is the last message in the data completion messages carrying the read requests of the labels corresponding to the storage space; and if so, processing the data completion message stored in the storage space, and adding 1 to the value of the preset variable.

Optionally, the length of the storage space is a preset multiple of the length of the maximum data completion packet of the read request.

The embodiment of the present application further provides a packet processing device, which is applied to a logic chip, where the logic chip is connected to a CPU through a PCIE protocol, the logic chip includes a preset number of storage spaces, and each storage space has a value of a corresponding tag, and the device includes:

a sending module, configured to send multiple read requests carrying tags to the CPU, so that the CPU feeds back a data completion packet carrying a tag included in each read request to the logic chip;

the receiving module is used for receiving the data completion message which carries the label and is fed back by the CPU;

the cache module is used for caching the received data completion message to a storage space corresponding to the value of the label carried by the data completion message;

and the processing module is used for processing the data completion message in the storage space corresponding to the label carried by each read request according to the sending sequence of the plurality of read requests.

Optionally, the sending module is specifically configured to detect whether a token exists in a preset token bucket for each read request carrying a tag, where the preset token bucket includes a preset number of tokens; if yes, taking out the token from the preset token bucket; sending the read request carrying the label to the CPU according to the taken token;

the device further comprises:

and the first adding module is used for generating a token when processing a data completion message corresponding to a read request, and adding the generated token into the preset token bucket.

Optionally, the apparatus further comprises:

the second adding module is used for adding a label to the read request and adding 1 to the value of the label when the read request is acquired;

the first updating module is used for updating the value of the label to be 0 when the value of the label is the maximum value of the label.

the processing module is specifically configured to process a data completion packet stored in a storage space corresponding to the value of the preset variable, and add 1 to the value of the preset variable; and when the value of the preset variable is the preset number, updating the value of the preset variable to be 0.

Optionally, the data completion message is a fragment message;

the processing module is specifically configured to detect whether a last data completion packet is stored in a storage space corresponding to the value of the preset variable, where the last data completion packet is a last packet in data completion packets carrying a read request of a tag corresponding to the storage space; and if so, processing the data completion message stored in the storage space, and adding 1 to the value of the preset variable.

Embodiments of the present application further provide a logic chip, including a processor and a machine-readable storage medium storing machine-executable instructions executable by the processor, the processor being caused by the machine-executable instructions to: implementing any of the above described message processing method steps.

Embodiments of the present application further provide a machine-readable storage medium storing machine-executable instructions executable by the processor, the processor being caused by the machine-executable instructions to: implementing any of the above described message processing method steps.

In the technical scheme provided by the embodiment of the application, the logic chip adds the label in the read request, so that the data completion message responded by the CPU also carries the corresponding label. Different read requests and different tags are carried. After a received data completion message which is fed back by the CPU and carries a label is received, the received data completion message is stored in a storage space corresponding to the value of the label based on the label, so that the data completion message in the storage space corresponding to the label included in the read request is processed according to the sending sequence of the read request, the processing sequence of the data completion message is the same as the sequence of the read request, and the requirement of a communication protocol on the message sequence is met. Therefore, in the embodiment of the application, the logic chip can send a plurality of read requests carrying different tags in parallel, the batch processing capacity of the CPU is fully utilized, and the communication speed between the CPU and the logic chip is improved.

Of course, it is not necessary for any product or method of the present application to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1-a is a signaling diagram of an uplink DMA process in the related art;

FIG. 1-b is a signaling diagram of a downstream DMA process in the related art;

FIG. 2 is a diagram illustrating data completion message misordering according to the related art;

fig. 3 is a first flowchart illustrating a message processing method according to an embodiment of the present application;

fig. 4 is a second flowchart of a message processing method according to an embodiment of the present application;

fig. 5 is a schematic diagram of a third flow of a message processing method according to an embodiment of the present application;

fig. 6 is a fourth flowchart illustrating a message processing method according to an embodiment of the present application;

fig. 7 is a fifth flowchart illustrating a message processing method according to an embodiment of the present application;

fig. 8 is a sixth flowchart illustrating a message processing method according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a message processing apparatus according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a logic chip according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the related art, according to the transmission direction of the packet, the communication between the CPU and the logic chip based on the PCIE protocol may be divided into: an uplink DMA process and a downlink DMA process. The uplink DMA process is that the logic chip sends a message to the CPU, and the downlink DMA process is that the CPU sends a message to the logic chip. For ease of understanding, reference is now made to FIGS. 1-a and 1-b. Fig. 1-a is a signaling diagram of an uplink DMA procedure in the related art. Fig. 1-b is a signaling diagram of a downlink DMA process in the related art.

As shown in fig. 1-a, in the uplink DMA process, a buffer space for message buffering is preset in the CPU. The CPU may store information of the Buffer space, such as address information of the Buffer space, in a designated memory in the form of a Buffer Descriptor (BD) message, and may transmit a pointer indicating a BD state to the logic chip. Wherein, the appointed memory is negotiated in advance by the CPU and the logic chip.

After receiving the pointer sent by the CPU, the logic chip may obtain BD information from the specified memory in the form of a read request according to the BD state indicated by the pointer. For example, the logic chip may Read BD information from a specified Memory by sending a PCIE Memory Read Request (PCIE Memory Read Request) to the CPU. And the logic chip caches the acquired BD information.

When the logic chip needs to send a message to the CPU, the logic chip may write the message into the cache space according to the cached BD information. For example, the logic chip may Write the message to be uploaded into the cache space in a form of a PCIE Memory Write Request (PCIE Memory Write Request). At this time, the logic chip may also update the BD status in the specified Memory in the form of a PCIE Memory Write Request.

The CPU may detect the BD status in a polling manner. When the BD state update is detected, the CPU may acquire the packet sent on the logic chip from the buffer space, and release the upper buffer space.

As shown in fig. 1-b, in the downlink DMA process, when the CPU needs to issue a message to the logic chip, the CPU may buffer the message to be issued into the buffer space. The CPU can store the message address and the message length in a specified memory in the form of BD information and send a pointer representing the BD state to the logic chip.

After receiving the pointer indicating the BD state, the logic chip may obtain BD information from the specified memory in the form of a read request according to the BD state indicated by the pointer. For example, the logic chip may Read BD information from a specified Memory in the form of a PCIE Memory Read Request. The logic chip may obtain the packet from the cache space in a form of a read request according to the BD information. For example, the logic chip may read, in the form of a PCIE read request, a message that needs to be issued by the CPU from the buffer space.

After the logic chip acquires the message, the BD state can be updated. For example, the logic chip may update the pointer indicating the BD state in the form of a PCIE Memory Write Request, and Write the pointer back to the specified Memory.

And after detecting the update of the BD state, the CPU recycles the cache space.

In the above uplink DMA process, the logic chip needs to send a read request for reading BD information to the CPU. In the above-mentioned downlink DMA process, the logic chip needs to send a read request for reading BD information and a request for reading a packet to the CPU. Therefore, in unit time, as the number of times of the read requests sent by the logic chip increases, the average rate of the data completion messages replied by the CPU for the received read requests is continuously increased, and the DMA efficiency is also increased. However, according to the PCIE protocol, the order of the data completion packets returned by the CPU is not necessarily consistent with the order in which the logic chip sends the read requests, that is, the data completion packets corresponding to multiple read requests may be out of order, and does not meet the requirement of the communication protocol on the packet order.

In addition, when the CPU replies to each received read request, because of the limitation of the PCIE maximum load (Max _ payload), a fragmentation phenomenon may occur in a data completion Packet corresponding to the read request, each fragment is a completed Transaction Layer Packet (TLP) Packet and is marked as a fragmentation Packet, and multiple fragmentation packets obtained by fragmentation may not be continuous. Therefore, TLPs corresponding to other read requests may be mixed in a data completion packet formed by a plurality of fragmented packets corresponding to the same read request. That is, the fragment packets corresponding to multiple read requests may also be out of order, and the requirement of the communication protocol on the packet order is not satisfied. For convenience of understanding, fig. 2 is an example to illustrate the disorder of the multiple fragmented packets, and fig. 2 is a schematic diagram of the disorder of data completion packets in the related art.

Fig. 2 only shows the fragmented packets generated during the period of completing packet generation corresponding to data in a certain read request, and the arrow direction indicates the sequence of the generation time of each fragmented packet from back to front. In fig. 2, CplD _ i _ j represents the j-th fragmentation message of CplD corresponding to the read request i. In fig. 2, for a read request, for example, all the fragmentation messages corresponding to request a include: CpLD _1_0, CpLD _1_1, and CpLD _1_ 2. During CpLD _1_0 to CpLD _1_2 generation, the CPU also generates slice messages for CpLD _ n (i.e., CpLD _ n _0 shown in fig. 2), CpLD _ m (i.e., CpLD _ m _0 and CpLD _ m _ k shown in fig. 2). Due to the fragmentation phenomenon and the generation period from CpLD _1_0 to CpLD _1_2, the CPU also generates corresponding data completion messages for other read requests, and after the CPU sends all generated fragmentation messages to the logic chip, the logic chip cannot accurately determine the data completion message corresponding to the request a, so that the requirement of the communication protocol on the message sequence is not met.

Therefore, in the related art, in order to ensure that the processing of the data completion packet can meet the requirement of the communication protocol on the packet sequence, after the CPU sends a read request to the logic chip, or after the logic chip sends a read request to the CPU, the next read request is sent only after the received data completion packet sent by the peer device. This reduces the number of read requests that are simultaneously processed by the CPU, resulting in an inability to fully utilize the batch processing capabilities of the CPU, limiting the communication rate between the CPU and the logic chip.

In order to solve the problem that the communication rate between a CPU and a logic chip is limited in the related art, the embodiment of the present application provides a message processing method. The method is applied to a logic chip, the logic chip is connected with a CPU through a PCIE protocol, the logic chip comprises a preset number of storage spaces, and each storage space has a corresponding label value. As shown in fig. 3, fig. 3 is a first flowchart illustrating a message processing method according to an embodiment of the present application. The method comprises the following steps.

Step S301, sending a plurality of read requests carrying tags to the CPU, so that the CPU feeds back a data completion packet carrying the tag included in each read request to the logic chip.

Step S302, receiving a data completion message carrying a label and fed back by the CPU.

Step S303, the received data completion packet is cached to a storage space corresponding to the value of the tag carried in the data completion packet.

Step S304, processing the data completion message in the storage space corresponding to the label included in each read request according to the sending sequence of the plurality of read requests.

In this embodiment, the logic chip may be a network card or other device communicatively connected to the CPU through a PCIE protocol. Here, the logic chip is not particularly limited.

By the method provided by the embodiment of the application, the logic chip adds the label in the read request, so that the data completion message responded by the CPU also carries the corresponding label. Different read requests and different tags are carried. After a received data completion message which is fed back by the CPU and carries a label is received, the received data completion message is stored in a storage space corresponding to the value of the label based on the label, so that the data completion message in the storage space corresponding to the label included in the read request is processed according to the sending sequence of the read request, the processing sequence of the data completion message is the same as the sequence of the read request, and the requirement of a communication protocol on the message sequence is met. Therefore, in the embodiment of the application, the logic chip can send a plurality of read requests carrying different tags in parallel, the batch processing capacity of the CPU is fully utilized, and the communication speed between the CPU and the logic chip is improved.

The following examples are given to illustrate the examples of the present application.

In step S301, a plurality of read requests carrying tags are sent to the CPU, so that the CPU feeds back a data completion packet carrying the tag included in each read request to the logic chip. The read request is a TLP.

In this step, when the logic chip needs to send a read request to the CPU, the logic chip may obtain the read request, allocate a corresponding tag to the read request, and send the read request carrying the tag to the CPU. After receiving a read request sent by a logic chip, the CPU may generate a data completion packet corresponding to the read request, where the data completion packet includes a tag carried by the read request.

The number of the data completion packets corresponding to each read request may be one or multiple. For example, when the CPU generates a data completion packet of a certain read request, if the fragmentation phenomenon occurs, the logic chip receives a plurality of fragment packets corresponding to the read request, where each fragment packet is a data completion packet, and all fragment packets together form a complete data completion packet corresponding to the read request. When the fragmentation phenomenon occurs, each fragmentation message carries a tag carried in a corresponding read request.

The logic chip may send one or more read requests at the same time when sending the read request to the CPU, and the above embodiment only takes the sending of one read request as an example for explanation. The transmission of a plurality of read requests is not specifically described herein with reference to the transmission of one read request.

In an optional embodiment, for the read request carrying the TAG, the TAG may be set in a message TAG (TAG) field of the read request. For each read request, the logic chip may add the TAG assigned to the read request to the message TAG field of the read request after determining the TAG. The TAG in the data completion message may also be set in the TAG field of the message. The tag assignment for each read request can be referred to the following description and will not be specifically described here.

The tag carried by each read request may be composed of numbers, letters, and the like, and the tag is not particularly limited. For convenience of description, the following description will be given only by using labels as numbers, and should not be construed as limiting in any way.

In step S302, the data completion packet with the tag fed back by the CPU is received. The data completion packet is a TLP.

In this embodiment of the present application, for each read request, because the data completion packet is fragmented when the CPU feeds back the data completion packet carrying the tag to the logic chip, the number of the data completion packets corresponding to the request received by the logic chip may be one or multiple. Here, the number of data completion packets corresponding to each read request received by the logic chip is not specifically limited.

In step S303, the received data completion packet is cached to the storage space corresponding to the value of the tag carried in the data completion packet.

In this step, the logic chip includes a storage space corresponding to the value of each tag. After the logic chip receives the data completion packet carrying the tag fed back by the CPU, the data completion packet may be cached in the storage space corresponding to the tag according to the tag carried in the data packet.

For the sake of understanding, the description will be made by taking the value of the label as the preset label value range [0, M-1 ].

The logic chip comprises M storage spaces, and the values of the tags correspond to the storage spaces one by one because the values of the tags have M values, namely 0 to M-1. Now, suppose that a data completion message with a label value of N is received by a logic chip at a certain time, and N is more than or equal to 0 and less than or equal to M-1. At this time, the logic chip may cache the data completion packet in the storage space corresponding to the tag with the value of N.

In this embodiment of the present application, for a data completion packet corresponding to the same read request, since a tag carried in the data completion packet is the same as a tag carried in the read request, even if the CPU generates a plurality of data completion packets, that is, the fragmentation packet, for a certain read request, at this time, tags carried in a plurality of data completion packets corresponding to the read request are also the same. Therefore, when the logic chip caches the received data completion messages in the storage space, the multiple data completion messages corresponding to the same read request can also be cached in the same storage space, so that the integrity of the data completion messages corresponding to the same read request and the accuracy of the sequence among the multiple data completion messages are effectively ensured.

The storage space may store the data completion packet in a form of a stack or a Random Access Memory (RAM). When the RAM is used for storage, the address information needs to be stored in the stack, so that the data can be conveniently processed in sequence in the later period.

In step S304, the data completion packet in the storage space corresponding to the tag included in each read request is processed according to the sending sequence of the plurality of read requests.

In this step, after the logic chip stores the received data completion message in the storage space corresponding to the value of the tag, the logic chip starts to process the data completion message in each storage space. Because each received data completion message carries the label carried in the corresponding read request, the logic chip can determine the processing sequence corresponding to the data completion message in each storage space according to the sending sequence of each read request, and sequentially process the data completion messages stored in each storage space according to the processing sequence, thereby ensuring the consistency of the processing sequence of the data completion messages and the sending sequence of the corresponding read requests.

In the embodiment of the present application, the logic chip may perform corresponding processing on the data packet according to different packet information carried in the data completion packet. For example, the message information carried in the data completion message received by the logic chip is data issued by the CPU, and at this time, the logic chip may forward the data completion message, or store the data in the data completion message. For another example, the message information carried in the data completion message received by the logic chip is the pointer indicating the BD information, and at this time, the logic chip may send the PCIE Memory Read Request to the CPU according to the pointer in the data completion message. Here, the above-mentioned treatment process is not particularly limited.

In an optional embodiment, according to the method shown in fig. 3, an embodiment of the present application further provides a message processing method. As shown in fig. 4, fig. 4 is a second flowchart of the message processing method according to the embodiment of the present application. In fig. 4, the step S301, that is, the step of sending a plurality of tag-carrying read requests to the CPU, is subdivided into the following steps S3011 to S3013.

Step S3011, for each read request carrying a tag, detecting whether there is a token in a preset token bucket. If yes, go to step S3012. If not, step S3011 is executed again.

In this step, before sending the read request carrying the tag to the CPU, the logic chip may detect the number of tokens included in the preset token bucket, thereby determining whether there is a token in the preset token bucket. If the detection result is yes, that is, there are tokens in the preset token bucket, the logic chip may execute step S3012.

If the detection result is negative, that is, there is no token in the preset token bucket, the logic chip re-executes step S3011.

In this embodiment, the logic chip may use a stack or a queue as a predetermined token bucket for storing tokens. The preset token bucket may include a preset number of tokens.

In an optional embodiment, since the number of tokens included in the preset token bucket is a preset number, the number of tokens included in the preset token bucket is limited. Besides executing step S3012 and step S3013, the logic chip may also recycle the taken tokens, thereby ensuring orderly use of the tokens. Therefore, when detecting that there are no tokens in the preset token bucket, the logic chip may re-execute the step S3011. That is, whether there is a token in the preset token bucket is re-detected, until there is a token in the preset token bucket, step S3012 is executed. For recycling of tokens, reference is made to the description below, which is not specifically described here.

In another alternative embodiment, when it is detected that there is no token in the preset token bucket, the logic chip may further wait for a preset time period and then re-execute the step S3011.

The preset number may be set according to a user requirement or a batch processing capability of the CPU for the read request, and is not specifically described herein.

Step S3012, the token is taken out from the preset token bucket.

In this step, when there are tokens in the preset token bucket, the logic chip may take out one token from the preset token bucket as a token of the read request for each read request that needs to be sent to the CPU.

Step S3013, according to the extracted token, sends the read request with the tag to the CPU.

In this step, for each read request, after determining that the read request has a corresponding token, the logic chip may send the read request carrying the tag to the CPU.

In this embodiment of the present application, for each read request, the step of obtaining the token corresponding to the read request may be before the step of allocating the tag carried in the read request, or may be after the step of allocating the tag carried in the read request. Here, the execution order of the token acquisition and the label assignment is not particularly limited.

Through the steps S3011 to S3013, the logic chip can ensure that the number of the read requests sent to the CPU in a certain time period is less than or equal to the preset number, thereby ensuring that the CPU processes the read requests in batch, effectively controlling the number of the read requests processed by the CPU, and ensuring stable operation of the CPU.

In an optional embodiment, according to the method shown in fig. 4, an embodiment of the present application further provides a message processing method. As shown in fig. 5, fig. 5 is a third flowchart illustrating a message processing method according to an embodiment of the present application. The method adds step S305.

Step S305, when a data completion packet corresponding to a read request is processed, a token is generated, and the generated token is added to a preset token bucket.

In this step, when the logic chip processes the received data packet, the logic chip may generate a token and add the token to the preset token bucket every time the logic chip processes a data completion packet corresponding to one read request.

The generation of the token may be represented as generating a new token or as recycling an original token.

In an optional embodiment, for the case of generating a new token, when the logic chip processes a token corresponding to a read request, the logic chip may regenerate a new token and add the token to the preset token bucket.

In another optional embodiment, for the case of recycling the original token, when the logic chip executes the step S3012, that is, when the token is taken out from the preset token bucket, the logic chip may locally record the corresponding relationship between the read request sent to the CPU and the token. When the logic chip processes a data completion message corresponding to a certain read request, a token corresponding to the read request can be determined according to the corresponding relationship, and the token is added to the preset token bucket again.

In the embodiment of the present application, the generation manner of the token is not particularly limited.

Through the step S303, the logic chip can guarantee the effective circulation of the tokens in the preset token bucket while guaranteeing that the number of the tokens in the preset token bucket is less than or equal to the preset number, that is, the number of the transmittable read requests, so as to guarantee the orderliness and stability of the transmission of the read requests.

In an optional embodiment, according to the method shown in fig. 3, an embodiment of the present application further provides a message processing method. As shown in fig. 6, fig. 6 is a fourth flowchart illustrating a message processing method according to an embodiment of the present application. The method comprises the following steps.

Step S601, when a read request is acquired, adding a tag to the read request, and adding 1 to the value of the tag.

In this step, after the logic chip obtains the read request that needs to be sent to the CPU, the current tag may be added to the read request to obtain the read request carrying the tag. At this time, the logic chip may also add 1 to the value corresponding to the current tag.

In step S602, when the value of the tag is the maximum value of the tag, the value of the tag is updated to 0.

In this step, after the logic chip executes the above step S601, it may further determine whether the current value of the tag, i.e., the value of the tag after being added with 1, is equal to the maximum value of the tag. If the current tag value is equal to the maximum value of the tag, the logic chip may update the tag value to 0.

In the embodiment of the present application, the label may be any value within a preset label value range. For ease of understanding, the predetermined tag value range is illustrated as [0, M-1], i.e., the tag may be any one of M values from 0 to M-1. At this time, the maximum value of the tag is M.

Now, suppose that a read request is acquired at a certain time, the current value of the TAG is N, and the logic chip may assign N to the read request and add N to the TAG field of the message of the read request. At this time, the logic chip may update the value of the current tag to N + 1. After the logic chip obtains the next read request, N +1 may be allocated to the tag, and the current value of the tag is updated to N + 2.

At a certain time, if the current tag value is equal to the maximum value of the tag, for example, N +5 equals M, the logic chip may update the current tag value to 0, and allocate the tag, that is, 0, to the next acquired read request. And by analogy, updating the value of the label is completed.

Through the steps S601 to S602, the logic chip may allocate a corresponding tag to each obtained read request, so that the uniqueness of the tag carried in the packet sent by the logic chip to the CPU within a certain time range is ensured, and the data completion packet carrying the tag is processed by the logic chip in the later period according to the sending sequence of the read request, that is, the communication rate between the CPU and the logic chip is increased, and the ordering of the data completion packet processing by the logic chip is ensured.

In this embodiment of the application, the number of the numerical values included in the preset tag value range is greater than the preset number, that is, the number of the numerical values included in the preset tag value range is preset to the number of tokens included in the token bucket. For example, the preset number may be 32, and the preset tag value range may be [0,255], that is, the number of values included in the preset tag value range is 256. The number of values included in the preset tag value range may be a multiple of 8 according to the characteristics of bytes in the message.

In one example, to facilitate management of the tags, the number of values included in the preset tag value range is a multiple of the preset number.

Step S603, sending a plurality of read requests carrying tags to the CPU, so that the CPU feeds back a data completion packet carrying the tag included in each read request to the logic chip.

Step S604, receiving the data completion message carrying the label fed back by the CPU.

Step S605, the received data completion packet is cached to the storage space corresponding to the value of the tag carried by the data completion packet.

Step S606, according to the sending sequence of the multiple read requests, processing the data completion packet in the storage space corresponding to the tag included in each read request.

The above steps S603 to S606 are the same as the above steps S301 to S304.

In an optional embodiment, the logic chip may include a preset variable and a preset number of storage spaces, a value of each tag corresponds to one storage space, a maximum value of the preset variable is the preset number, and the values of the preset variable correspond to the storage spaces one to one. According to the method shown in fig. 3, an embodiment of the present application further provides a message processing method. As shown in fig. 7, fig. 7 is a fifth flowchart illustrating a message processing method according to an embodiment of the present application. The method comprises the following steps.

Step S701, sending a plurality of read requests carrying tags to the CPU, so that the CPU feeds back a data completion packet carrying the tag included in each read request to the logic chip.

Step S702, receiving a data completion message carrying a label fed back by the CPU.

Step S703 is to cache the received data completion packet to a storage space corresponding to the value of the tag carried in the data completion packet.

The steps S701 to S703 are the same as the steps S301 to S303.

Step S704, the data completion packet stored in the storage space corresponding to the value of the preset variable is processed, and 1 is added to the value of the preset variable.

In this step, the values of the preset variables included in the logic chip correspond to the preset stores one to one. Therefore, the processing of the data completion packet carrying the label included in each read request according to the sending sequence of the plurality of read requests may be specifically represented as: and processing the data completion message stored in the storage space corresponding to the value of the preset variable, and adding 1 to the value of the preset variable, so as to continuously process the data completion message stored in the storage space corresponding to the value of the preset variable after adding 1. And the rest is done in sequence to finish the processing process of the message on the data stored in the storage space.

In step S705, when the value of the preset variable is the preset number, the value of the preset variable is updated to 0.

The updating process of the value of the preset variable may refer to the updating process of the value of the tag, and is not specifically described herein.

In this embodiment of the application, since the number of tokens included in the preset token bucket is the preset number, and the update mode of the value of the preset variable matches the update mode of the value of the tag, the logic chip can completely reflect the sending sequence of the read request corresponding to the data completion packet stored in each storage space through the update of the value of the preset variable, which can effectively ensure the orderliness of the data completion packet processing stored in the storage space.

In an optional embodiment, the length of the storage space is a preset multiple of the length of the maximum data completion packet of the read request. For example, the length of the storage space is 2 times or 3 times the length of the maximum data completion packet of the read request.

There is a delay in the processing of the data completion message. When the data completion message of one read request stored in the storage space is not processed, the logic chip is likely to receive the data completion messages of other read requests stored in the storage space. In the embodiment of the application, the length of the storage space is a preset multiple of the length of the maximum data completion message of the read request, so that the problem that the data completion message stored in the storage space is not processed and completed and the data completion messages of other read requests are received is effectively solved, the waiting time caused by the problem is avoided, and the communication rate between the CPU and the logic chip is further improved.

In an optional embodiment, when the CPU generates the data completion packet corresponding to each read request, a fragmentation phenomenon may occur, so that the number of data completion packets of a certain read request is multiple. Therefore, the data completion message may be a fragment message. According to the method shown in fig. 7, an embodiment of the present application further provides a message processing method. As shown in fig. 8, fig. 8 is a sixth flowchart illustrating a message processing method according to an embodiment of the present application. Specifically, step S704 is subdivided into steps S7041 to S7042.

Step S7041, it is detected whether a last data completion packet is stored in the storage space corresponding to the value of the preset variable, where the last data completion packet is a last packet in the data completion packets carrying the read request of the tag corresponding to the storage space. If yes, go to step S7042; if not, the process continues to step S7041.

In order to ensure the ordering and timeliness of the data completion message processing, the logic chip needs to detect whether the last fragment message is stored in the storage space corresponding to the value of the preset variable, that is, the last data completion message in the storage space corresponding to the value of the preset variable. If the last data completion message is stored, the logic chip may determine that the complete data completion message corresponding to the read request is stored in the storage space, and execute step S7042 to process the complete data completion message corresponding to the read request stored in the storage space.

In an optional embodiment, when detecting the last data completion packet in the storage space corresponding to the value of the preset variable, the logic chip may obtain, for each fragment packet stored in the storage space, a packet Length (Length) and a Byte Count (that is, Byte Count) of the fragment packet, and determine, according to the obtained Length and Byte Count, the last data completion packet in the storage space corresponding to the value of the preset variable. If the Length of one fragment message is less than or equal to the Byte Count, the fragment message is determined to be the last fragment message, namely the last data completion message.

The Length is 4 bytes, for example, 4 bytes corresponds to a Length value of 1, and 10 bytes corresponds to a Length value of 3. The Byte Count is in units of 1 Byte.

In this embodiment, the logic chip may also determine the last data completion packet in other manners. For example, the last data completion packet carries an identifier indicating that the last data completion packet is the last data completion packet. This is not limitative.

In an optional embodiment, in order to ensure timeliness of processing a data completion packet and solve a computational resource, when the data completion packet is stored in the storage space corresponding to the value of the preset variable, the logic chip executes the step S7041 to detect whether the data completion packet is a last data completion packet.

In another alternative embodiment, when the value of the preset variable is updated, the logic chip executes the step S7041 to detect whether the last stored packet in the storage space corresponding to the value of the preset variable is the last data completion packet.

Step S7042, the data completion packet stored in the storage space is processed, and the value of the preset variable is incremented by 1.

In this step, after detecting that the last data completion packet is stored in the storage space corresponding to the value of the preset variable, the logic chip may determine that the complete data completion packet corresponding to the read request is stored in the storage space, process the complete data completion packet corresponding to the read request stored in the storage space, and add 1 to the preset variable.

Through the steps S7041 to S7042, the logic chip can ensure that the data completes the ordered output of the message.

Based on the same inventive concept, according to the message processing method provided in the embodiment of the present application, the embodiment of the present application further provides a message processing apparatus. As shown in fig. 9, fig. 9 is a schematic structural diagram of a message processing apparatus according to an embodiment of the present application. The device is applied to a logic chip, the logic chip is connected with a CPU through a PCIE protocol, the logic chip comprises a preset number of storage spaces, and each storage space has a corresponding label value. The device comprises the following modules:

a sending module 901, configured to send multiple read requests carrying tags to a CPU, so that the CPU feeds back a data completion packet carrying a tag included in each read request to a logic chip;

a receiving module 902, configured to receive a data completion packet carrying a tag and fed back by a CPU;

a caching module 903, configured to cache the received data completion packet to a storage space corresponding to a value of a tag carried in the data completion packet;

the processing module 904 is configured to process, according to the sending sequence of the multiple read requests, a data completion packet in a storage space corresponding to a tag included in each read request.

Optionally, the sending module 901 may be specifically configured to detect whether there is a token in a preset token bucket for each read request carrying a tag, where the preset token bucket includes a preset number of tokens; if yes, taking out the token from a preset token bucket; and sending the read request carrying the label to the CPU according to the taken token.

Optionally, the message processing apparatus may further include:

and the first adding module is used for generating a token when processing a data completion message corresponding to a read request and adding the generated token into a preset token bucket.

Optionally, the message processing apparatus may further include:

and the first updating module is used for updating the value of the label to be 0 when the value of the label is the maximum value of the label.

Optionally, the logic chip may include preset variables, a maximum value of the preset variables is a preset number, and values of the preset variables correspond to the storage spaces one to one;

the processing module may be specifically configured to process a data completion packet stored in a storage space corresponding to a value of a preset variable, and add 1 to the value of the preset variable; and updating the value of the preset variable to 0 when the value of the preset variable is a preset number.

Optionally, the data completion message may be a fragment message;

the processing module 904 may be specifically configured to detect whether a last data completion packet is stored in a storage space corresponding to a value of a preset variable, where the last data completion packet is a last packet in a data completion packet of a read request carrying a tag corresponding to the storage space; and if so, processing the data completion message stored in the storage space, and adding 1 to the value of the preset variable.

Optionally, the length of the storage space may be a preset multiple of the length of the maximum data completion packet of the read request.

Through the device provided by the embodiment of the application, the logic chip adds the label in the read request, so that the data completion message responded by the CPU also carries the corresponding label. Different read requests and different tags are carried. After a received data completion message which is fed back by the CPU and carries a label is received, the received data completion message is stored in a storage space corresponding to the value of the label based on the label, so that the data completion message in the storage space corresponding to the label included in the read request is processed according to the sending sequence of the read request, the processing sequence of the data completion message is the same as the sequence of the read request, and the requirement of a communication protocol on the message sequence is met. Therefore, in the embodiment of the application, the logic chip can send a plurality of read requests carrying different tags in parallel, the batch processing capacity of the CPU is fully utilized, and the communication speed between the CPU and the logic chip is improved.

Based on the same inventive concept, according to the message processing method provided in the embodiment of the present application, the embodiment of the present application further provides a logic chip, as shown in fig. 10, including a processor 1001 and a machine-readable storage medium 1002, where the machine-readable storage medium 1002 stores machine-executable instructions that can be executed by the processor 1001. Processor 1001 is caused by machine executable instructions to implement any of the steps shown in fig. 3-8 described above.

In an alternative embodiment, as shown in fig. 10, the logic chip may further include: a communication interface 1003 and a communication bus 1004; the processor 1001, the machine-readable storage medium 1002, and the communication interface 1003 complete communication with each other through the communication bus 1004, and the communication interface 1003 is used for communication between the logic chip and other devices.

Based on the same inventive concept, according to the message processing method provided in the embodiment of the present application, an embodiment of the present application further provides a machine-readable storage medium, where a machine-executable instruction capable of being executed by a processor is stored in the machine-readable storage medium. The processor is caused by machine executable instructions to implement any of the steps shown in fig. 3-8 described above.

The communication bus may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

The machine-readable storage medium may include a RAM (Random Access Memory) and a NVM (Non-Volatile Memory), such as at least one disk Memory. Additionally, the machine-readable storage medium may be at least one memory device located remotely from the aforementioned processor.

The Processor may be a general-purpose Processor including a CPU, an NP (Network Processor), and the like; but also DSPs (Digital Signal Processing), ASICs (Application Specific Integrated circuits), FPGAs (Field Programmable Gate arrays) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments of the message processing apparatus, the logic chip, the machine-readable storage medium, and the like, since they are basically similar to the embodiments of the message processing method, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the embodiments of the message processing method.

The above description is only for the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A message processing method is characterized in that the method is applied to a logic chip, the logic chip is connected with a Central Processing Unit (CPU) through a Peripheral Component Interconnect Express (PCIE) protocol, the logic chip comprises a preset number of storage spaces, and each storage space has a corresponding label value, and the method comprises the following steps:

receiving a data completion message carrying a label and fed back by the CPU;

2. The method of claim 1, wherein the step of sending a plurality of tag-bearing read requests to the CPU comprises:

if yes, taking out the token from the preset token bucket;

3. The method of claim 2, further comprising:

4. The method according to claim 3, wherein the logic chip comprises preset variables, the maximum value of the preset variables is the preset number, and the values of the preset variables correspond to storage spaces one to one;

5. The method of claim 4, wherein the data completion packet is a fragmentation packet;

6. The method according to claim 4 or 5, wherein the length of the storage space is a preset multiple of the length of a maximum data completion packet of the read request.

7. The utility model provides a message processing apparatus which characterized in that is applied to the logic chip, the logic chip passes through peripheral component fast interconnect PCIE protocol with central processing unit CPU and connects, the logic chip includes a predetermined number of memory space, and each memory space has the value of corresponding label, the device includes:

8. The apparatus according to claim 7, wherein the sending module is specifically configured to detect, for each read request carrying a tag, whether there is a token in a preset token bucket, where the preset token bucket includes a preset number of tokens; if yes, taking out the token from the preset token bucket; sending the read request carrying the label to the CPU according to the taken token;

the device further comprises:

9. The apparatus of claim 8, further comprising:

10. The apparatus according to claim 9, wherein the logic chip comprises preset variables, a maximum value of the preset variables is the preset number, and values of the preset variables correspond to storage spaces one to one;

11. The apparatus according to claim 10, wherein the data completion packet is a fragmentation packet;

12. The apparatus according to claim 10 or 11, wherein the length of the storage space is a preset multiple of the length of a maximum data completion packet of the read request.

13. A logic chip comprising a processor and a machine-readable storage medium storing machine-executable instructions executable by the processor, the processor being caused by the machine-executable instructions to: carrying out the method steps of any one of claims 1 to 6.

14. A machine-readable storage medium having stored thereon machine-executable instructions executable by the processor, the processor being caused by the machine-executable instructions to: carrying out the method steps of any one of claims 1 to 6.