CN112947287A - Control method, controller and electronic equipment - Google Patents
Control method, controller and electronic equipment Download PDFInfo
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- CN112947287A CN112947287A CN202110335237.5A CN202110335237A CN112947287A CN 112947287 A CN112947287 A CN 112947287A CN 202110335237 A CN202110335237 A CN 202110335237A CN 112947287 A CN112947287 A CN 112947287A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1103—Special, intelligent I-O processor, also plc can only access via processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Abstract
The application discloses a control method, a controller and an electronic device, wherein the method comprises the following steps: under the condition that a first device and at least one second device are respectively connected to a controller, the controller receives a connection instruction transmitted by the first device; the controller establishes a data connection between the first device and a target device at least according to the connection instruction, the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device; the controller is a single programmable logic circuit component and can transmit data to the first equipment.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a control method, a controller, and an electronic device.
Background
Currently, in a backplane supporting NVME (Non-Volatile Memory express), at least three types of chips are required: a control chip, a device information chip and an I2C expansion chip.
The control chip is usually a complex programmable logic device cpld (complex Programming logic device), a programmable System single chip psoc (Programming System on chip), a single-chip microcomputer SCM (single-chip microcomputer) or a micro control unit mcu (micro controller unit), etc., and the control chip is used as a logic processing unit on the backplane and performs information interaction with a main controller on the main board; the device information chip is usually a charged Erasable Programmable read only memory (eeprom) for storing contents such as a product serial number and description information; in addition, the I2C expansion chip is used for expanding the single-channel I2C bus of the master into multiple channels, and is respectively connected to the I2C interfaces on the NVME hard disks so as to realize data transmission with the hard disks.
However, limited backplane space, there is a need to reduce the number of chips on the backplane.
Disclosure of Invention
In view of the above, the present application provides a control method, a controller and an electronic device, as follows:
a control method, comprising:
under the condition that a first device and at least one second device are respectively connected to a controller, the controller receives a connection instruction transmitted by the first device;
the controller establishes a data connection between the first device and a target device at least according to the connection instruction, the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device;
the controller is a single programmable logic circuit component and can transmit data to the first equipment.
In the above method, preferably, the controller is in data connection with the first device through a first port, and the controller is in data connection with the second devices through second ports, where one of the second ports corresponds to one of the second devices;
wherein the method further comprises:
and under the condition that the controller detects a low-level signal on the first port, the controller sets the first port to be in an input state and sets a target port connected to the target device in the second port to be in an output state, so that the first device transmits first data to the target device through the data connection.
The above method, preferably, further comprises:
and when the controller detects that the signal changes from a low level signal to a high level signal on the first port, the controller sets the first port to be in an output state and sets the target port to be in an input state, so that the first device receives second data transmitted by the target device through the data connection.
In the above method, preferably, the controller is in data connection with the first device through a first port, and the controller is in data connection with the second devices through second ports, where one of the second ports corresponds to one of the second devices;
wherein the method further comprises:
and under the condition that the controller detects a low-level signal on a target port connected to the target equipment in the second port, the controller sets the target port to be in an input state and sets the first port to be in an output state, so that the first equipment receives second data transmitted by the target equipment through the data connection.
The above method, preferably, further comprises:
and when the controller detects that the signal changes from a low level signal to a high level signal on the second port, the controller sets the target port to be in an output state and sets the first port to be in an input state, so that the first device transmits first data to the target device through the data connection.
In the above method, preferably, the setting, by the controller, the first port to the input state includes:
the controller sets the first port to be in a high-resistance state;
wherein the controller sets the target port to an output state, including:
the controller sets the target port to a low state.
In the above method, preferably, the setting, by the controller, the first port to the output state includes:
the controller sets the first port to be in a low level state;
wherein the controller sets the target port to an input state, including:
the controller sets the target port to be in a high impedance state.
The above method, preferably, further comprises:
the controller receives an information access instruction transmitted by the first equipment;
the controller accesses the target information corresponding to the information access instruction in a target area to obtain an access result; the target area is a storage area divided in the controller.
A controller, comprising:
the device comprises a first port and at least one second port, wherein the first port is used for connecting a first device, and the second port is used for connecting a second device;
the method comprises the steps that under the condition that a first device and at least one second device are connected to a controller respectively, the controller receives a connection instruction transmitted by the first device, and establishes data connection between the first device and a target device at least according to the connection instruction, wherein the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device;
the controller is a single programmable logic circuit component and can transmit data to the first equipment.
An electronic device, comprising:
a controller, a first device and at least one second device;
the method comprises the steps that under the condition that a first device and at least one second device are connected to a controller respectively, the controller receives a connection instruction transmitted by the first device, and establishes data connection between the first device and a target device at least according to the connection instruction, wherein the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device;
the controller is a single programmable logic circuit component and can transmit data to the first equipment.
According to the control method, the controller and the electronic device, a function of realizing data transmission between the master device and the slave device is integrated into a single programmable logic circuit component, namely the controller, so that data transmission between the controller and the master device can be realized, and data transmission between the master device and the slave device can also be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a control method according to an embodiment of the present application;
FIGS. 2-4 are diagrams illustrating examples of applications of embodiments of the present application;
fig. 5 is another flowchart of a control method according to an embodiment of the present application;
FIG. 6 is a diagram illustrating another exemplary application of an embodiment of the present application;
fig. 7 is another flowchart of a control method according to an embodiment of the present application;
FIG. 8 is a diagram illustrating another exemplary application of an embodiment of the present application;
fig. 9-10 are respectively another flow charts of a control method according to an embodiment of the present application;
fig. 11 is a partial flowchart of a control method according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of a controller according to a second embodiment of the present application;
fig. 13 is a schematic structural diagram of an electronic device according to a third embodiment of the present application;
FIG. 14 is a schematic structural diagram of a back plate in the prior art;
FIG. 15 is a schematic structural diagram of a control chip suitable for use in the backplane design of the present application;
FIG. 16 is a schematic diagram of a logic structure of an I2C expansion chip implemented by a control chip suitable for backplane design according to the present application;
fig. 17 is a schematic diagram of a logic structure of FRU storage implemented by a control chip suitable for backplane design according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, a flowchart of an implementation of a control method provided in an embodiment of the present application is provided, where the method may be applied to a controller capable of performing data processing and data transmission, where the controller is a single programmable logic circuit component, such as a CPLD, a PSOC, an SCM, or an MCU. The technical scheme in the embodiment is mainly used for reducing the number of chips in the electronic equipment so as to reduce the pressure on the space occupation of the electronic equipment.
Specifically, the method in this embodiment may include the following steps:
step 101: under the condition that a first device and at least one second device are respectively connected to the controller, the controller receives a connection instruction transmitted by the first device.
The first device may be a master device with respect to the controller, such as a baseboard Management controller bmc (baseboard Management controller) or the like as a master in the electronic device, and the second device may be a slave device with respect to the controller, such as an NVME hard disk or the like in the electronic device. When there are a plurality of second devices, the plurality of second devices may be all devices of the same type or different types, but all devices may be connectable to the controller.
Specifically, in this embodiment, the controller may implement data transmission with the first device, for example, the controller may implement data transmission with the first device through an Inter-Integrated Circuit (I2C bus). The controller and the second device may be connected through an I2C bus, as shown in fig. 2. Based on this, the controller in this embodiment receives the connection command transmitted from the first device through the I2C bus.
It should be noted that the connection instruction transmitted by the first device is at least used to indicate the second device to which the first device needs to connect, so as to facilitate data transmission between the first device and the second device indicated by the connection instruction. Specifically, the connection instruction may include a device identifier of the second device to which the first device needs to be connected, such as a device name, a device address, a device serial number, and other information that can uniquely characterize the second device.
Step 102: the controller establishes a data connection between the first device and the target device at least according to the connection instruction.
The target device is a device corresponding to the connection instruction in the second device connected to the first device, and the data connection established by the controller is used for realizing data transmission between the first device and the target device.
In one implementation, after receiving the connection instruction, the controller determines, according to the device identifier included in the connection instruction, a target device indicated by the connection instruction among one or more second devices connected to the first device, as shown in fig. 3, based on which the controller establishes a data connection between the first device and the target device, and based on the data connection, data transmission between the first device and the target device is possible.
Specifically, the controller is connected to the first device through a first port, the first port may be a port of an I2C bus, the controller is connected to the second device through a second port, the second port may be a port of an I2C bus, and there may be a plurality of second ports on the controller, one port corresponding to one second device, and each second port is used for connecting to a corresponding second device, as shown in fig. 4.
Based on this, after the controller receives the connection instruction, based on the routing configuration between the first port and the second port, the controller determines, according to the device identifier included in the connection instruction, a target port of the target device, which is a second device corresponding to the device identifier, on the plurality of second ports connected to the controller, and then connects the bus between the first port and the target port, that is, conducts the connection of the bus connection, i.e., the I2C bus, between the first port and the target port, and establishes the data connection between the first port and the target port, thereby establishing the data connection between the first device and the target device, and based on this, data transmission between the first device and the target device can be achieved through the established data connection.
It should be noted that after the controller determines the target port corresponding to the connection instruction, there may be two cases: in one case, the target port is already connected with the first port through a bus, and at this time, the controller only needs to establish data connection between the target port and the first port; in another case, the target port is disconnected from the first port, and the first port may have a bus connection with another second port, at this time, the controller first establishes the bus connection between the target port and the first port, and then establishes the data connection between the first port and the target port.
It can be seen from the foregoing solutions that, in the control method provided in the first embodiment of the present application, the function of implementing data transmission between the master device and the slave device is integrated onto a single programmable logic circuit component, that is, a controller, so that data transmission between the controller and the master device can be implemented, and data transmission between the master device and the slave device can also be implemented at the same time.
Based on the port diagram shown in fig. 4, the controller may implement data connection with the first device through the first port, and implement data connection with the second device through the second port. In a specific implementation, when data transmission is performed between the first device and the target device, a specific data transmission direction may be controlled by detecting a change in a signal level on the port, and in an implementation manner, the control on the data transmission may be implemented by using the first port as a detected port; in another implementation manner, the second port may be a detected port to implement control of data transmission. The method comprises the following specific steps:
in an implementation manner, after the controller establishes the data connection between the first device and the target device in this embodiment, the method in this embodiment may further include the following steps, as shown in fig. 5:
step 103: the controller sets the first port to an input state and sets a target port connected to the target device in the second port to an output state under the condition that the controller detects a low-level signal on the first port, so that the first device transmits first data to the target device through data connection.
The low-level signal may be a ground signal or a signal lower than a first level threshold, the low-level signal being relative to the high-level signal, and the high-level signal being a signal with a level higher than the corresponding first level threshold. In this embodiment, the controller monitors the signal level at the first port in real time, and when detecting that a low level signal is present at the first port, the first port is characterized as an input end in data transmission between the first device and the target device, where the input is an input from the first device to the controller side with respect to the controller.
Based on this, when the controller detects a low-level signal on the first port, the controller may determine that the first port is an input port in data transmission, and accordingly, may determine that a target port connected to the target device in the second port is an output port in data transmission, at this time, the controller sets the first port to an input state and sets the target port to an output state, based on which, the first device may transmit the first data to the target device through the data connection between the first port and the target port.
In particular, the controller may set the first port in a high impedance state, such as a state with a level above a second level threshold, such that the first port is set to an input state; meanwhile, the controller may set the target port to a low state, such as a ground state or a state in which the level is lower than a second level threshold, so that the target port is set to an output state.
For example, when the CPLD is connected to the BMC through the port a and connected to the NVME hard disk 2 through the port B, and data transmission is performed between the BMC and the NVME2 through data connection between the port a and the port B, if the CPLD detects a low level at the port a, it is determined that the BMC on the port a side is to perform data output, and at this time, the CPLD sets the port a in a high impedance state and pulls down the level of the port B or grounds the port B, so that the BMC on the port a side can transmit first data to the NVME hard disk 2 on the port B side, as shown in fig. 6.
Further, after step 103, the method in this embodiment may further include the following steps, as shown in fig. 7:
step 104: when the controller detects that the first port changes from a low-level signal to a high-level signal, the controller sets the first port to be in an output state and sets the target port to be in an input state, so that the first device receives second data transmitted by the target device through data connection.
That is, after the controller sets the first port to the input state and sets the target port to the output state, the controller continues to monitor the signal level on the first port in real time, and if it is monitored that the first port is still a low-level signal, the controller continues to maintain the first port in the input state and maintain the target port in the output state, and in a case where a change from the low-level signal to the high-level signal on the first port is detected, the controller indicates that the first port has been switched to the output terminal in data transmission between the first device and the target device, where the output is an output from the controller to the first device.
Based on this, when the controller detects that the signal changes from the low level signal to the high level signal on the first port, the controller may determine that the first port is an output end in data transmission, and accordingly, may determine that a target port connected to the target device in the second port is an input end in data transmission, at this time, the controller sets the first port to an output state and sets the target port to an output state, and based on this, the target device may transmit the second data to the first device through the data connection between the first port and the target port.
Specifically, the controller may set the first port to a low level state, such as a ground state or a state in which the level is lower than a second level threshold, so that the first port is set to an output state; meanwhile, the controller may set the target port to a high impedance state, such as a state with a level above a second level threshold, such that the target port is set to an input state.
For example, when the CPLD is connected to the BMC through the port a and connected to the NVME hard disk 2 through the port B, and data transmission is performed between the BMC and the NVME2 through data connection between the port a and the port B, if the CPLD detects that the level changes from low to high at the port a, it is determined that the NVME hard disk 2 on the port B side is to perform data input and the BMC on the port a side is to perform data reception, and at this time, the CPLD sets the port B in a high impedance state and pulls the port a low or grounds the port a, so that the BMC on the port a side can receive the second data transmitted by the NVME hard disk 2 on the port B side, as shown in fig. 8.
In another implementation manner, after the controller establishes the data connection between the first device and the target device in this embodiment, the method in this embodiment may further include the following steps, as shown in fig. 9:
step 105: and under the condition that the controller detects a low-level signal on a target port connected to the target equipment in the second port, the controller sets the target port to be in an input state and sets the first port to be in an output state, so that the first equipment receives second data transmitted by the target equipment through data connection.
That is, in this embodiment, the controller monitors the signal level at the destination port in real time, and when detecting that a low-level signal appears at the destination port, the destination port is characterized as an input end in data transmission between the first device and the destination device, where the input is an input from the destination device to the controller side with respect to the controller.
Based on this, when the controller detects a low level signal on the target port, the controller may determine that the target port is an input end in data transmission, and correspondingly, may determine that the first port is an output end in data transmission, at this time, the controller sets the target port to an input state and sets the first port to an output state, and based on this, the first device may receive second data transmitted by the target device through a data connection between the first port and the target port.
Specifically, the controller may set the target port in a high impedance state, such as a state with a level higher than a second level threshold, so that the target port is set in an input state; meanwhile, the controller may set the first port to a low level state, such as a ground state or a state in which the level is lower than a second level threshold, so that the first port is set to an output state.
For example, when the CPLD is connected to the BMC through the port a and connected to the NVME hard disk 2 through the port B, and data transmission is performed between the BMC and the NVME2 through data connection between the port a and the port B, if the CPLD detects a low level at the port B, it is determined that the NVME hard disk 2 on the port B side is to perform data output, and at this time, the CPLD sets the port B in a high impedance state and pulls down the level of the port a or grounds the port a, so that the NVME hard disk 2 on the port B side can transmit the second data to the BMC on the port a side, as shown in fig. 8.
Further, after step 105, the method in this embodiment may further include the following steps, as shown in fig. 10:
step 106: when the controller detects that the second port changes from a low-level signal to a high-level signal, the controller sets the target port to be in an output state and sets the first port to be in an input state, so that the first device transmits first data to the target device through the data connection.
That is, after the controller sets the target port to the input state and sets the first port to the output state, the controller continues to monitor the signal level on the target port in real time, if it is monitored that the target port is still a low-level signal, the controller continues to maintain the target port in the input state and maintain the first port in the output state, and in the case that a change from the low-level signal to a high-level signal on the target port is detected, the controller side is an output to the target device, which represents that the target port has been switched to an output end in data transmission between the first device and the target device.
Based on this, when the controller detects that the target port changes from a low level signal to a high level signal, the controller may determine that the target port is an output end in data transmission, and accordingly, may determine that the first port is an input end in data transmission, at this time, the controller sets the target port to an output state and sets the first port to an output state, and based on this, the target device may receive the first data transmitted by the first device through the data connection between the first port and the target port.
Specifically, the controller may set the target port to a low level state, such as a ground state or a state in which the level is lower than a second level threshold, so that the target port is set to an output state; at the same time, the controller may set the first port to a high impedance state, such as a state with a level above a second level threshold, such that the first port is set to an input state.
For example, when the CPLD is connected to the BMC through the port a and connected to the NVME hard disk 2 through the port B, and data transmission is performed between the BMC and the NVME2 through data connection between the port a and the port B, if the CPLD detects that the level changes from low to high at the port B, it is determined that the BMC on the port a side is to perform data input and the NVME hard disk 2 on the port B side is to perform data reception, and at this time, the CPLD sets the port a in a high-impedance state and pulls the port B low or grounds the port B, so that the NVME hard disk 2 on the port B side can receive the first data transmitted by the BMC on the port a side, as shown in fig. 6.
In one implementation, the controller includes a target area, and the target area is a storage area partitioned from the controller. The target area may store data or information and the like.
It should be noted that the target area may be a storage area partitioned in a nonvolatile storage unit for storing the image file in the controller. The mirror image file refers to a file for the controller to realize self-starting.
Based on this, the method in this embodiment may further include the following steps, as shown in fig. 11:
step 107: the controller receives the information access instruction transmitted by the first device.
The information access instruction may be an instruction to read target information, write target information, modify target information, or delete target information. The controller can receive the information access instruction transmitted by the first device through an I2C bus between the controller and the first device.
Step 108: and the controller accesses the target information corresponding to the information access instruction in the target area to obtain an access result.
The target area may be used for storing field replaceable unit (fru) information.
Specifically, in this embodiment, a part of interface logic, that is, interface logic of an I2C bus, is added to the controller, so that the target area and the first device are connected through the I2C bus, and are used for enabling the first device to access information in the target area.
Referring to fig. 12, a schematic structural diagram of a controller according to the second embodiment of the present disclosure is provided, where the controller may be a controller capable of performing data processing and data transmission, and the controller is a single programmable logic circuit component, such as a CPLD, a PSOC, an SCM, or an MCU. The technical scheme in the embodiment is mainly used for reducing the number of chips in the electronic equipment so as to reduce the pressure on the space occupation of the electronic equipment.
Specifically, the controller in this embodiment may include the following components:
a first port 1201 and at least one second port 1202, the first port 1201 being for connection to a first device and the second port 1202 being for connection to a second device;
the method comprises the steps that under the condition that a first device and at least one second device are connected to a controller respectively, the controller receives a connection instruction transmitted by the first device, and establishes data connection between the first device and a target device at least according to the connection instruction, wherein the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device;
the controller is a single programmable logic circuit component and can transmit data to the first equipment.
According to the foregoing scheme, in the controller provided in the second embodiment of the present application, the function of implementing data transmission between the master device and the slave device is integrated into a single programmable logic circuit component, that is, the controller, so that data transmission between the controller and the master device can be implemented, and data transmission between the master device and the slave device can also be implemented.
In one implementation, the controller is in data connection with the first device through a first port, and the controller is in data connection with the second devices through second ports, one of the second ports corresponding to one of the second devices;
wherein, when the controller detects a low level signal on the first port, the controller sets the first port to an input state and sets a target port connected to the target device in the second port to an output state, so that the first device transmits first data to the target device through the data connection.
In one implementation, when the controller detects that the first port changes from a low-level signal to a high-level signal, the controller sets the first port to an output state and sets the target port to an input state, so that the first device receives second data transmitted by the target device through the data connection.
In one implementation, the controller is in data connection with the first device through a first port, and the controller is in data connection with the second devices through second ports, one of the second ports corresponding to one of the second devices;
when the controller detects a low-level signal on a target port connected to the target device in the second port, the controller sets the target port to an input state and sets the first port to an output state, so that the first device receives second data transmitted by the target device through the data connection.
In one implementation, when the controller detects a signal changing from a low level signal to a high level signal on the second port, the controller sets the target port to an output state and sets the first port to an input state, so that the first device transmits first data to the target device through the data connection.
Wherein, the controller sets the first port as an input state, specifically: the controller sets the first port to be in a high-resistance state; the controller sets the target port to be in an output state, specifically: the controller sets the target port to a low state.
Wherein, the controller sets the first port to be in an output state, specifically: the controller sets the first port to be in a low level state; the controller sets the target port to be in an input state, specifically: the controller sets the target port to be in a high impedance state.
In one implementation, the controller receives an information access instruction transmitted by the first device; the controller accesses the target information corresponding to the information access instruction in a target area to obtain an access result; the target area is a storage area divided in the controller.
It should be noted that, in the present embodiment, reference may be made to the corresponding contents in the foregoing for specific implementation of the controller, and details are not described here.
Referring to fig. 13, a schematic structural diagram of an electronic device provided in the third embodiment of the present application is shown, where the electronic device may be a computer or a server. The technical scheme in the embodiment is mainly used for reducing the number of chips in the electronic equipment so as to reduce the pressure on the space occupation of the electronic equipment.
Specifically, the electronic device in this embodiment may include the following structure:
a controller 1301, a first device 1302 and at least one second device 1303.
The controller 1301 is a single programmable logic circuit component, and can perform data transmission with the first device 1302. The first device may be a master device such as BMC, and the second device may be a NVME hard disk.
When a first device 1302 and at least one second device 1303 are connected to a controller 1301, respectively, the controller 1301 receives a connection instruction transmitted by the first device 1302, and establishes a data connection between the first device 1302 and a target device 1304 at least according to the connection instruction, where the target device 1304 is a device corresponding to the connection instruction in the second device 1303, and the data connection is used to implement data transmission between the first device 1302 and the target device 1304.
According to the above scheme, in the electronic device provided in the third embodiment of the present application, the function of implementing data transmission between the master device and the slave device is integrated into a single programmable logic circuit component, that is, the controller, so that data transmission between the controller and the master device can be implemented, and data transmission between the master device and the slave device can also be implemented.
The following takes a server including a backplane as an example to illustrate the technical solution of the present application in detail:
first, the inventors of the present application found that, when the back plate is provided with the accessory: in the existing back panel design supporting NVME, at least three types of chips are required:
the control chip is usually a CPLD, a PSOC or an MCU and the like which are used as logic processing units on the backboard and carry out information interaction with a main controller on the mainboard;
the equipment information chip, usually an EEPROM, is used for storing the contents such as the product serial number, description information, etc.;
and the I2C expansion chip is used for expanding the single-path I2C bus of the master into multiple paths and respectively connected to the I2C interfaces on the NVME hard disks so as to obtain various information such as equipment manufacturers, temperatures and the like of the hard disks.
Taking the backplane supporting 4 NVME hard disks as an example, as shown in fig. 14, the master BMC is respectively connected to the control chip PSOC/CPLD, the I2C expansion chip expander and the device information chip FRU through an I2C bus, and is respectively connected to the NVME hard disks 1 to 4 through an I2C bus on the expander.
Therefore, the inventor of the application finds that the space and the cost of the back plate are strictly limited, so that if the types and the number of the chips can be reduced, the BOM cost can be directly reduced, the overall layout can be effectively optimized, the signal routing can be reduced, and the production and test difficulty can be reduced.
In view of this, the inventor of the present application proposes a technical solution for backplane integration, in which the characteristics of the CPLD programmable logic chip are fully utilized, and the related functions of the device information chip and the I2C expansion chip are integrated into a single CPLD chip, so as to implement integration of the active device on the backplane. The design can effectively reduce the BOM (bill of material) cost and simplify the circuit design of the backboard.
Also taking a backplane supporting 4 NVME hard disks as an example, the new backplane structure is shown in fig. 15, the master controller BMC is connected with the control chip CPLD through an I2C bus, and the control chip CPLD is respectively connected with the NVME hard disks 1 to 4 through an I2C bus, based on the characteristics of the programmable logic, an I2C extension chip Expander and an internal storage FRU are extended inside the control chip CPLD except for the control register Registers.
Thus, in connection with the controller implementation shown in fig. 15, the controller-implemented I2C extension logic and FRU storage logic are described in detail below:
1. I2C extended logic:
the working mechanism of the I2C extended chip is that after receiving a specific instruction from the master device, it knows which slave port the master device needs to communicate with at this time. And then bridges its selected slave port with the master device port. As shown in fig. 16, the I2C extension logic is implemented in the CPLD, so that the functions of the I2C extension chip can be implemented in the controller, based on which, the master device, such as BMC, is connected through the master port in the I2C extension chip, the slave device 1-4, such as NVME hard disk 1-4, is connected through the slave port in the I2C extension chip, and the switching of the port connection between the master port and the slave port can be implemented through 1/4 switches.
The I2C bus is generally composed of two signal lines: a Clock signal line scl (system Clock line), and a data signal line sda (serialdata). The method is to realize bidirectional interaction between master and slave devices through a single SDA signal line, so that the control mechanism of the master and slave devices is specified through a specific instruction in a protocol. Before the bus runs, the SDA signal line is controlled by the master device, when the master device needs to receive the slave device information, the master device releases the control right of the bus (the master device end is released to be in a high-impedance state), and the slave device can transmit the information to the master device. When the slave device finishes transmitting, the slave device releases the bus control right (the slave device end is released to be in a high-impedance state), and the master device can continue to control the signal line.
As shown in fig. 16, the CPLD is implemented by logic, and can easily analyze the switching instruction sent by the host device to identify the current routing configuration. The key technique is how to identify the direction on the SDA signal line when it knows the signal routing so that information can be passed correctly from the master port transparently to the slave port, or vice versa.
Based on this, when the CPLD is implemented, the characteristics of open-drain (open-drain) and external pull-up of the I2C port are fully utilized, that is, when the port outputs a high level or serves as an input, the port is controlled to be in a high-impedance state; the port will only be forced low if it is going to output a low level. In the logic implementation, the master-slave property of the equipment is not concerned, and the two ends are treated equally. Taking two ports, i.e., a (master port) and a B (slave port), on two sides as an example, when the CPLD implements the data transmission function of the I2C expansion chip, the logic control mechanism of the CPLD is:
(1) when the power is on by default, A, B is considered to be input at both ends and is set to be in a high impedance state. The CPLD simultaneously monitors the level states of both ports.
(2) If both ends of A, B are high, it is assumed that there is no change on both sides of the port, and high resistance control is maintained at both ends A, B.
(3) If the A port detects a low, the A-side device is considered to pull the SDA signal line low. At this time, the high impedance state of the a port is maintained (still input), the B port is switched to the output port and pulled low, and at this time, data is transferred from the master to the slave.
(4) Then only monitoring the state of the port A, and if the state is low, always keeping the output of the port B to be low; after it goes high, the a port is considered to output high logic, or it is switched to input and the SDA signal line is released, at which time the B port is switched to input and set to high impedance, at which time data is transmitted by the slave to the master.
(5) Returning to (2), the status of both ends continues to be monitored A, B. And (5) after the state of any end is changed, the steps are circularly executed according to the steps (2) to (5) (if the end B is low, the output of the end A is pulled down).
2. FRU storage logic:
to store FRU information, a CPLD is required to support a nonvolatile memory cell internally. One of the characteristics of the CPLD chip is that it has a nonvolatile memory unit for storing its self-starting image file. Therefore, its storage space can be divided into a part for storing FRU information. The CPLD needs to add a part of interface logic for realizing that the master accesses FRU information in the CPLD.
As shown in fig. 17, when the BMC needs to write to the CPLD, the BMC first transmits information to the Block RAM of 32kb through I2C slave and BRAM Bridge in the CPLD, and then writes the information to the on-chip flash through the SPI Bridge in the CPLD, thereby implementing information writing.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A control method, comprising:
under the condition that a first device and at least one second device are respectively connected to a controller, the controller receives a connection instruction transmitted by the first device;
the controller establishes a data connection between the first device and a target device at least according to the connection instruction, the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device;
the controller is a single programmable logic circuit component and can transmit data to the first equipment.
2. The method of claim 1, the controller implementing a data connection with the first device through a first port and the controller implementing a data connection with the second device through a second port, one of the second ports corresponding to one of the second devices;
wherein the method further comprises:
and under the condition that the controller detects a low-level signal on the first port, the controller sets the first port to be in an input state and sets a target port connected to the target device in the second port to be in an output state, so that the first device transmits first data to the target device through the data connection.
3. The method of claim 2, further comprising:
and when the controller detects that the signal changes from a low level signal to a high level signal on the first port, the controller sets the first port to be in an output state and sets the target port to be in an input state, so that the first device receives second data transmitted by the target device through the data connection.
4. The method of claim 1, the controller implementing a data connection with the first device through a first port and the controller implementing a data connection with the second device through a second port, one of the second ports corresponding to one of the second devices;
wherein the method further comprises:
and under the condition that the controller detects a low-level signal on a target port connected to the target equipment in the second port, the controller sets the target port to be in an input state and sets the first port to be in an output state, so that the first equipment receives second data transmitted by the target equipment through the data connection.
5. The method of claim 4, further comprising:
and when the controller detects that the signal changes from a low level signal to a high level signal on the second port, the controller sets the target port to be in an output state and sets the first port to be in an input state, so that the first device transmits first data to the target device through the data connection.
6. The method of claim 2 or 5, the controller setting the first port to an input state, comprising:
the controller sets the first port to be in a high-resistance state;
wherein the controller sets the target port to an output state, including:
the controller sets the target port to a low state.
7. The method of claim 3 or 4, the controller setting the first port to an output state, comprising:
the controller sets the first port to be in a low level state;
wherein the controller sets the target port to an input state, including:
the controller sets the target port to be in a high impedance state.
8. The method of claim 1, further comprising:
the controller receives an information access instruction transmitted by the first equipment;
the controller accesses the target information corresponding to the information access instruction in a target area to obtain an access result; the target area is a storage area divided in the controller.
9. A controller, comprising:
the device comprises a first port and at least one second port, wherein the first port is used for connecting a first device, and the second port is used for connecting a second device;
the method comprises the steps that under the condition that a first device and at least one second device are connected to a controller respectively, the controller receives a connection instruction transmitted by the first device, and establishes data connection between the first device and a target device at least according to the connection instruction, wherein the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device;
the controller is a single programmable logic circuit component and can transmit data to the first equipment.
10. An electronic device, comprising:
a controller, a first device and at least one second device;
the method comprises the steps that under the condition that a first device and at least one second device are connected to a controller respectively, the controller receives a connection instruction transmitted by the first device, and establishes data connection between the first device and a target device at least according to the connection instruction, wherein the target device is a device corresponding to the connection instruction in the second device, and the data connection is used for realizing data transmission between the first device and the target device;
the controller is a single programmable logic circuit component and can transmit data to the first equipment.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115982087A (en) * | 2023-02-20 | 2023-04-18 | 中科可控信息产业有限公司 | Signal transmission method, computer device, and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130304999A1 (en) * | 2010-10-06 | 2013-11-14 | Sharp Kabushiki Kaisha | Electronic device and serial data communication method |
| US20140189177A1 (en) * | 2013-01-03 | 2014-07-03 | International Business Machines Corporation | High speed overlay of idle i2c bus bandwidth |
| CN108701004A (en) * | 2017-01-25 | 2018-10-23 | 华为技术有限公司 | A kind of system of data processing, method and corresponding intrument |
| CN110472421A (en) * | 2019-07-22 | 2019-11-19 | 深圳中电长城信息安全系统有限公司 | Mainboard, firmware safety detection method and terminal device |
| CN110659238A (en) * | 2018-06-28 | 2020-01-07 | 鸿富锦精密电子(天津)有限公司 | Data communication system |
| CN111061587A (en) * | 2019-12-12 | 2020-04-24 | 浪潮商用机器有限公司 | Communication control method, device, equipment and storage medium of I2C bus |
| CN111641633A (en) * | 2020-05-28 | 2020-09-08 | 联想(北京)有限公司 | Information processing method for memory and electronic equipment |
| CN112416841A (en) * | 2020-11-10 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | Multi-machine communication realization method based on I2C bus and multi-machine communication system |
-
2021
- 2021-03-29 CN CN202110335237.5A patent/CN112947287A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130304999A1 (en) * | 2010-10-06 | 2013-11-14 | Sharp Kabushiki Kaisha | Electronic device and serial data communication method |
| US20140189177A1 (en) * | 2013-01-03 | 2014-07-03 | International Business Machines Corporation | High speed overlay of idle i2c bus bandwidth |
| CN108701004A (en) * | 2017-01-25 | 2018-10-23 | 华为技术有限公司 | A kind of system of data processing, method and corresponding intrument |
| CN110659238A (en) * | 2018-06-28 | 2020-01-07 | 鸿富锦精密电子(天津)有限公司 | Data communication system |
| CN110472421A (en) * | 2019-07-22 | 2019-11-19 | 深圳中电长城信息安全系统有限公司 | Mainboard, firmware safety detection method and terminal device |
| CN111061587A (en) * | 2019-12-12 | 2020-04-24 | 浪潮商用机器有限公司 | Communication control method, device, equipment and storage medium of I2C bus |
| CN111641633A (en) * | 2020-05-28 | 2020-09-08 | 联想(北京)有限公司 | Information processing method for memory and electronic equipment |
| CN112416841A (en) * | 2020-11-10 | 2021-02-26 | 光华临港工程应用技术研发(上海)有限公司 | Multi-machine communication realization method based on I2C bus and multi-machine communication system |
Non-Patent Citations (1)
| Title |
|---|
| 刘昌华等: "《数字逻辑原理与FPGA设计》", 28 February 2021 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115982087A (en) * | 2023-02-20 | 2023-04-18 | 中科可控信息产业有限公司 | Signal transmission method, computer device, and storage medium |
| CN115982087B (en) * | 2023-02-20 | 2023-09-19 | 中科可控信息产业有限公司 | Signal transmission method, computer device and storage medium |
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