CN112929017A - Promote integrator circuit of speed of resetting - Google Patents

Promote integrator circuit of speed of resetting Download PDF

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Publication number
CN112929017A
CN112929017A CN202110141961.4A CN202110141961A CN112929017A CN 112929017 A CN112929017 A CN 112929017A CN 202110141961 A CN202110141961 A CN 202110141961A CN 112929017 A CN112929017 A CN 112929017A
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mos tube
electrode
mos
reset
drain electrode
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CN112929017B (en
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王海强
王洪波
曹海祥
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Tongyuanwei Beijing Semiconductor Technology Co ltd
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Tongyuanwei Beijing Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)

Abstract

One embodiment of the invention discloses an integrator circuit for improving reset speed, which comprises: the amplifier comprises a reverse input end, a forward input end, an output end and a reset end; an integrating capacitor array; a first switch; and a second switch; the first end of the integrating capacitor array, the first end of the first switch and the second end of the second switch are connected with the reverse input end; the second end of the integrating capacitor array and the second end of the first switch are connected with the output end; a first end of the second switch receives a current input signal; the positive input end receives a reference voltage; in a coarse reset stage, the first switch receives an effective first reset signal, and the reset end receives an effective second reset signal, so that a voltage output signal output by the output end is close to a reference voltage; in the fine reset stage, the first switch continues to receive the effective first reset signal, and the reset terminal does not receive the effective second reset signal any more, so that the voltage output signal output by the output terminal is closer to the reference voltage than in the coarse reset stage.

Description

Promote integrator circuit of speed of resetting
Technical Field
The invention relates to the technical field of signal conversion, in particular to an integrator circuit for improving reset speed.
Background
The current-voltage integrator is mainly applied to the field of X-ray detectors and mainly used for converting a current signal output by a sensor into a voltage signal. Since the converted current can be very low, the integrator needs to have very low noise, and designers often reduce the noise of the integrator by increasing the miller compensation capacitance of the amplifier in the integrator to reduce the bandwidth of the integrator. But as the bandwidth of the integrator decreases, the longer it will take to reset during the reset phase.
The reset speed of the traditional integrator mainly depends on the bandwidth of the integrator, the larger the bandwidth of the integrator is, the faster the reset speed is, but the larger the noise generated by the integrator in the integration process is; the smaller the integrator bandwidth, the slower the reset speed, and the less noise the integrator generates during integration. The bandwidth of the integrator is typically designed to be small for the sake of reducing integrator noise, but this also increases the time for resetting the conventional integrator, increasing the "dead" time of the detector, which can be wasteful of time.
Disclosure of Invention
The invention aims to provide an integrator circuit capable of improving the reset speed, which reduces the reset time by increasing the reset end of an amplifier, a reset signal connected with the reset end and an amplifier circuit structure and solves the problem of long reset time of the traditional integrator.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides an integrator circuit for improving reset speed, which comprises:
the amplifier comprises a reverse input end, a forward input end, an output end and a reset end;
an integrating capacitor array;
a first switch; and
a second switch;
wherein the content of the first and second substances,
the first end of the integrating capacitor array, the first end of the first switch and the second end of the second switch are connected with the inverting input end;
the second end of the integrating capacitor array and the second end of the first switch are connected with the output end;
a first end of the second switch receives a current input signal;
the positive input end receives a reference voltage;
in a coarse reset stage, the first switch receives an effective first reset signal, and the reset terminal receives an effective second reset signal, so that a voltage output signal output by the output terminal approaches the reference voltage;
in a fine reset phase, the first switch continues to receive the effective first reset signal, and the reset terminal no longer receives the effective second reset signal, so that the voltage output signal output by the output terminal is closer to the reference voltage than in the coarse reset phase.
In one embodiment, during the integration phase, the first switch is turned off, the second switch is turned on, and the current input signal is input to the inverting input terminal of the amplifier, thereby outputting the voltage output signal.
In one embodiment, the circuit of the integrating capacitor array comprises:
first to nth integrating capacitance branch circuits connected in parallel, wherein the nth integrating capacitance branch circuit includes an nth capacitance array switch and an nth integrating capacitor, wherein a first end of the nth capacitance array switch is connected to a first end of the integrating capacitance array, a first electrode of the nth integrating capacitor is connected to a second end of the nth capacitance array switch, and a second electrode of the nth integrating capacitor is connected to a second end of the integrating capacitance array;
wherein N is 1-N, and N is a positive integer greater than or equal to 1.
In one embodiment, the circuit of the amplifier comprises:
the MOS transistor comprises first to fourteenth MOS transistors, a phase inverter and a Miller compensation capacitor, wherein the first to third MOS transistors, the eighth MOS transistor, the ninth MOS transistor and the eleventh to fourteenth MOS transistors are NMOS transistors, and the fourth to seventh MOS transistors and the tenth MOS transistor are PMOS transistors;
the grid electrode of the first MOS tube is connected with the inverting input end of the amplifier; the drain electrode of the first MOS tube is connected with the drain electrode of the fourth MOS tube; the source electrode of the first MOS tube is connected with the drain electrode of the third MOS tube and the source electrode of the second MOS tube;
the grid electrode of the second MOS tube is connected with the positive input end of the amplifier; the drain electrode of the second MOS tube is connected with the first electrode of the Miller compensation capacitor;
the second electrode of the Miller compensation capacitor is connected with the output end of the amplifier;
the source electrode of the third MOS tube is grounded; the grid electrode of the third MOS tube is connected with a first bias voltage;
the source electrode of the fourth MOS tube is connected with a power supply; the grid electrode of the fourth MOS tube is connected with the second bias voltage and the grid electrode of the fifth MOS tube;
the source electrode of the fifth MOS tube is connected with a power supply; the drain electrode of the fifth MOS tube is connected with the first electrode of the Miller compensation capacitor and the source electrode of the seventh MOS tube;
the drain electrode of the seventh MOS tube is connected with the drain electrode of the ninth MOS tube, the grid electrode of the eleventh MOS tube and the drain electrode of the twelfth MOS tube; the grid electrode of the seventh MOS tube is connected with the third bias voltage and the grid electrode of the sixth MOS tube;
the source electrode of the sixth MOS tube is connected with the drain electrode of the fourth MOS tube; the drain electrode of the sixth MOS tube is connected with the drain electrode of the eighth MOS tube and the grid electrode of the eighth MOS tube;
the source electrode of the eighth MOS tube is grounded;
the grid electrode of the ninth MOS tube is connected with the grid electrode of the eighth MOS tube and the drain electrode of the thirteenth MOS tube; the source electrode of the ninth MOS tube is grounded;
the source electrode of the thirteenth MOS tube is connected with the grid electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the thirteenth MOS tube is connected with the reset end of the amplifier and the input end of the phase inverter;
the output end of the phase inverter is connected with the grid electrode of the fourteenth MOS tube;
the source electrode of the fourteenth MOS tube is grounded;
the source electrode of the twelfth MOS tube is grounded;
the source electrode of the eleventh MOS tube is grounded; the drain electrode of the eleventh MOS tube is connected with the second electrode of the Miller compensation capacitor and the drain electrode of the tenth MOS tube;
the source electrode of the tenth MOS tube is connected with a power supply; and the grid electrode of the tenth MOS tube is connected with the second bias voltage.
In a specific embodiment, in the coarse reset stage, the thirteenth MOS transistor is turned on, the fourteenth MOS transistor is turned off, and the current of the twelfth MOS transistor replicates the current of the eighth MOS transistor according to a preset proportion, so that the current flowing through the tenth MOS transistor, the miller compensation capacitor and the seventh MOS transistor is increased, and the charging speed of the miller compensation capacitor is accelerated;
in the fine reset stage, the thirteenth MOS transistor is turned off, the fourteenth MOS transistor is turned on, the gate voltage of the twelfth MOS transistor is pulled to the ground level, and the twelfth MOS transistor is turned off, so that the voltage output signal output by the output terminal is closer to the reference voltage than in the coarse reset stage.
In a particular embodiment, the first reset signal and the second reset signal are active when high.
In one embodiment, the circuit of the amplifier comprises:
the MOS transistor comprises first to fourteenth MOS transistors, a phase inverter and a Miller compensation capacitor, wherein the first to fifth MOS transistors and the tenth MOS transistor are PMOS transistors, and the sixth to ninth MOS transistors and the eleventh to fourteenth MOS transistors are NMOS transistors;
the grid electrode of the first MOS tube is connected with the inverting input end of the amplifier; the drain electrode of the first MOS tube is connected with the drain electrode of the eighth MOS tube; the source electrode of the first MOS tube is connected with the drain electrode of the third MOS tube and the source electrode of the second MOS tube;
the grid electrode of the second MOS tube is connected with the positive input end of the amplifier; the drain electrode of the second MOS tube is connected with the first electrode of the Miller compensation capacitor;
the second electrode of the Miller compensation capacitor is connected with the output end of the amplifier;
the source electrode of the third MOS tube is connected with a power supply; the grid electrode of the third MOS tube is connected with a first bias voltage;
the source electrode of the fourth MOS tube is connected with a power supply; the grid electrode of the fourth MOS tube is connected with the second bias voltage and the grid electrode of the fifth MOS tube;
the source electrode of the fifth MOS tube is connected with a power supply; the drain electrode of the fifth MOS tube is connected with the drain electrode of the seventh MOS tube and the grid electrode of the eleventh MOS tube;
the source electrode of the seventh MOS tube is connected with the drain electrode of the ninth MOS tube, the first electrode of the Miller compensation capacitor and the drain electrode of the twelfth MOS tube; the grid electrode of the seventh MOS tube is connected with the third bias voltage and the grid electrode of the sixth MOS tube;
the drain electrode of the sixth MOS tube is connected with the drain electrode of the fourth MOS tube and the grid electrode of the eighth MOS tube; the source electrode of the sixth MOS tube is connected with the drain electrode of the eighth MOS tube;
the source electrode of the eighth MOS tube is grounded;
the grid electrode of the ninth MOS tube is connected with the grid electrode of the eighth MOS tube and the drain electrode of the thirteenth MOS tube; the source electrode of the ninth MOS tube is grounded;
the source electrode of the thirteenth MOS tube is connected with the grid electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the thirteenth MOS tube is connected with the reset end of the amplifier and the input end of the phase inverter;
the output end of the phase inverter is connected with the grid electrode of the fourteenth MOS tube;
the source electrode of the fourteenth MOS tube is grounded;
the source electrode of the twelfth MOS tube is grounded;
the source electrode of the eleventh MOS tube is grounded; the drain electrode of the eleventh MOS tube is connected with the second electrode of the Miller compensation capacitor and the drain electrode of the tenth MOS tube;
the source electrode of the tenth MOS tube is connected with a power supply; and the grid electrode of the tenth MOS tube is connected with the second bias voltage.
In a specific embodiment, in the coarse reset stage, the thirteenth MOS transistor is turned on, the fourteenth MOS transistor is turned off, and the current of the twelfth MOS transistor replicates the current of the eighth MOS transistor according to a preset proportion, so that the current flowing through the tenth MOS transistor, the miller compensation capacitor and the seventh MOS transistor is increased, and the charging speed of the miller compensation capacitor is accelerated;
in the fine reset stage, the thirteenth MOS transistor is turned off, the fourteenth MOS transistor is turned on, the gate voltage of the twelfth MOS transistor is pulled to the ground level, and the twelfth MOS transistor is turned off, so that the voltage output signal output by the output terminal is closer to the reference voltage than in the coarse reset stage.
In a particular embodiment, the first reset signal and the second reset signal are active when high.
The invention has the following beneficial effects:
according to the integrator circuit for improving the reset speed, the reset time is shortened by adding the amplifier reset end, the reset signal connected with the reset end and the amplifier circuit structure, the reset speed of the integrator is ensured to be accelerated, meanwhile, the bias circuit is not influenced, the power consumption of a power supply is not increased, and the problem that the reset time of a traditional integrator is long is solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are one embodiment of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a block diagram of a conventional integrator circuit according to an embodiment of the present invention.
Fig. 2 illustrates a conventional amplifier circuit configuration diagram of a conventional integrator according to an embodiment of the present invention.
Fig. 3 shows a block diagram of an integrator circuit for increasing the reset speed according to an embodiment of the present invention.
Fig. 4 is a block diagram illustrating an amplifier circuit of an integrator for increasing a reset speed according to an embodiment of the present invention.
Fig. 5 shows a timing diagram of a reset signal according to one embodiment of the invention.
Fig. 6 is a diagram showing an amplifier circuit configuration of an integrator for improving a reset speed according to another embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The present invention will be described in detail with reference to specific examples, but the present invention is not limited to these examples. Variations and modifications may be made by those skilled in the art without departing from the principles of the invention and should be considered within the scope of the invention.
Referring to fig. 1, fig. 1 shows a conventional integrator circuit structure, which includes:
a conventional amplifier 1, an integrating capacitor array 11 with configurable capacitance value, a first switch SW1 and a second switch SW 2;
wherein the second switch SW2 controls the current input terminal IINWhether the input current input signal is connected to an integrator or not;
the first switch SW1 is a RESET switch, and the first RESET signal RESET controls the on-off of the first switch SW 1; the conventional integrator has the first switch SW1 turned off during integration and the first switch SW1 turned on during reset. When the conventional integrator is in a reset state, the input end and the output end of the conventional amplifier 1 are short-circuited, and the conventional amplifier 1 outputs the output end V of the conventional amplifier 1 through unit negative feedbackOUTReset to reference voltage VREF。
As shown in fig. 2, the circuit of the conventional amplifier 1 includes:
first to eleventh MOS transistors M1 to M11 and a Miller compensation capacitor CM;
the conventional amplifier 1 belongs to a cascode two-stage operational amplifier; the first MOS transistor M1 and the second MOS transistor M2 are input transistors and form a first stage of the traditional amplifier 1 together with the third MOS transistor M3-M9; the tenth MOS transistor M10 and the eleventh MOS transistor M11 form a second stage of the conventional amplifier 1, and since the second stage needs higher driving capability, the tenth MOS transistor M10 and the eleventh MOS transistor M1 generally have higher current. But the current flowing through the first stage is typically much less than the current flowing through the second stage due to power consumption considerations.
The reset speed of the traditional integrator mainly depends on the bandwidth of the integrator, the larger the bandwidth of the integrator is, the faster the reset speed is, but the larger the noise generated by the integrator in the integration process is; the smaller the integrator bandwidth, the slower the reset speed, and the less noise the integrator generates during integration. The bandwidth of the integrator is typically designed to be small for the sake of reducing integrator noise, but this also increases the time for resetting the conventional integrator, increasing the "dead" time of the detector, which can be wasteful of time.
Therefore, the present embodiment provides an integrator circuit for increasing the reset speed on the basis of the above-mentioned conventional integrator circuit, as shown in fig. 3, the integrator circuit for increasing the reset speed includes:
an amplifier 2 including an inverting input terminal, a forward input terminal, and an output terminal VOUTAnd a reset terminal RST;
an integrating capacitor array 11;
a first switch SW1 and a second switch SW 2;
wherein the content of the first and second substances,
the first end of the integrating capacitor array 11, the first end of the first switch SW1 and the second end of the second switch SW2 are connected to the inverting input terminal;
the second end of the integrating capacitor array 11 and the second end of the first switch SW1 are connected to the output end VOUT；
A first terminal of the second switch SW2 receives the current input terminal IINA transmitted current input signal;
the positive input end receives a reference voltage VREF；
Wherein the first switch SW1 is controlled by the first RESET signal RESET, and the RESET terminal RST receives the second RESET signal FRST.
The circuit of the integrating capacitor array 11 includes:
first to Nth integrating-capacitance branch circuits connected in parallel, wherein the Nth integrating-capacitance branch circuit includes an Nth capacitance array switch SW3_ N and an Nth integrating capacitor CINTnWherein a first terminal of the nth capacitive array switch is connected to a first terminal of the integrating capacitive array, a first electrode of the nth integrating capacitor is connected to a second terminal of the nth capacitive array switch, and a second terminal of the nth integrating capacitorAn electrode is connected to a second end of the integrating capacitor array,
wherein N is 1-N, and N is a positive integer greater than or equal to 1; cINT1～CINTnThe capacitance values of the integration capacitors are determined according to actual requirements; n is determined according to the input current range of the integrator in practical application, for example, the input current range is large, a large number of integration capacitors are required, and the value of N is large.
In one embodiment, the first switch SW1, the second switch SW2, and the first to nth capacitor array switches SW3_1 to SW3_ n are all MOS transistors switches. The first end and the second end of the switch respectively refer to a source electrode and a drain electrode of the MOS tube, and corresponding driving signals are sent to a grid electrode of the MOS tube.
Further, as shown in fig. 4, the circuit of the amplifier 2 includes:
first to fourteenth MOS transistors M1 to M14, an inverter INV, and a Miller compensation capacitor CM;
the first to third MOS transistors M1-M3, the eighth MOS transistor M8, the ninth MOS transistor M9 and the eleventh to fourteenth MOS transistors M11-M14 are NMOS transistors, and the fourth to seventh MOS transistors M4-M7 and the tenth MOS transistor M10 are PMOS transistors;
the grid electrode of the first MOS transistor M1 is connected with the inverting input VIN of the amplifier 2; the drain electrode of the first MOS transistor M1 is connected with the drain electrode of the fourth MOS transistor M4; the source electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3 and the source electrode of the second MOS transistor M2;
the gate of the second MOS transistor M2 is connected with the positive input end VIP of the amplifier; the drain electrode of the second MOS tube M2 is connected with the first electrode of the Miller compensation capacitor CM;
the second electrode of the Miller compensation capacitor CM is connected with the output end V of the amplifierOUT；
The source electrode of the third MOS transistor M3 is grounded VSS; the gate of the third MOS transistor M3 is connected to the first bias voltage VB 1;
the source electrode of the fourth MOS transistor M4 is connected with a power supply VDD; the gate of the fourth MOS transistor M4 is connected to the second bias voltage VB2 and the gate of the fifth MOS transistor M5;
the source electrode of the fifth MOS transistor M5 is connected with a power supply VDD; the drain electrode of the fifth MOS tube M5 is connected with the first electrode of the Miller compensation capacitor CM and the source electrode of the seventh MOS tube M7;
the drain electrode of the seventh MOS tube M7 is connected with the drain electrode of the ninth MOS tube M9, the gate electrode of the eleventh MOS tube M11 and the drain electrode of the twelfth MOS tube M12; the gate of the seventh MOS transistor M7 is connected to the third bias voltage VB3 and the gate of the sixth MOS transistor M6;
the source electrode of the sixth MOS transistor M6 is connected with the drain electrode of the fourth MOS transistor M4; the drain of the sixth MOS transistor M6 is connected to the drain of the eighth MOS transistor M8 and the gate of the eighth MOS transistor M8;
the source electrode of the eighth MOS transistor M8 is grounded VSS;
the gate of the ninth MOS transistor M9 is connected to the gate of the eighth MOS transistor M8 and the drain of the thirteenth MOS transistor M13; the source electrode of the ninth MOS transistor M9 is grounded VSS;
the source electrode of the thirteenth MOS transistor M13 is connected with the gate electrode of the twelfth MOS transistor M12 and the drain electrode of the fourteenth MOS transistor M14;
the gate of the thirteenth MOS transistor M13 is connected to the reset terminal RST of the amplifier 2 and the input terminal of the inverter INV;
the output end of the inverter INV is connected with the grid electrode of a fourteenth MOS tube M14;
the source electrode of the fourteenth MOS transistor M14 is grounded VSS;
the source electrode of the twelfth MOS transistor M12 is grounded VSS;
the source electrode of the eleventh MOS transistor M11 is grounded VSS; the drain electrode of the eleventh MOS transistor M11 is connected to the second electrode of the miller compensation capacitor CM and the drain electrode of the tenth MOS transistor M10;
the source electrode of the tenth MOS transistor M10 is connected to the power supply VDD; the gate of the tenth MOS transistor M10 is connected to the second bias voltage VB 2;
wherein the content of the first and second substances,
the first to ninth MOS tubes M1-M9 jointly form the first stage of the amplifier, as in the conventional amplifier 1; the tenth MOS transistor M10 and the eleventh MOS transistor M11 together constitute the second stage of the amplifier.
When the current input terminal I of the integrator circuit for increasing the reset speed provided by this embodiment is providedINIntegration when the received input current is largeThe output end V of the integrating amplifier from the beginning of integrating to the end of integratingOUTThe output voltage output signal is derived from a reference voltage VREFFalling to around 0V, the integration ends, the integrator circuit enters a RESET state, and the timings of the first RESET signal RESET and the second RESET signal FRST are shown in fig. 5.
The first RESET signal RESET and the second RESET signal FRST start to become active RESET signals at the same time, i.e., to become high level at the same time, and the pulse length of the second RESET signal FRST is smaller than that of the first RESET signal RESET, which can be set as needed.
The integrator circuit for increasing the reset speed provided by the embodiment divides the reset into two stages: a coarse reset phase and a fine reset phase.
During the coarse RESET phase, the first switch SW1 receives an active first RESET signal RESET and the RESET terminal RST receives an active second RESET signal FRST, so that the output terminal VOUTThe output voltage output signal is close to the reference voltage VREF；
The method specifically comprises the following steps:
the first RESET signal RESET changes from low level to high level to control the first switch SW1 to be conducted, and the amplifier 2 is connected into a unit negative feedback structure;
meanwhile, the second reset signal FRST also changes to a high level, at this time, the thirteenth MOS transistor M13 in the amplifier 2 is turned on, the fourteenth MOS transistor M14 is turned off, and the gate voltage of the twelfth MOS transistor M12 is equal to the gate voltages of the eighth MOS transistor M8 and the ninth MOS transistor M9; thus, the twelfth MOS transistor M12 and the eighth MOS transistor M8 form a current mirror;
the current of the twelfth MOS transistor M12 replicates the current of the eighth MOS transistor M8 according to a predetermined ratio, so that the total current flowing through the seventh MOS transistor M7 is increased, the current flowing through the path of the tenth MOS transistor M10, the miller compensation capacitor CM and the seventh MOS transistor M7 is increased, and the charging speed of the miller compensation capacitor CM during reset is increased.
The current of the tenth MOS transistor M10 and the eighth MOS transistor M8 and the proportion of the current of the eighth MOS transistor M8 copied by the twelfth MOS transistor M12 are reasonably designed, and simultaneously the current is fullThe slew rate of the circuit in the integration process can ensure that the integrator completes the rough reset to the reference voltage V in the very short time when the second reset signal FRST is a high-level pulseREF。
For example: the capacitance value of the miller compensation capacitor CM is 30pF, the output swing of the integrator is 4V, when the integrator is integrated to be close to 0.1V, the voltage of the first electrode of the miller compensation capacitor CM is approximately constant in the integrating and resetting processes, then the resetting process needs to charge the second electrode of the miller compensation capacitor CM from 0.1V to 4.1V, and if the high-level pulse time of the second reset signal FRST is 1us, the current of the tenth MOS transistor M10 needs to be set to be 120uA at least; in consideration of power consumption and slew rate, the current of the eighth MOS transistor M8 is set to 30uA, and the current ratio of the twelfth MOS transistor M12 to the eighth MOS transistor M8 is 3: 1, in the coarse reset stage, the current flowing through the twelfth MOS transistor M12 is 90uA, and the current flowing through the seventh MOS transistor M7 is the sum of the currents of the ninth MOS transistor M9 and the twelfth MOS transistor M12, which is 120uA, so that it can be ensured that the voltage of the second electrode of the miller compensation capacitor CM rises by about 4V when the high level of the second reset signal FRST is 1us, thereby achieving the purpose of fast reset.
The amplifier 2 is connected into a unit negative feedback structure, and the output end V of the amplifier 2OUTIs close to the reference voltage V after the coarse reset is finishedREFAnd in the coarse reset stage when the second reset signal FRST is at a high level, the total current drawn by the amplifier 2 from the power supply VDD is kept constant, thereby ensuring that the fast reset process does not increase extra power consumption.
Entering a fine RESET stage after the coarse RESET stage, the first switch SW1 continues to receive the effective first RESET signal RESET, and the RESET terminal RST no longer receives the effective second RESET signal FRST, that is, the second RESET signal FRST changes from high level to low level, so that the output terminal V is connected to the output terminal VOUTThe output voltage output signal is closer to the reference voltage V than in the coarse reset phaseREF。
The method specifically comprises the following steps:
after the coarse reset is completed, the second reset signal FRST of the integrator changes from high level to low level, the first switch SW1 is still turned on, and the amplifier is turned offThe thirteenth MOS transistor M13 in the amplifier 2 is turned off, the fourteenth MOS transistor M14 is turned on, the gate voltage of the twelfth MOS transistor M12 is pulled to the ground, the twelfth MOS transistor M12 is also turned off, the amplifier 2 has the same structure as the conventional amplifier 1, the integrator provided in this embodiment is reset as the conventional integrator, the integrator starts to enter a fine reset stage, and the integrator outputs a voltage output signal after the fine reset, which is closer to the reference voltage V than the coarse reset stageREF。
Finally, when the reset is completed, the integrator circuit enters an integration phase, the first reset signal and the second reset signal both become low, the first switch SW1 is turned off, the second switch SW2 is still turned on, and the current input signal is input to the inverting input terminal of the amplifier, thereby outputting the voltage output signal.
Because the embodiment accelerates the process of resetting the traditional integrator to the vicinity of the reference voltage at a lower voltage in the resetting process, the current of the current mirror in the amplifier is copied, and no current path is newly added from the power supply, the resetting speed of the integrator is accelerated, the bias circuit is not influenced, and the power consumption of the power supply is not increased.
In another embodiment of the present invention, there is provided a circuit of another amplifier 3 in an integrator circuit for increasing a reset speed, as shown in fig. 6, the circuit of the amplifier 3 includes:
first to fourteenth MOS transistors M1 to M14, an inverter INV, and a Miller compensation capacitor CM;
the first to fifth MOS transistors M1-M5 and the tenth MOS transistor M10 are PMOS transistors, and the sixth to ninth MOS transistors M6-M9 and the eleventh to fourteenth MOS transistors M11-M14 are NMOS transistors;
the grid electrode of the first MOS transistor M1 is connected to the inverting input terminal VIN of the amplifier 3; the drain electrode of the first MOS transistor M1 is connected with the drain electrode of the eighth MOS transistor M8; the source electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3 and the source electrode of the second MOS transistor M2;
the gate of the second MOS transistor M2 is connected to the positive input end VIP of the amplifier 3; the drain electrode of the second MOS tube M2 is connected with the first electrode of the Miller compensation capacitor CM;
the second electrode of the Miller compensation capacitor CM is connected to the output V of the amplifier 3OUT；
The source electrode of the third MOS tube M3 is connected with a power supply VDD; the gate of the third MOS transistor M3 is connected to the first bias voltage VB 1;
the source electrode of the fourth MOS transistor M4 is connected with a power supply VDD; the gate of the fourth MOS transistor M4 is connected to the second bias voltage VB2 and the gate of the fifth MOS transistor M5;
the source electrode of the fifth MOS transistor M5 is connected with a power supply VDD; the drain electrode of the fifth MOS tube M5 is connected with the drain electrode of the seventh MOS tube M7 and the gate electrode of the eleventh MOS tube M11;
the source electrode of the seventh MOS transistor M7 is connected to the drain electrode of the ninth MOS transistor M9, the first electrode of the miller compensation capacitor CM and the drain electrode of the twelfth MOS transistor M12; the gate of the seventh MOS transistor M7 is connected to the third bias voltage VB3 and the gate of the sixth MOS transistor M6;
the drain electrode of the sixth MOS transistor M6 is connected with the drain electrode of the fourth MOS transistor M4 and the gate electrode of the eighth MOS transistor M8; the source electrode of the sixth MOS transistor M6 is connected with the drain electrode of the eighth MOS transistor M8;
the source electrode of the eighth MOS transistor M8 is grounded VSS;
the gate of the ninth MOS transistor M9 is connected to the gate of the eighth MOS transistor M8 and the drain of the thirteenth MOS transistor M13; the source electrode of the ninth MOS transistor M9 is grounded VSS;
the source electrode of the thirteenth MOS transistor M13 is connected with the gate electrode of the twelfth MOS transistor M12 and the drain electrode of the fourteenth MOS transistor M14;
the gate of the thirteenth MOS transistor M13 is connected to the reset terminal RST of the amplifier 3 and the input terminal of the inverter INV;
the output end of the inverter INV is connected with the grid electrode of a fourteenth MOS tube M14;
the source electrode of the fourteenth MOS transistor M14 is grounded VSS;
the source electrode of the twelfth MOS transistor M12 is grounded VSS;
the source electrode of the eleventh MOS transistor M11 is grounded VSS; the drain electrode of the eleventh MOS transistor M11 is connected to the second electrode of the miller compensation capacitor CM and the drain electrode of the tenth MOS transistor M10;
the source electrode of the tenth MOS transistor M10 is connected to the power supply VDD; the gate of the tenth MOS transistor M10 is connected to the second bias voltage VB 2.
The integrator circuit, the reset signal timing and the related operation principle of the present embodiment are completely the same as those of the above embodiments, and are not described herein again.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims (9)

1. An integrator circuit for increasing reset speed, the circuit comprising:
the amplifier comprises a reverse input end, a forward input end, an output end and a reset end;
an integrating capacitor array;
a first switch; and
a second switch;
wherein the content of the first and second substances,
the first end of the integrating capacitor array, the first end of the first switch and the second end of the second switch are connected with the inverting input end;
the second end of the integrating capacitor array and the second end of the first switch are connected with the output end;
a first end of the second switch receives a current input signal;
the positive input end receives a reference voltage;
in a coarse reset stage, the first switch receives an effective first reset signal, and the reset terminal receives an effective second reset signal, so that a voltage output signal output by the output terminal approaches the reference voltage;
in a fine reset phase, the first switch continues to receive the effective first reset signal, and the reset terminal no longer receives the effective second reset signal, so that the voltage output signal output by the output terminal is closer to the reference voltage than in the coarse reset phase.
2. The circuit of claim 1,
in the integration phase, the first switch is turned off, the second switch is turned on, and the current input signal is input to the inverting input terminal of the amplifier, thereby outputting a voltage output signal.
3. The circuit of claim 1, wherein the circuit of the integrating capacitor array comprises:
first to nth integrating capacitance branch circuits connected in parallel, wherein the nth integrating capacitance branch circuit includes an nth capacitance array switch and an nth integrating capacitor, wherein a first end of the nth capacitance array switch is connected to a first end of the integrating capacitance array, a first electrode of the nth integrating capacitor is connected to a second end of the nth capacitance array switch, and a second electrode of the nth integrating capacitor is connected to a second end of the integrating capacitance array;
wherein N is 1-N, and N is a positive integer greater than or equal to 1.
4. The circuit of claim 1, wherein the circuitry of the amplifier comprises:
the MOS transistor comprises first to fourteenth MOS transistors, a phase inverter and a Miller compensation capacitor, wherein the first to third MOS transistors, the eighth MOS transistor, the ninth MOS transistor and the eleventh to fourteenth MOS transistors are NMOS transistors, and the fourth to seventh MOS transistors and the tenth MOS transistor are PMOS transistors;
the grid electrode of the first MOS tube is connected with the inverting input end of the amplifier; the drain electrode of the first MOS tube is connected with the drain electrode of the fourth MOS tube; the source electrode of the first MOS tube is connected with the drain electrode of the third MOS tube and the source electrode of the second MOS tube;
the grid electrode of the second MOS tube is connected with the positive input end of the amplifier; the drain electrode of the second MOS tube is connected with the first electrode of the Miller compensation capacitor;
the second electrode of the Miller compensation capacitor is connected with the output end of the amplifier;
the source electrode of the third MOS tube is grounded; the grid electrode of the third MOS tube is connected with a first bias voltage;
the source electrode of the fourth MOS tube is connected with a power supply; the grid electrode of the fourth MOS tube is connected with the second bias voltage and the grid electrode of the fifth MOS tube;
the source electrode of the fifth MOS tube is connected with a power supply; the drain electrode of the fifth MOS tube is connected with the first electrode of the Miller compensation capacitor and the source electrode of the seventh MOS tube;
the drain electrode of the seventh MOS tube is connected with the drain electrode of the ninth MOS tube, the grid electrode of the eleventh MOS tube and the drain electrode of the twelfth MOS tube; the grid electrode of the seventh MOS tube is connected with the third bias voltage and the grid electrode of the sixth MOS tube;
the source electrode of the sixth MOS tube is connected with the drain electrode of the fourth MOS tube; the drain electrode of the sixth MOS tube is connected with the drain electrode of the eighth MOS tube and the grid electrode of the eighth MOS tube;
the source electrode of the eighth MOS tube is grounded;
the grid electrode of the ninth MOS tube is connected with the grid electrode of the eighth MOS tube and the drain electrode of the thirteenth MOS tube; the source electrode of the ninth MOS tube is grounded;
the source electrode of the thirteenth MOS tube is connected with the grid electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the thirteenth MOS tube is connected with the reset end of the amplifier and the input end of the phase inverter;
the output end of the phase inverter is connected with the grid electrode of the fourteenth MOS tube;
the source electrode of the fourteenth MOS tube is grounded;
the source electrode of the twelfth MOS tube is grounded;
the source electrode of the eleventh MOS tube is grounded; the drain electrode of the eleventh MOS tube is connected with the second electrode of the Miller compensation capacitor and the drain electrode of the tenth MOS tube;
the source electrode of the tenth MOS tube is connected with a power supply; and the grid electrode of the tenth MOS tube is connected with the second bias voltage.
5. The circuit of claim 4,
in a coarse reset stage, the thirteenth MOS tube is switched on, the fourteenth MOS tube is switched off, and the current of the twelfth MOS tube copies the current of the eighth MOS tube according to a preset proportion, so that the current flowing through a path of the tenth MOS tube, the Miller compensation capacitor and the seventh MOS tube is increased, and the charging speed of the Miller compensation capacitor is accelerated;
in the fine reset stage, the thirteenth MOS transistor is turned off, the fourteenth MOS transistor is turned on, the gate voltage of the twelfth MOS transistor is pulled to the ground level, and the twelfth MOS transistor is turned off, so that the voltage output signal output by the output terminal is closer to the reference voltage than in the coarse reset stage.
6. The circuit of claim 4 or 5,
the first reset signal and the second reset signal are active when high.
7. The circuit of claim 1, wherein the circuitry of the amplifier comprises:
the MOS transistor comprises first to fourteenth MOS transistors, a phase inverter and a Miller compensation capacitor, wherein the first to fifth MOS transistors and the tenth MOS transistor are PMOS transistors, and the sixth to ninth MOS transistors and the eleventh to fourteenth MOS transistors are NMOS transistors;
the grid electrode of the first MOS tube is connected with the inverting input end of the amplifier; the drain electrode of the first MOS tube is connected with the drain electrode of the eighth MOS tube; the source electrode of the first MOS tube is connected with the drain electrode of the third MOS tube and the source electrode of the second MOS tube;
the grid electrode of the second MOS tube is connected with the positive input end of the amplifier; the drain electrode of the second MOS tube is connected with the first electrode of the Miller compensation capacitor;
the second electrode of the Miller compensation capacitor is connected with the output end of the amplifier;
the source electrode of the third MOS tube is connected with a power supply; the grid electrode of the third MOS tube is connected with a first bias voltage;
the source electrode of the fourth MOS tube is connected with a power supply; the grid electrode of the fourth MOS tube is connected with the second bias voltage and the grid electrode of the fifth MOS tube;
the source electrode of the fifth MOS tube is connected with a power supply; the drain electrode of the fifth MOS tube is connected with the drain electrode of the seventh MOS tube and the grid electrode of the eleventh MOS tube;
the source electrode of the seventh MOS tube is connected with the drain electrode of the ninth MOS tube, the first electrode of the Miller compensation capacitor and the drain electrode of the twelfth MOS tube; the grid electrode of the seventh MOS tube is connected with the third bias voltage and the grid electrode of the sixth MOS tube;
the drain electrode of the sixth MOS tube is connected with the drain electrode of the fourth MOS tube and the grid electrode of the eighth MOS tube; the source electrode of the sixth MOS tube is connected with the drain electrode of the eighth MOS tube;
the source electrode of the eighth MOS tube is grounded;
the grid electrode of the ninth MOS tube is connected with the grid electrode of the eighth MOS tube and the drain electrode of the thirteenth MOS tube; the source electrode of the ninth MOS tube is grounded;
the source electrode of the thirteenth MOS tube is connected with the grid electrode of the twelfth MOS tube and the drain electrode of the fourteenth MOS tube;
the grid electrode of the thirteenth MOS tube is connected with the reset end of the amplifier and the input end of the phase inverter;
the output end of the phase inverter is connected with the grid electrode of the fourteenth MOS tube;
the source electrode of the fourteenth MOS tube is grounded;
the source electrode of the twelfth MOS tube is grounded;
the source electrode of the eleventh MOS tube is grounded; the drain electrode of the eleventh MOS tube is connected with the second electrode of the Miller compensation capacitor and the drain electrode of the tenth MOS tube;
the source electrode of the tenth MOS tube is connected with a power supply; and the grid electrode of the tenth MOS tube is connected with the second bias voltage.
8. The circuit of claim 7,
in a coarse reset stage, the thirteenth MOS tube is switched on, the fourteenth MOS tube is switched off, and the current of the twelfth MOS tube copies the current of the eighth MOS tube according to a preset proportion, so that the current flowing through a path of the tenth MOS tube, the Miller compensation capacitor and the seventh MOS tube is increased, and the charging speed of the Miller compensation capacitor is accelerated;
in the fine reset stage, the thirteenth MOS transistor is turned off, the fourteenth MOS transistor is turned on, the gate voltage of the twelfth MOS transistor is pulled to the ground level, and the twelfth MOS transistor is turned off, so that the voltage output signal output by the output terminal is closer to the reference voltage than in the coarse reset stage.
9. The circuit of claim 7 or 8,
the first reset signal and the second reset signal are active when high.
CN202110141961.4A 2021-02-02 2021-02-02 Integrator circuit for improving reset speed Active CN112929017B (en)

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