CN112908392B - Control method for controlling parameters of nonvolatile memory - Google Patents
Control method for controlling parameters of nonvolatile memory Download PDFInfo
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- CN112908392B CN112908392B CN202110178558.9A CN202110178558A CN112908392B CN 112908392 B CN112908392 B CN 112908392B CN 202110178558 A CN202110178558 A CN 202110178558A CN 112908392 B CN112908392 B CN 112908392B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
Abstract
The present invention provides a control method for controlling parameters of a nonvolatile memory, the control method comprising: a dynamic trigger point defining step of setting a dynamic trigger point in the dynamic trigger point defining step; an update parameter storage step of storing update parameters in a specific storage area for each of the dynamic trigger points; a marking unit defining step of defining a corresponding marking unit for each dynamic trigger point; and a parameter updating step in which parameters of the nonvolatile memory are updated based on the total number of erase operations that have been completed, the specific number of erase operations corresponding to each dynamic trigger point, and the programmed states of the corresponding flag cells.
Description
Technical Field
The present invention relates to a control method of a parameter, and more particularly, to a control method for controlling a parameter of a nonvolatile memory.
Background
Semiconductor memory devices can be generally classified into Volatile (NV) memory and nonvolatile (Non-Volatile) memory. Volatile memories (such as DRAM, SRAM, etc.) lose stored data in the absence of applied power. In contrast, nonvolatile memory (such as EEPROM, EAROM, PROM, EPROM, flash memory, etc.) is able to retain stored data in the absence of applied power. With the development of portable electronic products (such as personal computers, smart phones, digital cameras, multimedia playing devices, etc.), the demand for nonvolatile memories is increasing, and the demand for performance thereof is also increasing.
In use, the process of powering up the nonvolatile memory is equivalent to a data write operation of the nonvolatile memory, and is referred to as "programming". Whereas the nonvolatile memory is powered down (potential returns to a default potential), this corresponds to the erasing data of the nonvolatile memory, and this process is called "Erase". A complete one-time program/erase (P/E) cycle is the write cycle of the non-volatile memory. Therefore, maintaining P/E cycle stability is critical to the operational life and stability of the nonvolatile memory.
In non-volatile memory storage, it is known to perform program operations using an incremental step pulse programming (ISPP: incremental step pulse program) process and erase operations using an incremental step pulse erase (ISPE: incremental step pulse erase) process. Fig. 1 shows a flow chart and a schematic diagram of an ISPP process. As shown in fig. 1, during ISPP, the program voltage is gently increased until the programmed cell reaches the target program threshold voltage. In the ISPP process, the program start voltage will be set by the initial program speed. Fig. 2 shows a flow chart and schematic diagram of the ISPE process. As shown in fig. 2, during ISPE, the program voltage is gently increased until the erased cell reaches the target erase threshold voltage. In the ISPE process, the erase start voltage will be set by the initial erase speed.
Disclosure of Invention
Technical problem to be solved by the invention
However, in the conventional nonvolatile memory, if the nonvolatile memory cells are programmed at a faster speed during the programming process, the time of the ISPP process is reduced and the initial program start voltage may stress the nonvolatile memory cells. In the erasing process, if the NV cells are erased at a slower speed, the time of the ISPE process increases, and the initial erase start voltage presses the NV cells. Due to these effects, as the number of ISPP processes increases, the ratio of program time to P/E cycle time gradually decreases, as shown in fig. 3, while as the number of ISPE processes increases, the ratio of erase time to P/E cycle time gradually increases. Thus, as the number of ISPE or ISPP runs increases, the ratio of program time to erase time in the P/E cycle time changes, and the P/E cycle becomes unstable, affecting the operating life and performance of the memory.
The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a control method for controlling parameters of a nonvolatile memory, which can change the operating conditions of the nonvolatile memory to improve the P/E cycle performance of the nonvolatile memory.
Technical proposal for solving the technical problems
In one embodiment of the present invention to solve the above-mentioned problems, there is provided a control method for controlling a nonvolatile memory parameter, comprising:
a dynamic trigger point defining step of setting N dynamic trigger points, each of which corresponds to a specific number of erase operations of the nonvolatile memory, wherein N is a positive integer greater than or equal to 1, and the N dynamic trigger points are arranged from 1 to N in order of the specific number of the erase operations corresponding from small to large;
an update parameter storage step of storing update parameters in a specific memory area of the nonvolatile memory for each of the N dynamic trigger points; and
a flag cell defining step of defining, for each of the N dynamic trigger points, a corresponding flag cell in the nonvolatile memory, the flag cell being initially unprogrammed;
and a parameter updating step of, after each time the erasing operation is completed, being executed in the nonvolatile memory, judging, one by one, for each dynamic trigger point, whether the total number of times of the erasing operation that has been completed is greater than or equal to the specific number of times of the erasing operation that corresponds to the dynamic trigger point and whether a flag cell that corresponds to the dynamic trigger point is programmed, in an order from the nth dynamic trigger point to the first dynamic trigger point in which, when it is judged that one dynamic trigger point appears such that the total number of times of the erasing operation that has been completed is greater than or equal to the specific number of times of the erasing operation that corresponds to the one dynamic trigger point and the flag cell that corresponds to the one dynamic trigger point is not programmed, using the parameter for updating the nonvolatile memory parameter and programming the flag cell that corresponds to the one dynamic trigger point, and ending the parameter updating step, and if it is judged that the specific number of times of the erasing operation that corresponds to the N dynamic trigger points is greater than the total number of times of the erasing operation that has been completed and/or the flag cell that corresponds to the N dynamic trigger points is ended.
In one embodiment of the present invention, the control method further includes:
and a post-power-on updating step of determining, one by one, whether a flag cell corresponding to an nth dynamic trigger point is programmed for each dynamic trigger point in the sequence from the nth dynamic trigger point to a first dynamic trigger point, if it is determined that one flag cell is programmed, selecting an update parameter corresponding to a dynamic trigger point corresponding to the one flag cell for updating the nonvolatile memory parameter, and if it is determined that none of the flag cells corresponding to the N dynamic trigger points is programmed, updating the nonvolatile memory parameter using an initial parameter of the nonvolatile memory.
In another embodiment of the present invention to solve the above-described problems, there is provided a control method for controlling a nonvolatile memory parameter, including:
a dynamic trigger point defining step of setting N dynamic trigger points in which each of the N dynamic trigger points corresponds to a specific number of erase operations of the nonvolatile memory, wherein N is a positive integer greater than or equal to 1;
an update parameter storage step of storing update parameters in a specific memory area of the nonvolatile memory for each of the N dynamic trigger points; and
a flag cell defining step of defining, for each of the N dynamic trigger points, a corresponding flag cell in the nonvolatile memory, the flag cell being initially unprogrammed;
and a parameter updating step of, after each time the erasing operation is completed, being executed in the nonvolatile memory, determining, for one or more dynamic trigger points for which the corresponding flag cell of the N dynamic trigger points is not programmed, whether or not the total number of times of the erasing operation that has been completed is greater than or equal to a specific number of times of the erasing operation corresponding to one of the one or more dynamic trigger points, and if the total number of times of the erasing operation that has been completed is greater than or equal to a specific number of times of the erasing operation corresponding to one of the one or more dynamic trigger points, using an update parameter corresponding to the one dynamic trigger point for updating the nonvolatile memory parameter and programming the flag cell corresponding to the one dynamic trigger point.
In one embodiment of the present invention, the control method further includes:
and a power-on-after-power-off updating step, which is executed under the condition that the nonvolatile memory is powered off and then powered on, and in the power-on-power-off updating step, determining whether a dynamic trigger point of which the corresponding mark unit is programmed exists in the N dynamic trigger points, if the dynamic trigger point of which the corresponding mark unit is programmed exists in the N dynamic trigger points, selecting the dynamic trigger point of which the specific erasing operation frequency is the largest in the dynamic trigger points of which the corresponding mark unit is programmed for updating the nonvolatile memory parameter, and if the dynamic trigger point of which the corresponding mark unit is not programmed exists in the N dynamic trigger points, updating the nonvolatile memory parameter by using the initial parameter of the nonvolatile memory.
In one embodiment of the present invention, in the control method, the N dynamic trigger points are stored in a specific cell area of the nonvolatile memory.
In one embodiment of the present invention, in the control method, the N dynamic trigger points are stored in one block in the specific cell area.
In one embodiment of the present invention, in the control method, the update parameter corresponding to each of the N dynamic trigger points is stored on one page of the one block, and the initial parameter of the nonvolatile memory is stored on one page of the one block.
In one embodiment of the present invention, in the control method, each of the flag cells corresponding to the N dynamic trigger points is stored in a specific cell area of the nonvolatile memory, and each flag cell is spaced apart by a certain distance.
In still another embodiment of the present invention that solves the above-mentioned problems, there is provided a nonvolatile memory storing computer instructions that, when executed by a processing section, perform the above-mentioned control method for the nonvolatile memory.
In still another embodiment of the present invention that solves the above-mentioned problems, there is provided a computer system including:
a computer storage medium having stored thereon computer instructions;
a nonvolatile memory; and
and a processing unit configured to perform the control method on the nonvolatile memory when the computer instructions are executed.
Effects of the invention
According to the present invention, by changing the operating condition of the nonvolatile memory after a specific number of P/E cycles, the P/E cycle performance of the nonvolatile memory can be improved.
Drawings
Fig. 1 is a diagram showing an ISPP process in a nonvolatile memory.
Fig. 2 is a diagram showing an ISPE process in a nonvolatile memory.
FIG. 3 is a schematic diagram showing the relationship between programming time and P/E cycle time as a function of P/E cycle number in the prior art.
FIG. 4 is a schematic diagram showing the relationship between erase time and P/E cycle time as a function of P/E cycle number in the prior art.
FIG. 5 is a schematic diagram illustrating the contents of a "bias" condition in a programming mode according to one embodiment of the invention.
Fig. 6 is a schematic diagram showing the contents of the "bias" condition in the erase mode according to one embodiment of the present invention.
Fig. 7 is a diagram showing one example of a special area for managing a nonvolatile memory according to one embodiment of the present invention.
Fig. 8 is a diagram showing one example of information in a CNF block in a nonvolatile memory according to one embodiment of the present invention.
Fig. 9 is a diagram showing one example of a flag cell in a dyn_pt_on flag block in a nonvolatile memory according to one embodiment of the present invention.
FIG. 10 is a flow chart illustrating dynamic trigger point control during operation according to one embodiment of the invention.
FIG. 11 is a flow chart illustrating dynamic trigger point control after power-up after power-down in accordance with one embodiment of the present invention.
FIG. 12 is a schematic diagram illustrating the relationship between programming time and P/E cycle time as a function of P/E cycle number according to one embodiment of the invention.
FIG. 13 is a schematic diagram illustrating the relationship between erase time and P/E cycle time as a function of P/E cycle number in accordance with one embodiment of the present invention.
Fig. 14 is a flowchart illustrating a control method for controlling the "bias" condition of a nonvolatile memory according to one embodiment of the present invention.
Fig. 15 is a flowchart showing a control method for controlling the "bias" condition of the nonvolatile memory according to one present embodiment of the present invention.
FIG. 16 is a block diagram illustrating a non-volatile memory in which "bias" condition control is performed, according to one embodiment of the invention.
FIG. 17 is a block diagram illustrating a computer system in which "bias" condition control is performed, according to one embodiment of the invention.
Detailed Description
Embodiments of the invention may be understood by reference to the exemplary embodiments depicted in the drawings (embodiments of the invention briefly summarized above and discussed in more detail below). The drawings, however, illustrate only typical embodiments of the invention and are therefore not to be considered limiting of its scope, for the principles may admit to other equally effective embodiments.
For ease of understanding, the same reference numbers are used in the various figures to denote the same elements in common in the figures. The drawings are not to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation.
Example 1 ]
Hereinafter, a control method for controlling parameters of a nonvolatile memory according to an embodiment of the present invention will be described with reference to fig. 5 to 13.
In a nonvolatile memory, there are a number of parameter data within the chip of the memory that are used to control the configuration and/or operation of the nonvolatile memory, and the collection of these parameter data is generally referred to as a "bias" condition. Fig. 5 and 6 show examples of the "bias" condition in the program mode and the "bias" condition in the erase mode, respectively. Among other things, as can be seen from FIG. 5, the "bias" conditions in the programming mode include various operating parameters of the ISPP process (e.g., pre-program pulse, start voltage, maximum voltage, delta step, pulse before erase failure, program pulse time, etc.), and verify levels, etc. As can be seen from fig. 6, the "bias" condition in erase mode includes various operating parameters of the ISPE process (e.g., pre-program pulse, start voltage, maximum voltage, delta step, pulse before erase failure, program pulse time, etc.), and verify level, etc. With these "bias" conditions, the operation of the nonvolatile memory in the P/E cycle can be adjusted.
Thus, we can adjust the "bias" condition (e.g., increase erase time or decrease erase time) after a particular number of P/E cycles have been completed. The specific number of P/E cycles for performing the erase operation may be calculated by the number of ISPE processes (hereinafter, abbreviated as ISPE sequence number). Thus, we can use the current ISPE sequence number of the memory to know how many P/E cycles have been performed. Based on this information, we can change the "bias" condition to control the P/E loop operation.
Fig. 14 shows a flowchart of a control method for controlling the "bias" condition of the nonvolatile memory of the present embodiment.
At step S1401, based on sufficient test results for the non-volatile memory, one or more particular ISPE sequence numbers may be determined, and the "bias" condition may be appropriately changed during the P/E operation to improve the P/E cycle operation whenever the number of ISPEs reaches the one or more particular ISPE sequence numbers. The one or more specific ISPE sequence numbers may be referred to as dynamic trigger points.
At step S1402, N configuration Control (CNF) registers (N is a positive integer greater than or equal to 1, corresponding to the number of dynamic trigger points) may be defined in the non-volatile memory for one or more dynamic trigger points as described above. Each dynamic trigger point corresponds to a CNF register. Each CNF register has stored therein a value of the dynamic trigger point corresponding thereto. The N CNF registers are denoted by cnfdyn_x_det, where X is a positive integer less than or equal to N and greater than or equal to 1, representing the number of the CNF registers. Alternatively, the CNF register may be set after the chip test is completed. N dynamic trigger points can be arranged in order from small to large according to the specific erasing times corresponding to the dynamic trigger points. For example, the dynamic trigger point with the minimum number of corresponding specific erasures is set as the 1 st trigger point, and corresponds to the first CNF register cnfdyn_1_det; setting the second smallest dynamic trigger point of the corresponding specific erasing times as a 2 nd trigger point, corresponding to a second CNF register CNFDYN_2_DET; … …; the corresponding dynamic trigger point with the largest specific erasing times is set as the N trigger point and corresponds to the N CNF register CNFDYN_N_DET. Each CNF register has stored therein a corresponding "bias" condition for updating the configuration of the memory.
As an example of setting of the dynamic trigger point, for example, initially (0K P/E cycle), the ISPE sequence number to complete the erase operation is 2; after the 20K P/E loop, the ISPE sequence number to complete the erase operation is 4, setting CNFDYN_1_DET to 4 (the first dynamic trigger point); after the 40K P/E loop, the ISPE sequence number to complete the erase operation is 6, CNFDYN_2_DET is set to 6 (the second dynamic trigger point); … …; by analogy, after a 100K P/E loop, the ISPE sequence number to complete the erase operation is 10, setting CNFDYN_N_DET to 10 (the N-th dynamic trigger point).
At step S1403, for each of the N dynamic trigger points, one flag cell is defined in a specific storage area of the nonvolatile memory, and N flag cells in total are defined. Each dynamic trigger point corresponds to a flag cell. The N flag cells may be represented by dyn_x_pt_on, where X is a positive integer less than or equal to N and greater than or equal to 1, representing the number of the CNF register. The N flag cells are initially unprogrammed. If the number of times of the completed ISPE process of the current memory (hereinafter, abbreviated as the current memory ISPE sequence number) exceeds the value of a certain dynamic trigger point, the flag cell corresponding to the dynamic trigger point may be programmed to be used for knowing the state of the current P/E cycle. Based on sufficient test results for the non-volatile memory, a changed "bias" condition may be defined for each dynamic trigger point for updating or adjusting the operation of the non-volatile memory. As one example, the operation of the non-volatile memory may be adjusted by changing the "bias" condition of the non-volatile memory in the following manner: for the programming process, changing the starting voltage, maximum voltage, delta step, programming pulse time, etc., such that the programming time is lower than before; and/or for the erase process, the start voltage, maximum voltage, delta steps, erase pulse time, etc. are changed such that the erase time is higher than before.
The storage, setting, content, operation and the like for the CNF register and the flag unit in steps S1401 to S1403 are described in more detail below.
For example, one or more specific memory cell regions may be defined in the non-volatile memory for storing the CNF registers and the tag units. Fig. 7 shows an example for managing 2 specific memory cell areas storing CNF registers and tag units. The upper side of fig. 7 shows the internal storage structure of the memory. The lower side of fig. 7 shows the function of the internal memory structure. In general, a nonvolatile memory device may include a memory cell array. The memory cell array may have many blocks, and each block may have many pages. A block may be defined as a minimum unit of erase required to perform an erase operation on data stored in a memory cell. A block may comprise, for example, 16 pages or 32 pages. A main memory cell array (simply referred to as a main array) may be used for a user's application. In a cell region of memory other than the main array, a first specific memory cell region (e.g., 1 block) may be defined for storing the CNF register, and a second specific memory cell region (e.g., 1 block or 1 page) may be defined for storing the tag unit. In this example, it may be set that the first specific memory cell and the second specific memory cell are each 1 block, and the first specific memory cell region may be referred to as a CNF block and the second specific memory cell region may be referred to as a dyn_pt_on flag block.
Fig. 8 shows one example of Content Addressable Memory (CAM) information in the CNF block in the above example. The Content Addressable Memory (CAM) refers to a special area for writing configuration values related to various operations of the memory. Initially, the N CNF registers have default values, and during a Power On Reset (POR) time, the user can set the values of the CNF registers by CAM reading. During the POR time, these data can be read and various operation-related configurations set. Thus, we can set N CNF registers to write the target value into the CAM area.
Fig. 9 shows one example of information of a flag cell in the dyn_pt_on flag block in the above example. How many P/E cycles have been performed can be known from the tag units in the DYN_PT_ON tag block. Each flag cell will be programmed individually. Preferably, the marking units are separated by a certain distance within the dyn_pt_on marking block. The distance in the example of fig. 9 is 32 columns.
In order to operate the device correctly, configuration data ("bias" conditions) for various types of operations of the nonvolatile memory may be set according to the test results. Each memory device may have different configuration data. These configuration data may be stored within the CNF block. During the POR time, the memory device downloads configuration data from the CNF block and uses the configuration data to set configuration registers associated with various operations of the memory. Thus, by checking the tag unit, these configuration data can be downloaded to update the configuration of the memory according to the current P/E cycle time.
After each erase operation of the memory is completed, at step S1404, the current memory ISPE sequence number may be compared with the value of each dynamic trigger point, whether the flag cell corresponding to each dynamic trigger point has been programmed is determined, and the "bias" condition of the memory is updated based on the results of the above comparison and determination. As one example, the process of comparison, judgment, and update in this step S1404 may be as shown in fig. 10. Preferably, as shown in fig. 10, the value of each dynamic trigger point (corresponding to a specific number of erase operations) is compared with the current memory ISPE sequence number in order from the nth trigger point (cnfdyn_n_det) to the first trigger point (cnfdyn_1_det). If the current ISPE sequence number exceeds a certain dynamic trigger point (assuming that the current ISPE sequence number is the Y-th dynamic trigger point, Y is a positive integer less than or equal to N and greater than or equal to 1), the flag cell (dyn_y_pt_on) corresponding to the dynamic trigger point may be programmed. And, for the dynamic trigger point, the corresponding configuration parameters (e.g., the Y-th page data) in the CNF block are downloaded, and the values of CNF registers corresponding to the various operations are updated to accommodate the corresponding "bias" condition (Y-th bias "condition). Thereafter, the step ends.
On the other hand, if it is determined that the values of the N dynamic trigger points are all greater than the current ISPE sequence number of the memory and/or the flag cells corresponding to the N dynamic trigger points are all programmed, the "bias" adjustment is not changed, and the step is ended.
Optionally, the control method further includes step S1405. Step S1405 may be performed with the nonvolatile memory powered off and then powered on. As an example, the process of this step S1405 may be as shown in fig. 11. At step S1405, first, a flag cell in the dyn_pt_on flag block may be checked. Preferably, the comparison is performed by judging the current memory ISPE sequence number in order from the nth trigger point (cnfdyn_n_det) to the first trigger point (cnfdyn_1_det). If a certain flag cell (assuming that the Z flag cell is the Z-th flag cell, Z is a positive integer less than or equal to N and greater than or equal to 1) is programmed, corresponding configuration data can be downloaded for the dynamic trigger point corresponding to the flag cell, and various CNF register values can be updated to adapt to the corresponding "bias" condition (Z-th bias "condition). If all of the flag cells are in the erased state, page 0 data in the CNF block may be downloaded for the initial CNF value and all kinds of CNF register values updated to accommodate the initial "offset" condition.
Fig. 12 shows the ratio of the program time to the P/E cycle of the nonvolatile memory using the control method of the present embodiment as a function of the number of P/E cycles. As can be seen from fig. 12, the programming time is nearly the same during the 0K to 100K P/E cycle time. Fig. 13 shows the ratio of the erasing time to the P/E cycle of the nonvolatile memory using the control method of the present embodiment as a function of the number of P/E cycles. As can be seen from fig. 13, the erase time is nearly the same during the 0K to 100K P/E cycle time. This means that the non-volatile memory cells are not subjected to any stress during P/E operation.
Therefore, it can be appreciated that with the control method of the present embodiment, the operating conditions of the nonvolatile memory can be changed, thereby improving the performance of the P/E cycle.
Example 2 ]
Hereinafter, a control method for controlling the "bias" condition of the nonvolatile memory according to the present embodiment will be described with reference to fig. 15.
Fig. 15 is a flowchart showing a control method for controlling the "bias" condition of the nonvolatile memory according to the present embodiment.
At step S1501, based on sufficient test results for the non-volatile memory, one or more particular ISPE sequence numbers may be determined, and the "bias" condition may be appropriately changed during P/E operations to improve P/E cycle operation whenever the number of ISPEs reaches the one or more particular ISPE sequence numbers. The one or more specific ISPE sequence numbers may be referred to as dynamic trigger points. For example, N dynamic trigger points may be set, where N is a positive integer greater than or equal to 1.
At step S1502, N update "bias" conditions corresponding one-to-one to the N dynamic trigger points may be stored in non-volatile memory (e.g., in one or more blocks and/or one or more pages of memory) for one or more dynamic trigger points as described above. The update bias condition is used to update configuration parameters corresponding to various operations of the memory. These configuration data may be stored within one or more blocks of memory, or one or more pages.
At step S1503, for each of the N dynamic trigger points, one corresponding flag cell is defined in the non-volatile memory (e.g., in one or more blocks and/or one or more pages of memory), for a total of N flag cells. Each dynamic trigger point corresponds to a flag cell. The N flag cells are initially unprogrammed.
After the non-volatile memory completes the erase operation each time, at step S1504, for one or more dynamic trigger points that are not programmed by the corresponding flag cells of the N dynamic trigger points, it is determined whether the current memory ISPE sequence number is greater than or equal to the specific erase operation count corresponding to one of the N dynamic trigger points, and if the current memory ISPE sequence number is greater than or equal to the specific erase operation count corresponding to one of the N dynamic trigger points (assuming that Y is a Y-th dynamic trigger point, Y is a positive integer that is less than or equal to N and greater than or equal to 1), the update parameter ("bias" condition) corresponding to the one dynamic trigger point (Y-th dynamic trigger point) is used to update the configuration parameter of the non-volatile memory, and the flag cell (Y-th flag cell) corresponding to the one dynamic trigger point (Y-th dynamic trigger point) is programmed.
Optionally, the control method of the present embodiment further includes step S1505, which is performed in a case where the nonvolatile memory is powered off and then powered on. In this step, it is determined whether there is a dynamic trigger point in which a corresponding flag cell is programmed among N dynamic trigger points, and if it is determined that there is a dynamic trigger point in which a corresponding flag cell is programmed among the N dynamic trigger points (assuming that there are M dynamic trigger points in which a flag cell is programmed, M is a positive integer less than or equal to N and greater than or equal to 1), a dynamic trigger point corresponding to the dynamic trigger point in which the corresponding flag cell is programmed (M dynamic trigger points) having the largest number of specific erase operations is selected, and the configuration parameters of the nonvolatile memory are updated using the "bias" condition corresponding to the dynamic trigger point. If it is determined that there is no corresponding dynamic trigger point of the N dynamic trigger points for which the flag cells are programmed, the configuration parameters of the nonvolatile memory are updated using the initial parameters of the nonvolatile memory.
In certain embodiments, operations in the methods of the embodiments described above may occur simultaneously, substantially simultaneously, or in a different order than shown in the figures. The methods, operations of the processes, and combinations of operations may be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
All or part of the operations involved in embodiments of the present invention may optionally be performed automatically by a program. In one example, the invention may be implemented as a program product stored on a computer readable storage medium for use with a computer system. The program(s) of the program product include the functions of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) Non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM machine, flash memory, ROM chips or any type of solid state non-volatile semiconductor memory) on which information is permanently stored; and (ii) a writable storage medium (e.g., a disk storage or hard disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. Such computer-readable storage media, when carrying computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present invention.
Example 3 ]
Hereinafter, a nonvolatile memory in which the "bias" condition of the nonvolatile memory is controlled will be described with reference to fig. 16.
Fig. 16 is a block diagram showing a nonvolatile memory in which "bias" condition control is performed according to the present embodiment. The nonvolatile memory 1601 according to the present embodiment may be a nonvolatile memory such as EEPROM, EAROM, PROM, EPROM or a flash memory. The memory includes a storage area 1602 and a processing section 1603. The storage area 1602 is a portion for storing various types of memory parameters and user data information. The processing section 1603 may control the storage area 1602 automatically or upon receiving a signal from an external computing device (e.g., a computer or a communication terminal, etc.). The processing unit 1603 may be, for example, a semiconductor chip or the like in a nonvolatile memory. The processing section 1603 may execute the control method for controlling the "bias" condition of the nonvolatile memory as described in the above-described embodiment 1 and/or embodiment 2, or a method in which the control methods in the embodiment 1 and the embodiment 2 are partially combined, thereby controlling the storage area 1602 of the nonvolatile memory to improve the P/E cycle of the nonvolatile memory. Related update "bias" parameters, dynamic trigger points, and/or flag cells may be stored in the storage area 1602.
Example 4 ]
Hereinafter, a computer system in which the "bias" condition of the nonvolatile memory is controlled will be described with reference to fig. 17.
Fig. 17 is a block diagram showing a computer system in which "bias" condition control is performed according to the present embodiment. The computer system 1701 may include a memory 1702 and a processing portion 1703. The memory 1702 may be a nonvolatile memory such as EEPROM, EAROM, PROM, EPROM, flash memory, or the like. The processing portion 1702 may control the memory 1702 automatically or upon receiving signals from outside (e.g., via wireless transmission) or from inside (e.g., from other circuitry or components within the computer system 1701). As an example, the processing section 1703 may include an ASIC (Application Specific Integrated Circuit: application specific integrated circuit), an IC (Integrated Circuit: integrated circuit), a DSP (Digital Signal Processor: digital signal processor), an FPGA (Field Programmable Gate Array: field programmable gate array), various logic circuits, various signal processing circuits, and the like. The processing unit 1703 may perform the control method for controlling the "bias" condition of the nonvolatile memory as described in the above-described embodiment 1 and/or embodiment 2, or the method obtained by partially combining the control methods in the embodiment 1 and embodiment 2, thereby controlling the memory 1702 to improve the P/E cycle of the memory 1702.
The update "bias" parameters, dynamic trigger points, and/or flag elements related to control of the memory 1702 may be stored in the memory 1702, other storage devices in the computer system 1701, and/or external storage devices, which other storage devices in the computer system 1701 may be computer readable storage media including, but not limited to: (i) Non-writable storage media (e.g., read-only memory devices within a computer such as CD-ROM disks readable by a CD-ROM machine, flash memory, ROM chips or any type of solid state non-volatile semiconductor memory) on which information is permanently stored; and (ii) a writable storage medium (e.g., a disk storage or hard disk drive or any type of solid-state random-access semiconductor memory) on which alterable information is stored. The external storage device may be the same as or similar to the memory 1702 or other storage devices in the computer system 1701, or may be a cloud, a remote storage device, a remote server, or the like, which communicates with the processing unit 1703. The storage 1702 or the storage device transmits the computer instructions to the processing unit 1703 or receives signals such as feedback signals from the processing unit 1703 via wireless communication, wired communication, or the like.
The foregoing describes in detail alternative embodiments of the present invention. It will be appreciated that various embodiments and modifications may be resorted to without departing from the broad spirit and scope of the invention. Many modifications and variations will be apparent to those of ordinary skill in the art in light of the concepts of the invention without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by a person skilled in the art according to the inventive concept shall fall within the scope of protection defined by the claims of the present invention.
Claims (10)
1. A control method for controlling parameters of a nonvolatile memory, comprising:
a dynamic trigger point defining step of setting N dynamic trigger points in which each of the N dynamic trigger points corresponds to a specific number of erase operations of the nonvolatile memory, wherein N is a positive integer greater than or equal to 1, and the N dynamic trigger points are arranged from 1 to N in order of the specific number of erase operations corresponding from small to large;
an update parameter storage step of storing update parameters in a specific memory area of the nonvolatile memory for each of the N dynamic trigger points;
a flag cell defining step of defining, for each of the N dynamic trigger points, a corresponding flag cell in the nonvolatile memory, the flag cell being initially unprogrammed; and
and a parameter updating step of, after each time the erasing operation is completed, being executed in the nonvolatile memory, judging, one by one, for each dynamic trigger point, whether the total number of times of the erasing operation that has been completed is greater than or equal to the specific number of times of the erasing operation that corresponds to the dynamic trigger point and whether a flag cell that corresponds to the dynamic trigger point is programmed, in an order from the nth dynamic trigger point to the first dynamic trigger point in which, when it is judged that one dynamic trigger point appears such that the total number of times of the erasing operation that has been completed is greater than or equal to the specific number of times of the erasing operation that corresponds to the one dynamic trigger point and the flag cell that corresponds to the one dynamic trigger point is not programmed, using the parameter for updating the nonvolatile memory parameter and programming the flag cell that corresponds to the one dynamic trigger point, and ending the parameter updating step, and if it is judged that the specific number of times of the erasing operation that corresponds to the N dynamic trigger points is greater than the total number of times of the erasing operation that has been completed and/or the flag cell that corresponds to the N dynamic trigger points is ended.
2. The control method as set forth in claim 1, further comprising:
and a post-power-on updating step of determining, one by one, whether a flag cell corresponding to an nth dynamic trigger point is programmed for each dynamic trigger point in the sequence from the nth dynamic trigger point to a first dynamic trigger point, if it is determined that one flag cell is programmed, selecting an update parameter corresponding to a dynamic trigger point corresponding to the one flag cell for updating the nonvolatile memory parameter, and if it is determined that none of the flag cells corresponding to the N dynamic trigger points is programmed, updating the nonvolatile memory parameter using an initial parameter of the nonvolatile memory.
3. A control method for controlling parameters of a nonvolatile memory, comprising:
a dynamic trigger point defining step of setting N dynamic trigger points in which each of the N dynamic trigger points corresponds to a specific number of erase operations of the nonvolatile memory, wherein N is a positive integer greater than or equal to 1;
an update parameter storage step of storing update parameters in a specific memory area of the nonvolatile memory for each of the N dynamic trigger points;
a flag cell defining step of defining, for each of the N dynamic trigger points, a corresponding flag cell in the nonvolatile memory, the flag cell being initially unprogrammed; and
and a parameter updating step of, after each time the erasing operation is completed, being executed in the nonvolatile memory, determining, for one or more dynamic trigger points for which the corresponding flag cell of the N dynamic trigger points is not programmed, whether or not the total number of times of the erasing operation that has been completed is greater than or equal to a specific number of times of the erasing operation corresponding to one of the one or more dynamic trigger points, and if the total number of times of the erasing operation that has been completed is greater than or equal to a specific number of times of the erasing operation corresponding to one of the one or more dynamic trigger points, using an update parameter corresponding to the one dynamic trigger point for updating the nonvolatile memory parameter and programming the flag cell corresponding to the one dynamic trigger point.
4. The control method according to claim 3, characterized by further comprising:
and a power-on-after-power-off updating step, which is executed under the condition that the nonvolatile memory is powered off and then powered on, and in the power-on-power-off updating step, determining whether a dynamic trigger point of which the corresponding mark unit is programmed exists in the N dynamic trigger points, if the dynamic trigger point of which the corresponding mark unit is programmed exists in the N dynamic trigger points, selecting the dynamic trigger point of which the specific erasing operation frequency is the largest in the dynamic trigger points of which the corresponding mark unit is programmed for updating the nonvolatile memory parameter, and if the dynamic trigger point of which the corresponding mark unit is not programmed exists in the N dynamic trigger points, updating the nonvolatile memory parameter by using the initial parameter of the nonvolatile memory.
5. The control method according to any one of claims 1 to 4, characterized in that the N dynamic trigger points are stored in a specific cell area of the nonvolatile memory.
6. The control method of claim 5, wherein the N dynamic trigger points are stored in one block in the specific cell area.
7. The control method according to claim 6, wherein the update-use parameter corresponding to each of the N dynamic trigger points is stored on one page in the one block, and the initial parameter of the nonvolatile memory is stored on one page in the one block.
8. The control method according to any one of claims 1 to 4, wherein each of the flag cells corresponding to the N dynamic trigger points is stored in a specific cell area of the nonvolatile memory with a distance therebetween.
9. A nonvolatile memory in which computer instructions are stored, which when executed by a processing section performs the control method according to any one of claims 1 to 4 on the nonvolatile memory.
10. A computer system, comprising:
a computer storage medium having stored thereon computer instructions;
a nonvolatile memory; and
a processing section that, when executing the computer instructions, performs the control method according to any one of claims 1 to 4 on the nonvolatile memory.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102609403A (en) * | 2011-01-26 | 2012-07-25 | 微软公司 | Formatting data by example |
| CN102985976A (en) * | 2010-04-18 | 2013-03-20 | 桑迪士克技术有限公司 | Programming non-volatile storage includng reducing impact from other memory cells |
| CN103578552A (en) * | 2012-08-10 | 2014-02-12 | 三星电子株式会社 | Nonvolatile memory device and operating method with variable memory cell state definitions |
| CN103810443A (en) * | 2013-11-13 | 2014-05-21 | 威盛电子股份有限公司 | Device and method for protecting basic input and output system |
| CN104011800A (en) * | 2011-12-28 | 2014-08-27 | 英特尔公司 | Cycling endurance extending for memory cells of a non-volatile memory array |
| CN105340020A (en) * | 2013-07-16 | 2016-02-17 | 英特尔公司 | Erase management in memory systems |
| CN109918323A (en) * | 2019-02-28 | 2019-06-21 | 苏州浪潮智能科技有限公司 | Data signals acquisition method, device, equipment and storage medium in integrated circuit |
| CN110955611A (en) * | 2018-09-27 | 2020-04-03 | 爱思开海力士有限公司 | Memory system and operating method thereof |
-
2021
- 2021-02-09 CN CN202110178558.9A patent/CN112908392B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102985976A (en) * | 2010-04-18 | 2013-03-20 | 桑迪士克技术有限公司 | Programming non-volatile storage includng reducing impact from other memory cells |
| CN102609403A (en) * | 2011-01-26 | 2012-07-25 | 微软公司 | Formatting data by example |
| CN104011800A (en) * | 2011-12-28 | 2014-08-27 | 英特尔公司 | Cycling endurance extending for memory cells of a non-volatile memory array |
| CN103578552A (en) * | 2012-08-10 | 2014-02-12 | 三星电子株式会社 | Nonvolatile memory device and operating method with variable memory cell state definitions |
| CN105340020A (en) * | 2013-07-16 | 2016-02-17 | 英特尔公司 | Erase management in memory systems |
| CN103810443A (en) * | 2013-11-13 | 2014-05-21 | 威盛电子股份有限公司 | Device and method for protecting basic input and output system |
| CN110955611A (en) * | 2018-09-27 | 2020-04-03 | 爱思开海力士有限公司 | Memory system and operating method thereof |
| CN109918323A (en) * | 2019-02-28 | 2019-06-21 | 苏州浪潮智能科技有限公司 | Data signals acquisition method, device, equipment and storage medium in integrated circuit |
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|---|---|
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