CN112887093A - Hardware acceleration system and method for implementing cryptographic algorithms - Google Patents
Hardware acceleration system and method for implementing cryptographic algorithms Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
Abstract
The application provides a hardware acceleration system and a method for realizing a cryptographic algorithm, wherein the system comprises a hardware acceleration end and a host end, wherein the hardware acceleration end comprises a plurality of hardware acceleration modules, and each hardware acceleration module in the plurality of hardware acceleration modules is formed by combining editable hardware logic units and is used for realizing a preset cryptographic algorithm; the host side is used for providing an application program interface for an upper application program so as to receive data to be processed through the application program interface; the host terminal is also used for carrying out calculation power splitting according to the current application scene, controlling the working state of a hardware acceleration module on the hardware acceleration terminal based on the calculation power splitting result and loading data to be processed to the hardware acceleration module; the hardware acceleration module is used for executing cryptographic algorithm operation on the data to be processed to obtain processing result data and returning the processing result data to the host. The scheme can effectively improve the flexibility and the function richness of the hardware acceleration system.
Description
Technical Field
The present application relates to the field of cryptography, and in particular, to a hardware acceleration system and method for implementing a cryptographic algorithm.
Background
With the rapid development of the internet industry and the artificial intelligence industry, the application scenes of various technologies are continuously expanded, and the generation and the acquisition of the daily data are accompanied. Privacy protection is also increasingly gaining importance as an important attribute of data use, especially in the era where new technology applications such as cloud computing and big data are rapidly rising. However, key information can often be obtained from massive data through data mining technology, which poses a serious threat to privacy protection of both enterprises and individuals. Therefore, there is a great demand for privacy protection, the cryptographic technique is the core technique and the basic support of privacy protection, and the key operation of the cryptographic algorithm is finite field operation. In order to ensure safety, the operation is generally large integer operation, belongs to calculation intensive operation, has very large demand on calculation force, and a general CPU (central processing unit) cannot meet related demands. In sum, performance has become the largest bottleneck among them. To meet the relevant performance requirements, hardware acceleration has been increasingly used as one of the most important types of methods, including the use of FPGAs and GPUs. The hardware acceleration has various characteristics of high concurrency, low time delay, controllable pipelining and the like, but the addition and use of the hardware greatly reduces indexes of a system of pure software in the past in the aspects of coupling, robustness and flexibility, great inconvenience is brought to a user, and finally the use scene of the hardware acceleration is greatly narrowed.
At present, the hardware acceleration of cryptography belongs to the frontier field, various methods are relatively small, diversified and mostly in the primary stage, basically, data are directly input to relevant hardware acceleration equipment through a relevant driving interface, and after the data are processed on the hardware acceleration equipment, a processing result is returned to the driving interface through a relevant hardware connecting passage for a user to obtain. These hardware acceleration schemes are relatively single in function and lack flexibility.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the application provides a hardware acceleration system and a method for realizing a cryptographic algorithm, so as to solve the problems of single function and lack of flexibility of cryptographic hardware acceleration in the prior art.
The embodiment of the application provides a hardware acceleration system for realizing a cryptographic algorithm, which comprises a hardware acceleration end and a host end, wherein the hardware acceleration end comprises a plurality of hardware acceleration modules, and each hardware acceleration module in the plurality of hardware acceleration modules is formed by combining editable hardware logic units and is used for realizing a preset cryptographic algorithm; the host side is used for providing an application program interface for an upper application program so as to receive data to be processed through the application program interface; the host terminal is also used for carrying out calculation power splitting according to the current application scene, switching on and off a hardware acceleration module on the hardware acceleration terminal based on a calculation power splitting result, and loading data to be processed to the hardware acceleration module; the hardware acceleration module is used for executing cryptographic algorithm operation on the data to be processed to obtain processing result data.
The embodiment of the present application further provides a hardware acceleration method for implementing a cryptographic algorithm, where the method is applied to a hardware acceleration system for implementing a cryptographic algorithm, the hardware acceleration system includes a host and a hardware acceleration end, the hardware acceleration end includes a plurality of hardware acceleration modules, and the method includes: the host receives data to be processed through an application program interface; the host computer end carries out calculation power splitting according to the current application scene, controls the working state of a hardware acceleration module on the hardware acceleration end based on the calculation power splitting result, and loads data to be processed to the hardware acceleration module on the hardware acceleration end; the hardware acceleration module executes cryptographic algorithm operation on the data to be processed to obtain processing result data, and returns the processing result data to the host.
In the embodiment of the application, a hardware acceleration system for implementing a cryptographic algorithm is provided, the system includes a hardware acceleration end and a host end, the hardware acceleration end may include a plurality of hardware acceleration modules, each hardware acceleration module in the plurality of hardware acceleration modules may be formed by combining editable hardware logic units, for realizing the preset cryptographic algorithm, the host end can provide an application program interface for an upper application program, the host computer end can also carry out calculation force splitting according to the current application scene so as to receive the data to be processed through the application program interface, control the working state of a hardware acceleration module on the hardware acceleration end based on the calculation force splitting result, and loading the data to be processed to a hardware acceleration module, wherein the hardware acceleration module can execute cryptographic algorithm operation on the data to be processed to obtain processing result data, and returning the processing result data to the host terminal. In the above scheme, an application program interface is provided for an upper application program through a host end to receive data to be processed, and the host end and a hardware acceleration end are arranged in the same frame system, so that developers can use the hardware acceleration module without threshold, compatibility of each development environment is ensured, the host end can also control the working state of the hardware acceleration module according to the current application scene, the host end can automatically switch various modules according to client setting, flexibility of the system is improved, in addition, the hardware acceleration end comprises a plurality of hardware acceleration modules, each hardware acceleration module is used for realizing a preset cryptographic algorithm, the data to be processed are loaded to different hardware acceleration modules, different cryptographic algorithm operations can be executed, the system can be suitable for different application scenes, and functions are rich. By means of the technical scheme, the technical problems that the cryptology hardware acceleration function is single and the flexibility is poor in the prior art are solved, and the technical effects of effectively improving the flexibility and the function richness of a hardware acceleration system are achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application, are incorporated in and constitute a part of this application, and are not intended to limit the application. In the drawings:
FIG. 1 is a diagram illustrating a hardware acceleration system for implementing a cryptographic algorithm in one embodiment of the present application;
FIG. 2 is a diagram illustrating a hardware acceleration system for implementing a cryptographic algorithm in an embodiment of the present application;
FIG. 3 is a flow chart illustrating a hardware acceleration method for implementing a cryptographic algorithm according to an embodiment of the present application;
fig. 4 is a schematic flowchart illustrating an overall hardware acceleration method for implementing a cryptographic algorithm according to an embodiment of the present application.
Detailed Description
The principles and spirit of the present application will be described with reference to a number of exemplary embodiments. It should be understood that these embodiments are given solely for the purpose of enabling those skilled in the art to better understand and to practice the present application, and are not intended to limit the scope of the present application in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The embodiment of the application provides a hardware acceleration system for realizing a cryptographic algorithm. Fig. 1 is a schematic diagram of a hardware acceleration system for implementing a cryptographic algorithm according to an embodiment of the present application. Specifically, as shown in fig. 1, a hardware acceleration system for implementing a cryptographic algorithm provided by an embodiment of the present application may include: a hardware acceleration end and a host end.
The hardware acceleration end may include a plurality of hardware acceleration modules. Each of the plurality of hardware acceleration modules may be combined by an editable hardware logic unit. Each hardware acceleration module can be used for realizing data operation in a preset cryptographic algorithm. The hardware acceleration end may be an FPGA (Field Programmable Gate Array) board or other editable hardware capable of implementing acceleration.
The host side may provide an application program interface to the upper layer application program to receive the data to be processed via the application program interface. The data to be processed refers to data to be subjected to a cryptographic algorithm. For example, the data to be processed may be directly input by the user via an upper layer application. For another example, the user may input a data saving path in the application program, and the application program may obtain the data to be processed according to the data saving path input by the user, and send the obtained data to be processed to the host via the application program interface.
The host side can also carry out calculation power splitting according to the current application scene, and control the working state of a hardware acceleration module on the hardware acceleration side based on the calculation power splitting result. Wherein the current application scenario may include at least one of: the type of algorithm to be executed, the current hardware conditions, the amount of data to be processed, etc. The host side can also carry out calculation power splitting according to a preset strategy and the current application scene. The preset policy may be a rule preset by a user, and may be, for example, performance priority, power consumption priority, or a balance state. For example, for the case of performance priority, all hardware acceleration modules may be turned on even if the data amount of the data to be processed is small; for the case of priority of power consumption, even if the data volume of the data to be processed is large, only a small number of hardware acceleration modules can be turned on. And after the host side carries out calculation power splitting according to the current application scene, a calculation power splitting result can be obtained. For example, before performing the computation power splitting, the host may obtain specific conditions of the hardware acceleration module in the current entire system, such as cryptographic algorithm types and the number of operators of each type supported by the hardware acceleration terminal, and then the host may perform the computation power splitting according to the obtained specific hardware conditions. The computational split result may include the number of hardware acceleration modules to be opened. The host side can control the working state of the hardware acceleration module on the hardware acceleration side based on the calculation force splitting result, namely, the hardware acceleration module is opened or closed. For example, the host may interact with the hardware acceleration terminal in a preset interaction manner to control the operating state of each hardware acceleration module. The preset interaction mode may be sending a control signal to the hardware acceleration module or sending a control signal to a control module in the hardware acceleration terminal, and the control module may control a working state of the hardware acceleration module according to the control signal.
The host terminal can also load the data to be processed to a hardware acceleration module with an open working state, and the hardware acceleration module can execute cryptographic algorithm operation on the data to be processed to obtain processing result data and return the processing result data to the host terminal.
In the system in the above embodiment, an application program interface is provided for an upper application program through a host terminal to receive data to be processed, and the host terminal and a hardware acceleration terminal are disposed in the same set of framework system, so that developers can use hardware acceleration modules without threshold, and compatibility of each development environment is ensured.
In some embodiments of the present application, the host side may further be configured to determine host parameters matching the hardware acceleration side according to user requirements and host performance. The host parameter refers to a parameter of a host on which the host terminal operates, and may include at least one of the following: CPU frequency, number of cores, system memory usage, number of threads, etc. In the above embodiment, the host parameter matched with the hardware acceleration end is determined according to the user requirement and the host performance, so that the host end and the hardware acceleration end are more adaptive, the performance of the hardware acceleration system is improved, and the flexibility is enhanced.
In some embodiments of the present application, the host side may include a cryptographic algorithm hardmac. The cryptographic algorithm hardmac may include an application program interface upper layer (UAPI), a scheduling module, and an application program interface lower Layer (LAPI).
The application program interface upper layer may be used to provide an application program interface to an upper layer application. The upper layer of the application program interface can receive the data to be processed input by the user calling the application program. The scheduling module may be configured to perform computational power splitting according to a current application scenario. The scheduling module can perform calculation power splitting according to a preset strategy according to the current application scene, and determine the number of the hardware acceleration modules to be started, so as to control the working state of the hardware acceleration modules at the hardware acceleration end. The scheduling module can load the data to be processed to the hardware acceleration module through the lower layer of the application program interface according to the calculation force splitting result.
The application program interface lower layer can also be used for receiving processing result data returned by a hardware acceleration module in the hardware acceleration end. The scheduling module may output the processing result data to the upper application program via the upper application program interface layer when determining that the lower application program interface layer receives the processing result data.
In the above embodiment, the cryptographic algorithm hardmac includes an upper layer of application program interface provided upward for the application program to use, a lower layer of application program interface provided upward for shielding details of the underlying hardware, and a scheduling module for performing downward computation of splitting, scheduling, and load balancing of the hardware. In the cipher algorithm hardmac, the UAPI is responsible for providing a friendly user interface, a user call interface can transmit corresponding user setting parameters and data cache addresses, and the UAPI obtains corresponding data and transmits the corresponding data to the scheduling module after corresponding analysis. The scheduling module can split the calculation power according to the current system performance and the user requirement and a specific strategy, and reasonably loads data to each hardware acceleration module in the hardware acceleration end, so that the balanced scheduling of the calculation power is ensured. The LAPI may implement the relevant scheduling and data transfer to the actual hardware details of the hardware acceleration end. The LAPI can mask hardware details up, without upper layers understanding the hardware details. For example, when an upper layer application program needs to call a certain hardware acceleration module on the hardware acceleration end, only the LAPI is used. The LAPI can configure the details of transmission interface parameters, module parameters of a hardware acceleration end and the like and enable data to be transmitted. When the hardware acceleration module in the hardware acceleration end changes, such as implementation change or hardware replacement, the LAPI is responsible for implementing relevant details, the scheduling module and the UAPI do not need to be changed, and an application program does not need to be changed, so that the flexibility is greatly enhanced.
In some embodiments of the present application, the host may further include a data forwarding layer. The data forwarding layer can receive the data to be processed sent through the lower layer of the application program interface, package the data to be processed to obtain a data packet to be processed, and send the data packet to be processed to the hardware acceleration module. The data forwarding layer can also receive a processing result data packet returned by the hardware acceleration module, analyze the processing result data packet to obtain processing result data, and return the processing result data to the application program interface lower layer.
Specifically, the data forwarding layer unpacks data upwards, returns the processing result of the hardware, and prepares for data encapsulation, data transmission or data reception downwards according to the relevant parameters. During data stream transmission, the data stream is packaged according to various protocols, including a general protocol and various private protocols, so that the data forwarding layer can perform data packaging and unpacking according to a protocol negotiated with the hardware acceleration end. When data is sent, the data forwarding layer divides data acquired from the cipher algorithm hard core into blocks according to a protocol, adds corresponding packet heads and packet tails to form single packets, then puts a plurality of single packets into a cache set by a sending submodule to form a data packet stream, sends a start signal to a hardware acceleration end after the data is ready, and a corresponding IP module in the hardware acceleration end receives the data stream. When receiving data sent by a hardware acceleration end, a data forwarding layer firstly starts a receiving submodule, stores a data stream transmitted from the hardware acceleration end into a specified cache, then unpacks according to a corresponding protocol, removes a packet head and a packet tail, copies effective load (payload) data into a real data cache to form a data block, and finally returns a cache address to an upper cryptographic algorithm hard core.
In some embodiments of the present application, the host may further include a driver layer, where the data forwarding layer may send the data packet to be processed to the hardware acceleration module through the driver layer, and the driver layer is used for driving a system base module at the host; the driving layer can also be used for receiving a processing result data packet returned by the hardware acceleration module and transmitting the processing result data packet to the data forwarding layer.
Specifically, the driver layer may be used for driving basic modules of the system, including a file system, a memory (memory), a PCIE (peripheral component interconnect express) and other basic modules, so that the system can operate with high performance. The drive layer is an infrastructure of the host, the module is used for encapsulating the file system, the memory, the PCIE and other general modules again according to the requirement, and a parameter setting mechanism is added in the middle of the module, so that the basic modules can operate according to the requirement. Under some special scenes, the drive layer can ensure the exclusivity of the own party to the universal basic modules and ensure the resource calling of the own party. If the driver layer is lacked, the corresponding resource calling module needs to be changed every time a type of machine or system is changed, and the calling of the resource cannot be guaranteed. Thus, the driver layer can guarantee the flexibility of the hardware acceleration system for the cryptographic algorithm and the maximum use of resources.
In some embodiments of the present application, the hardware acceleration module may include an operator layer and an algorithm layer, wherein the operator layer includes hardware logic circuits for implementing data operations in a cryptographic algorithm; the algorithm layer can be used for combining operators in the operator layer into a hardware acceleration module for realizing a target cryptographic algorithm, so as to execute target cryptographic algorithm operation on data to be processed to obtain processing result data, and return the processing result data to the host side.
In particular, the operator layer may be used for the logical implementation of the significant operators. Some combinations of operations on data that are often used in cryptographic algorithms may be referred to as operators. Some of these operators are easier to implement and are not bottlenecks in performance, while others are very computationally expensive, and the operator layer is a hardware-logical implementation of these very computationally expensive operators. The conventional software algorithm has multithreading concurrent operation on operators, the multithreading concurrent operation has synchronization and scheduling problems, the hardware logic realization has no consideration of the problems, and all sub-operations are directly stacked and used, so that the concurrent operation can be guaranteed to the maximum extent. The operator layer can be multiplexed in various algorithms, and when operators supported by the operator layer are more and more, a very high city protection river can be formed, so that the uniqueness of a frame system is ensured, and the development cost of a corresponding module can be greatly reduced in the subsequent algorithm development.
The algorithm layer can realize scheduling processing and connection processing on the algorithm and can ensure the performance maximization of the hardware acceleration module. By hardwiring the cryptographic algorithm, a large amount of system overhead such as software calling can be saved, and the performance of the cryptographic algorithm application can be greatly improved. Meanwhile, after the whole cryptographic algorithm is realized at the hardware acceleration end, the transmission overhead and the communication overhead can be greatly reduced, and the performance is improved exponentially. The hardware acceleration module realizes the preset cryptographic algorithm by combining different operators, adding logic processing such as a production line and the like on the basis of the operator layer and performing connection processing according to related requirements. In this embodiment, the flexibility and compatibility of the system can also be improved by separating the algorithm layer and the operator layer.
In some embodiments of the present application, the hardware acceleration end may further include an interface layer, an interface protocol analysis layer, and an adaptation layer, where the interface layer may include a plurality of interface IP modules, and is configured to receive a to-be-processed data packet sent by the host end; the interface protocol analysis layer and the adaptation layer can be used for analyzing the received data packet to be processed to obtain data to be processed and transmitting the data to be processed to the operator layer and the algorithm layer; the interface protocol analysis layer and the adaptation layer can also be used for receiving processing result data transmitted by the algorithm layer and the algorithm layer, packaging the processing result data to obtain a processing result data packet, and returning the processing result data packet to the host end through the interface layer.
Specifically, various interface IPs may be included in the interface layer. Wherein, IP refers to a kernel module, which is a pre-designed integrated circuit, device or component even verified to have some certain function. For example, when a customer needs to use a PCIE interface, the hardware acceleration end may instantiate a PCIE interface, the interface is formed by combining various logic units, and when the customer needs to change to an optical fiber interface, the logic units may be recombined and instantiated to an optical fiber interface. By setting the interface layer, the compatibility of multiple interfaces can be ensured to be realized by using minimum on-board resources.
The interface protocol parsing layer may be used for data unpacking, packing and storing of related transport interface protocols. The interface protocol analysis layer is connected with interface IP instantiated by the interface layer, the general interface IP is generally a larger protocol stack corresponding to the general interface IP, and the interface protocol analysis layer can be realized by the corresponding protocol stack. When the interface IP protocol stack is complex, the corresponding realization of the interface protocol analysis layer is complex, the host end uses software to analyze, and the hardware acceleration end uses hardware to directly analyze. For a big data scene, an interface protocol analysis layer is adopted to analyze the data packet, so that the compatibility is ensured and the system performance is greatly enhanced.
The adaptation layer may be used for data parsing and processing related to internal protocols (including interface protocols and transport protocols) on the host side. As mentioned above, the data forwarding layer of the host performs packet packing and unpacking according to the protocol. The adaptation layer of the hardware acceleration end is used with the proprietary protocol in the data forwarding layer of the host end. The hardware acceleration end and the host end usually negotiate one or more private protocols in advance, and the adaptation layer is implemented according to a protocol stack of the negotiated protocols. The difference between the adaptation layer and the interface protocol analysis layer is that the interface protocol analysis layer is a universal interface protocol, the universal interface can ensure compatibility, the adaptation layer is a private protocol, and the private protocol can ensure that the host end and the hardware acceleration end have good security and privacy while being well adapted.
The above system is described with reference to a specific embodiment, however, it should be noted that the specific embodiment is only for better describing the present application and should not be construed as limiting the present application.
Referring to fig. 2, a schematic diagram of a hardware acceleration system for implementing a cryptographic algorithm in an embodiment of the present application is shown. As shown in fig. 2, the hardware acceleration system in this embodiment may include a host side and a hardware acceleration side. The host end may include a cryptographic algorithm hardmac, a data forwarding layer, and a driver layer. The hardware acceleration end can comprise an interface layer, an interface protocol analysis layer, an adaptation layer, an algorithm layer and an algorithm layer.
The cryptographic algorithm hardmac comprises an upper application program interface layer which is provided for application programs to use upwards, a lower application program interface layer which is provided for shielding bottom hardware details upwards, and a scheduling module which is used for performing downward calculation power splitting, scheduling and load balancing of hardware. In the cipher algorithm hardmac, the UAPI is responsible for providing a friendly user interface, a user call interface can transmit corresponding user setting parameters and data cache addresses, and the UAPI obtains corresponding data and transmits the corresponding data to the scheduling module after corresponding analysis. The scheduling module can split the calculation power according to the current system performance and the user requirement and a specific strategy, and reasonably loads data to each hardware acceleration module in the hardware acceleration end, so that the balanced scheduling of the calculation power is ensured. The LAPI may implement the relevant scheduling and data transfer to the actual hardware details of the hardware acceleration end. The LAPI can mask hardware details up, without upper layers understanding the hardware details. For example, when an upper layer application needs to call a certain acceleration module on the hardware acceleration end, only the LAPI is used. The LAPI can configure the details of transmission interface parameters, module parameters of a hardware acceleration end and the like and enable data to be transmitted. When the hardware acceleration module in the hardware acceleration end changes, such as implementation change or hardware replacement, the LAPI is responsible for implementing relevant details, the scheduling module and the UAPI are not changed, and an application program is not required to be changed, so that the flexibility is greatly enhanced.
And the data forwarding layer unpacks data upwards, returns the processing result of hardware and prepares for data packaging and data transmission or reception downwards according to the related parameters. During data stream transmission, the data stream is packaged according to various protocols, including a general protocol and various private protocols, so that the data forwarding layer can perform data packaging and unpacking according to a protocol negotiated with the hardware acceleration end. When data is sent, the data forwarding layer divides data acquired from the cipher algorithm hard core into blocks according to a protocol, adds corresponding packet heads and packet tails to form single packets, then puts a plurality of single packets into a cache set by a sending submodule to form a data packet stream, sends a start signal to a hardware acceleration end after the data is ready, and a corresponding IP module in the hardware acceleration end receives the data stream. When receiving data sent by a hardware acceleration end, a data forwarding layer firstly starts a receiving submodule, stores a data stream transmitted from the hardware acceleration end into a specified cache, then unpacks according to a corresponding protocol, removes a packet head and a packet tail, copies effective load (payload) data into a real data cache to form a data block, and finally returns a cache address to an upper cryptographic algorithm hard core.
The driver layer may be used for driving basic modules of the system, including a file system, a memory, a PCIE (peripheral component interconnect express) and other basic modules, so that the system can operate with high performance. Among them, PCIE can be configured based on RIFFA framework. The drive layer is an infrastructure of the host, the module is used for encapsulating the file system, the memory, the PCIE and other general modules again according to the requirement, and a parameter setting mechanism is added in the middle of the module, so that the basic modules can operate according to the requirement. Under some special scenes, the drive layer can ensure the exclusivity of the own party to the universal basic modules and ensure the resource calling of the own party. If the driver layer is lacked, the corresponding resource calling module needs to be changed every time a type of machine or system is changed, and the calling of the resource cannot be guaranteed. Thus, the driver layer can guarantee the flexibility of the hardware acceleration system for the cryptographic algorithm and the maximum use of resources.
Various interface IPs may be included in the interface layer. Wherein, IP refers to a kernel module, which is a pre-designed integrated circuit, device or component even verified to have some certain function. For example, when a customer needs to use a PCIE interface, the hardware acceleration end may instantiate a PCIE interface, the interface is formed by combining various logic units, and when the customer needs to change to an optical fiber interface, the logic units may be recombined and instantiated to an optical fiber interface. By setting the interface layer, the compatibility of multiple interfaces can be ensured to be realized by using minimum on-board resources.
The interface protocol parsing layer may be used for data unpacking, packing and storing of related transport interface protocols. The interface protocol analysis layer is connected with interface IP instantiated by the interface layer, the general interface IP is generally a larger protocol stack corresponding to the general interface IP, and the interface protocol analysis layer can be realized by the corresponding protocol stack. When the interface IP protocol stack is complex, the corresponding realization of the interface protocol analysis layer is complex, the host end uses software to analyze, and the hardware acceleration end uses hardware to directly analyze. For a big data scene, an interface protocol analysis layer is adopted to analyze the data packet, so that the compatibility is ensured and the system performance is greatly enhanced.
The adaptation layer may be used for data parsing and processing related to internal protocols (including interface protocols and transport protocols) on the host side. As mentioned above, the data forwarding layer of the host performs packet packing and unpacking according to the protocol. The adaptation layer of the hardware acceleration end is used with the proprietary protocol in the data forwarding layer of the host end. The hardware acceleration end and the host end usually negotiate one or more private protocols in advance, and the adaptation layer is implemented according to a protocol stack of the negotiated protocols. The difference between the adaptation layer and the interface protocol analysis layer is that the interface protocol analysis layer is a universal interface protocol, the universal interface can ensure compatibility, the adaptation layer is a private protocol, and the private protocol can ensure that the host end and the hardware acceleration end have good security and privacy while being well adapted.
The operator layer can be used for the logical implementation of the significant operators. Some combinations of operations on data that are often used in cryptographic algorithms may be referred to as operators. For example, the operator layer may include NTT (Number theoretical Transforms) and other operators. Some of these operators are easier to implement and are not bottlenecks in performance, while others are very computationally expensive, and the operator layer is a hardware-logical implementation of these very computationally expensive operators. The conventional software algorithm has multithreading concurrent operation on operators, the multithreading concurrent operation has synchronization and scheduling problems, the hardware logic realization has no consideration of the problems, and all sub-operations are directly stacked and used, so that the concurrent operation can be guaranteed to the maximum extent. The operator layer can be multiplexed in various algorithms, and when operators supported by the operator layer are more and more, a very high city protection river can be formed, so that the uniqueness of a frame system is ensured, and the development cost of a corresponding module can be greatly reduced in the subsequent algorithm development.
The algorithm layer can realize scheduling processing and connection processing on the algorithm and can ensure the performance maximization of the hardware acceleration module. By hardwiring the cryptographic algorithm, a large amount of system overhead such as software calling can be saved, and the performance of the cryptographic algorithm application can be greatly improved. Meanwhile, after the whole cryptographic algorithm is realized at the hardware acceleration end, the transmission overhead and the communication overhead can be greatly reduced, and the performance is improved exponentially. The hardware acceleration module realizes the preset cryptographic algorithm by combining different operators, adding logic processing such as a production line and the like on the basis of the operator layer and performing connection processing according to related requirements. In this embodiment, the flexibility and compatibility of the system can also be improved by separating the algorithm layer and the operator layer.
The hardware acceleration system in the embodiment forms a framework system through different module combinations, can stably and adaptively operate in different scenes, and can be developed according to the local thinking of application development through the provided related interfaces without knowing hardware details, so that the threshold of a user is greatly reduced, and the hardware performance is more efficiently exerted; different modules can form various combinations through switches, and are suitable for various scenes; the throughput among different modules can be more effectively optimized under the condition of modularization; under the condition of the same parameters, the whole method shows the acceleration of the algorithm.
Based on the same inventive concept, the embodiment of the application also provides a hardware acceleration method for realizing the cryptographic algorithm, the method is applied to a hardware acceleration system for realizing the cryptographic algorithm, the hardware acceleration system comprises a host end and a hardware acceleration end, and the hardware acceleration end comprises a plurality of hardware acceleration modules. As described in the examples below. Because the principle of solving the problem of the hardware acceleration method for implementing the cryptographic algorithm is similar to that of the hardware acceleration system for implementing the cryptographic algorithm, the implementation of the hardware acceleration method for implementing the cryptographic algorithm can refer to the implementation of the hardware acceleration system for implementing the cryptographic algorithm, and repeated details are not repeated. Fig. 3 is a flowchart of a hardware acceleration method for implementing a cryptographic algorithm according to an embodiment of the present application.
Although the present application provides method operational steps or apparatus configurations as illustrated in the following examples or figures, more or fewer operational steps or modular units may be included in the methods or apparatus based on conventional or non-inventive efforts. In the case of steps or structures which do not logically have the necessary cause and effect relationship, the execution sequence of the steps or the module structure of the apparatus is not limited to the execution sequence or the module structure described in the embodiments and shown in the drawings of the present application. When the described method or module structure is applied in an actual device or end product, the method or module structure according to the embodiments or shown in the drawings can be executed sequentially or executed in parallel (for example, in a parallel processor or multi-thread processing environment, or even in a distributed processing environment).
As shown in fig. 3, a hardware acceleration method for implementing a cryptographic algorithm according to an embodiment of the present application may include the following steps.
In step S301, the host receives data to be processed through the application program interface.
Step S302, the host computer performs calculation power splitting according to the current application scene, controls the working state of a hardware acceleration module on the hardware acceleration end based on the calculation power splitting result, and loads the data to be processed to the hardware acceleration module of the hardware acceleration end.
Step S303, the hardware acceleration module executes the cryptographic algorithm operation on the data to be processed to obtain processing result data, and returns the processing result data to the host.
In some embodiments of the present application, the method may further comprise: and the host end determines host parameters matched with the hardware acceleration end according to the user requirements and the host performance.
In some embodiments of the present application, the host includes a cryptographic algorithm hardcore, a data forwarding layer and a driver layer; the cryptographic algorithm hardmac comprises an application program interface upper layer, a scheduling module and an application program interface lower layer; the hardware acceleration end comprises an interface layer, an interface protocol analysis layer, an adaptation layer, an algorithm layer and an algorithm layer; the host receives data to be processed through an upper layer of an application program interface; correspondingly, the host receives the data to be processed through the upper layer of the application program interface; the loading, by the host, the data to be processed to the hardware acceleration module of the hardware acceleration end may include: the scheduling module performs calculation power splitting according to the current application scene so as to send the data to be processed to the data forwarding layer through the lower layer of the application program interface; the data forwarding layer packages the received data to be processed to obtain a data packet to be processed, and sends the data packet to be processed to the interface layer through the driving layer; the interface protocol analysis layer and the adaptation layer analyze the received data packet to be processed to obtain data to be processed, and transmit the data to be processed to the algorithm layer and the algorithm layer.
In some embodiments of the present application, the executing, by the hardware acceleration module, a cryptographic algorithm operation on the data to be processed to obtain processing result data may include: the algorithm layer combines operators in the operator layer into a hardware acceleration module for realizing a target cryptographic algorithm so as to execute the target cryptographic algorithm operation on the data to be processed and obtain processing result data.
In some embodiments of the present application, the returning, by the hardware acceleration end, the processing result data to the host end may include: the arithmetic layer and the algorithm layer transmit the processing result data to the interface protocol analysis layer and the adaptation layer; the interface protocol analysis layer and the adaptation layer encapsulate the processing result data to obtain a processing result data packet, and the processing result data packet is returned to the host end through the interface layer; the host receives the processing result data packet through the driving layer, and the driving layer transmits the processing result data packet to the data forwarding layer; the data forwarding layer analyzes the processing result data packet to obtain processing result data, and returns the processing result data to the lower layer of the application program interface; and the scheduling module outputs the processing result data to an upper application program through the upper application program interface layer under the condition that the lower application program interface layer receives the processing result data.
The above method is described below with reference to a specific example, however, it should be noted that the specific example is only for better describing the present application and is not to be construed as limiting the present application.
Referring to fig. 4, a general flowchart of a hardware acceleration method for implementing a cryptographic algorithm according to an embodiment of the present application is shown. As shown in fig. 4, the hardware acceleration method in this embodiment may include the following steps.
Step 1, a user calls UAPI in a cipher algorithm hard core of a host end through an application program, corresponding user setting parameters and data cache addresses are transmitted, and the UAPI acquires corresponding data, correspondingly analyzes the data and transmits the data to a scheduling module. The scheduling module can split the calculation power according to the current system performance and the user requirement and a specific strategy, and sends the split calculation power to the data forwarding layer through the LAPI. The data forwarding layer splits and encapsulates the data according to a protocol, and then sends the data out from the host end through basic modules in a drive layer, such as a file system, a memory, a PCIE and the like. The user parameter setting may be different parameters set by the user according to a specific scene and a specific requirement. For example, in order to improve the calculation accuracy, the user parameters may include parameters such as an angle and a data address for an application scenario of face recognition, and the user parameters may include parameters such as a gender, an age, and a family medical history for an application scenario of disease diagnosis.
And 2, after receiving data through a basic IP module of an interface layer such as PCIE, DMA, RAM and DDR and the like, a hardware acceleration end analyzes related protocols at an interface protocol analysis layer and an adaptation layer, so that an effective data stream is obtained and transmitted to an algorithm layer, and the algorithm layer and an operator layer work cooperatively to process the related data to obtain result data.
And 3, returning the obtained result data to the interface protocol analysis layer and the adaptation layer by the operator layer and the algorithm layer. And the result data is encapsulated in the interface protocol analysis layer and the adaptation layer according to the protocol, and the encapsulated result data flow is sent out from the hardware acceleration end through the interface layer.
And 4, the host end receives the result data stream through the driving layer and then upwards sends the result data stream to the data forwarding layer. And the data forwarding layer analyzes according to the protocol, obtains result data from the protocol and returns the result data to the LAPI. And the scheduling module outputs the result data to an upper application program through the UAPI after knowing that the LAPI acquires the result data.
From the above description, it can be seen that the embodiments of the present application achieve the following technical effects: the host end can also switch the hardware acceleration module according to the current application scene, so that the host end can automatically switch various modules according to the setting of a client, the flexibility of the system is improved, in addition, the hardware acceleration end comprises a plurality of hardware acceleration modules, each hardware acceleration module is used for realizing the preset cryptographic algorithm, different cryptographic algorithm operations can be executed by loading the data to be processed to different hardware acceleration modules, and therefore the system is suitable for different application scenes and has rich functions. By means of the technical scheme, the technical problems that the cryptology hardware acceleration function is single and the flexibility is poor in the prior art are solved, and the technical effects of effectively improving the flexibility and the function richness of a hardware acceleration system are achieved.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the present application described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different from that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the application should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the pending claims along with the full scope of equivalents to which such claims are entitled.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and it will be apparent to those skilled in the art that various modifications and variations can be made in the embodiment of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (13)
1. A hardware acceleration system for realizing a cryptographic algorithm is characterized by comprising a hardware acceleration end and a host end, wherein,
the hardware acceleration end comprises a plurality of hardware acceleration modules, and each hardware acceleration module in the plurality of hardware acceleration modules is formed by combining editable hardware logic units and is used for realizing a preset cryptographic algorithm;
the host side is used for providing an application program interface for an upper application program so as to receive data to be processed through the application program interface; the host side is further used for performing calculation power splitting according to the current application scene, controlling the working state of a hardware acceleration module on the hardware acceleration side based on a calculation power splitting result, and loading the data to be processed to the hardware acceleration module;
the hardware acceleration module is used for executing cryptographic algorithm operation on the data to be processed to obtain processing result data and returning the processing result data to the host side.
2. The system of claim 1, wherein the hardware acceleration port comprises an FPGA board.
3. The system of claim 1, wherein the host side is further configured to determine host parameters matching the hardware acceleration side according to user requirements and host performance.
4. The system of claim 1, wherein the host side comprises a cryptographic algorithm hardmac comprising an upper application program interface layer, a scheduling module, and a lower application program interface layer, wherein,
the upper layer of the application program interface is used for providing an application program interface for an upper layer application program, and the scheduling module is used for performing calculation power splitting according to the current application scene so as to load data to be processed onto the hardware acceleration module through the lower layer of the application program interface;
the lower application program interface layer is further configured to receive processing result data returned by the hardware acceleration module, and the scheduling module outputs the processing result data to the upper application program via the upper application program interface layer when determining that the lower application program interface layer receives the processing result data.
5. The system of claim 4, wherein the host further comprises a data forwarding layer, and the data forwarding layer is configured to receive to-be-processed data sent via the application program interface lower layer, package the to-be-processed data to obtain to-be-processed data packets, and send the to-be-processed data packets to the hardware acceleration module;
and the data forwarding layer is also used for receiving the processing result data packet returned by the hardware acceleration module, analyzing the processing result data packet to obtain processing result data, and returning the processing result data to the application program interface lower layer.
6. The system according to claim 5, wherein the host further comprises a driver layer, the data forwarding layer sends the data packet to be processed to a hardware acceleration module through the driver layer, and the driver layer is used for driving a system base module at the host;
the driving layer is also used for receiving a processing result data packet returned by the hardware acceleration module and transmitting the processing result data packet to the data forwarding layer.
7. The system of claim 1, wherein the hardware acceleration module comprises an arithmetic layer and an algorithm layer, wherein,
the operator layer comprises hardware logic circuits for implementing data operations in a cryptographic algorithm;
the algorithm layer is used for combining operators in the operator layer into a hardware acceleration module used for realizing a target cryptographic algorithm, executing target cryptographic algorithm operation on data to be processed to obtain processing result data, and returning the processing result data to the host side.
8. The system of claim 7, wherein the hardware acceleration end further comprises an interface layer, an interface protocol resolution layer, and an adaptation layer, wherein,
the interface layer comprises a plurality of interface IP modules and is used for receiving the data packets to be processed sent by the host end;
the interface protocol analysis layer and the adaptation layer are used for analyzing the received data packet to be processed to obtain data to be processed and transmitting the data to be processed to the algorithm layer and the algorithm layer;
the interface protocol analysis layer and the adaptation layer are further used for receiving processing result data transmitted by the algorithm layer and the algorithm layer, encapsulating the processing result data to obtain a processing result data packet, and returning the processing result data packet to the host end through the interface layer.
9. A hardware acceleration method for realizing a cryptographic algorithm is applied to a hardware acceleration system for realizing the cryptographic algorithm, the hardware acceleration system comprises a host end and a hardware acceleration end, the hardware acceleration end comprises a plurality of hardware acceleration modules, and the method comprises the following steps:
the host receives data to be processed through an application program interface;
the host side carries out calculation power splitting according to the current application scene, controls the working state of a hardware acceleration module on the hardware acceleration side based on the calculation power splitting result, and loads the data to be processed to the hardware acceleration module of the hardware acceleration side;
and the hardware acceleration module executes cryptographic algorithm operation on the data to be processed to obtain processing result data, and returns the processing result data to the host side.
10. The method of claim 9, further comprising:
and the host end determines host parameters matched with the hardware acceleration end according to user requirements and host performance.
11. The method of claim 9, wherein the host side comprises a cryptographic hard core, a data forwarding layer, and a driver layer; the cryptographic algorithm hardmac comprises an application program interface upper layer, a scheduling module and an application program interface lower layer; the hardware acceleration end comprises an interface layer, an interface protocol analysis layer, an adaptation layer, an algorithm layer and an algorithm layer; the host side receives data to be processed through the upper layer of the application program interface;
correspondingly, the host receives data to be processed through the upper layer of the application program interface;
the host end loads the data to be processed to a hardware acceleration module of a hardware acceleration end, and the method comprises the following steps:
the scheduling module performs calculation power splitting according to the current application scene so as to send the data to be processed to the data forwarding layer through the lower layer of the application program interface;
the data forwarding layer packages the received data to be processed to obtain a data packet to be processed, and sends the data packet to be processed to the interface layer through the driving layer;
the interface protocol analysis layer and the adaptation layer analyze the received data packet to be processed to obtain data to be processed, and transmit the data to be processed to the algorithm layer and the algorithm layer.
12. The method of claim 11, wherein the hardware acceleration module performs a cryptographic operation on the data to be processed to obtain processing result data, and comprises:
the algorithm layer combines operators in the operator layer into a hardware acceleration module for realizing a target cryptographic algorithm so as to execute the target cryptographic algorithm operation on the data to be processed and obtain processing result data.
13. The method of claim 12, wherein the hardware acceleration end returns the processing result data to the host end, and comprises:
the arithmetic layer and the arithmetic layer transmit the processing result data to the interface protocol analysis layer and the adaptation layer;
the interface protocol analysis layer and the adaptation layer encapsulate the processing result data to obtain a processing result data packet, and the processing result data packet is returned to the host end through the interface layer;
the host end receives the processing result data packet through the driving layer, and the driving layer transmits the processing result data packet to the data forwarding layer;
the data forwarding layer analyzes the processing result data packet to obtain processing result data, and returns the processing result data to the lower layer of the application program interface;
and the scheduling module outputs the processing result data to an upper application program through the upper application program interface layer under the condition that the lower application program interface layer is determined to receive the processing result data.
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