CN112860327A - CPU port switching method, device, equipment and readable medium - Google Patents
CPU port switching method, device, equipment and readable medium Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The invention discloses a CPU port switching method, which comprises the following steps: obtaining backboard information of the backboard by the BMC, judging the backboard type of the backboard based on the backboard information and storing the backboard type; in response to receiving the query request of the BIOS, the BMC returns the type of the backboard to the BIOS; sending a corresponding instruction to a controller of a CPU port by the BIOS based on the backboard type so as to switch the CPU into a port supporting a backboard type protocol; and carrying out signal transmission with the backplane by the CPU port based on the protocol. The invention also discloses a CPU port switching device, computer equipment and a readable storage medium. The invention identifies the type of the backboard and flexibly supports different types of backboard according to different items, thereby providing more selection spaces for the configuration of the downlink backboard.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a method, an apparatus, a device, and a readable medium for switching a CPU port.
Background
At present, the domestic storage industry has the development trend that the user range is wider and wider, and the user demand is higher and higher. Traditionally, low value users have required lower data availability requirements, requiring storage by a single controller; high-value users generally require dual-control storage due to high requirements on data availability. However, as the industry grows and users become more dependent on data access, many medium and even low value customers also need cost effective dual controller storage. The CPU Port of current servers can only support a certain protocol, such as PCIe or SATA.
Since it is necessary to provide various servers with different configurations in response to different needs of clients, the configuration supported by a CPU whose port only supports a single protocol has a limitation in the case where the number of CPU ports is fixed.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, an apparatus, a device, and a readable medium for switching a CPU port, which identify a backplane type, flexibly support different types of backplanes according to different items, and provide more selection spaces for downlink backplane configuration.
Based on the above object, an aspect of the embodiments of the present invention provides a CPU port switching method, including the following steps: obtaining backboard information of the backboard by the BMC, judging the backboard type of the backboard based on the backboard information and storing the backboard type; in response to receiving the query request of the BIOS, the BMC returns the type of the backboard to the BIOS; sending a corresponding instruction to a controller of a CPU port by the BIOS based on the backboard type so as to switch the CPU into a port supporting a backboard type protocol; and carrying out signal transmission with the backplane by the CPU port based on the protocol.
In some embodiments, obtaining backplane information for the backplane by the BMC comprises: the backboard information stored by the FRU of the backboard is read by the BMC through the I2C protocol.
In some embodiments, the FRU stores backplane information including production time, date, manufacturer, backplane name, production number.
In some embodiments, returning, by the BMC, the backplane type to the BIOS includes: the BMC returns the backplane type to the BIOS via IPMI commands.
In some embodiments, sending, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type to cause the CPU to switch to a port supporting the backplane type protocol comprises: responding to the type of the back plate as the SATA back plate, sending an instruction to a controller of a CPU port by the BIOS so as to switch the CPU into a port supporting the SATA protocol;
the signal transmission between the CPU port and the backboard based on the protocol comprises the following steps: and the CPU port transmits signals with the SATA back plate based on the SATA protocol.
In some embodiments, sending, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type to cause the CPU to switch to a port supporting the backplane type protocol comprises: responding to the back plate type as an NVME back plate, sending an instruction to a controller of a CPU port by the BIOS so as to switch the CPU into a port supporting an NVME protocol;
the signal transmission between the CPU port and the backboard based on the protocol comprises the following steps: and the CPU port performs signal transmission with the NVME backboard based on the NVME protocol.
In some embodiments, the CPU is a Milan processor of the AMD platform.
In another aspect of the embodiments of the present invention, there is also provided a CPU port switching apparatus, including: the judgment module is configured to acquire the backboard information of the backboard by the BMC, judge the backboard type of the backboard based on the backboard information and store the backboard type; the query module is configured to respond to a received query request of the BIOS and return the type of the backboard to the BIOS by the BMC; the switching module is configured to send an instruction to a controller of a CPU port by the BIOS based on the backplane type so as to switch the CPU into a port supporting the backplane type protocol; and the communication module is configured for carrying out signal transmission with the backboard by the CPU port based on a protocol.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: the type of the backplane is identified, and the server based on the AMD Socket SP3 processor flexibly supports different types of backplanes according to different projects, so that more selection spaces are provided for downlink backplane configuration.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a diagram illustrating an embodiment of a CPU port switching method according to the present invention;
FIG. 2 is a process diagram of an embodiment of a CPU port switching method according to the present invention;
FIG. 3 is a diagram illustrating an embodiment of a CPU port switching device according to the present invention;
FIG. 4 is a schematic diagram of an embodiment of a computer device provided by the present invention;
FIG. 5 is a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a CPU port switching method. Fig. 1 is a schematic diagram illustrating an embodiment of a CPU port switching method provided in the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s01, obtaining the backboard information of the backboard by the BMC, and judging the backboard type of the backboard based on the backboard information and storing the backboard type;
s02, responding to the received query request of the BIOS, and returning the backboard type to the BIOS by the BMC;
s03, the BIOS sends a corresponding instruction to the controller of the CPU port based on the backboard type, so that the CPU is switched to the port supporting the backboard type protocol; and
and S04, the CPU port transmits signals with the backboard based on the protocol.
In this embodiment, a Socket SP3 processor from Milan, which is introduced by AMD, is taken as an example. The Milan processor employs a Zen 3 core, supporting SP3 slots, DDR4, PCIe 4. Socket SP3 processors support a variety of server designs, each processor can support up to 16 memory banks, and each processor has 8 16-bit I/O links. The high speed I/O channels (128 total) supported by the SP3 processor may be divided into P0, P2, P3, G0, G1, G2, and G3. The functions of the links (P0, P2, P3, G0, G1, G2, and G3) supported by the Socket SP3 processor are shown in the table below, and the ports from any given PHY group within a link must be of the same protocol type, i.e., PCIe or SATA (Serial ATA).
Some ports of the AMD Socket SP3 processor support both SATA and PCIe protocols, that is, the ports can be configured with a SAS/SATA backplane or a NVMe backplane, which provides more selection space for downstream backplane configuration.
In this embodiment, fig. 2 is a schematic process diagram of an embodiment of a CPU port switching method. As shown in fig. 2, the CPU is a Socket SP3 processor of AMD, where PO, P1, G2, G3 support SATA or NVMe protocols, and a downstream SAS/SATA backplane or NVMe backplane may be configured; the BP is a backboard and supports the FRU, and the FRU can store backboard information such as production time, date, manufacturer, backboard name, production number and the like; the BMC (baseboard management controller) is a basic core function subsystem of the server, namely a substrate management controller and intelligent platform management interface, and is responsible for core functions of hardware state management, operating system management, health state management, power consumption management and the like of the server; the BIOS is a basic input and output system, and the BIOS is responsible for a self-checking program and a system self-starting program of the computer system, so that the BIOS is a first program after the computer system is started, a controller capable of controlling a CPU port and controlling the CPU port to adapt to an SATA protocol or an NVMe protocol; IPMI is an on-board component which is independent of a CPU, a BIOS/UEFI and an OS of a host system and can run independently, and the core component of the IPMI is BMC. The interaction between BMC and BIOS is accomplished via IPMI.
In the starting process, after the backboard is powered on, the mainboard BMC reads information on the FRU of the backboard through an I2C protocol, identifies the type of the backboard and judges whether the backboard is an SATA backboard or an NVMe backboard. After the BMC acquires the backboard information and the BIOS sends an inquiry request to the BMC, the BMC feeds back the BIOS backboard information through an IPMI command and informs the BIOS that the backboard needs to support an SATA (serial advanced technology attachment) protocol (or NVMe) protocol. And after the BIOS acquires the information, the BIOS controls a controller of the CPU port, so that the CPU port supports an SATA protocol (or an NVMe protocol).
In some embodiments of the present invention, obtaining the backplane information of the backplane by the BMC comprises: the backboard information stored by the FRU of the backboard is read by the BMC through the I2C protocol.
In some embodiments, the FRU stores backplane information including production time, date, manufacturer, backplane name, production number.
In some embodiments, returning, by the BMC, the backplane type to the BIOS includes: the BMC returns the backplane type to the BIOS via IPMI commands.
In some embodiments, sending, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type to cause the CPU to switch to a port supporting the backplane type protocol comprises: and responding to the type of the back plate as the SATA back plate, and sending an instruction to a controller of the CPU port by the BIOS so as to switch the CPU into the port supporting the SATA protocol. The signal transmission between the CPU port and the backboard based on the protocol comprises the following steps: and the CPU port transmits signals with the SATA back plate based on the SATA protocol.
In some embodiments, sending, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type to cause the CPU to switch to a port supporting the backplane type protocol comprises: and responding to the type of the back plate as an NVME back plate, and sending an instruction to a controller of the CPU port by the BIOS so as to switch the CPU into a port supporting the NVME protocol. The signal transmission between the CPU port and the backboard based on the protocol comprises the following steps: and the CPU port performs signal transmission with the NVME backboard based on the NVME protocol.
In some embodiments, the CPU is a Milan processor of the AMD platform.
It should be particularly noted that, the steps in the embodiments of the CPU port switching method described above may be mutually intersected, replaced, added, or deleted, and therefore, the CPU port switching method based on these reasonable permutation and combination transformations shall also belong to the scope of the present invention, and shall not limit the scope of the present invention to the embodiments.
In view of the above object, a second aspect of the embodiments of the present invention provides a CPU port switching apparatus. Fig. 2 is a schematic diagram illustrating an embodiment of the CPU port switching apparatus provided in the present invention. As shown in fig. 2, the embodiment of the present invention includes the following modules: the judgment module S11 is configured to acquire the backplane information of the backplane by the BMC, and judge and store the backplane type of the backplane based on the backplane information; a query module S12 configured to return the backplane type to the BIOS by the BMC in response to receiving a query request of the BIOS; a switching module S13 configured to send a corresponding instruction to the controller of the CPU port by the BIOS based on the backplane type, so that the CPU switches to a port supporting the backplane type protocol; and a communication module S14 configured to transmit signals with the backplane by the CPU port based on the protocol.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device. Fig. 3 is a schematic diagram of an embodiment of a computer device provided by the present invention. As shown in fig. 3, an embodiment of the present invention includes the following means: at least one processor S21; and a memory S22, the memory S22 storing computer instructions S23 executable on the processor, the instructions when executed by the processor implementing the steps of the above method.
The invention also provides a computer readable storage medium. FIG. 4 is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 4, the computer readable storage medium stores S31 a computer program that, when executed by a processor, performs the method as described above S32.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the program of the CPU port switching method may be stored in a computer readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A CPU port switching method is characterized by comprising the following steps:
obtaining backboard information of a backboard by a BMC, and judging and storing a backboard type of the backboard based on the backboard information;
returning, by the BMC, the backplane type to the BIOS in response to receiving a query request for the BIOS;
sending, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type to switch the CPU to a port supporting the backplane type protocol; and
and carrying out signal transmission with the backboard by the CPU port based on the protocol.
2. The CPU port switching method of claim 1, wherein obtaining the backplane information of the backplane by the BMC comprises:
the backboard information stored by the FRU of the backboard is read by the BMC through the I2C protocol.
3. The CPU port switching method of claim 2, wherein the FRU stores backplane information including production time, date, manufacturer, backplane name, production number.
4. The CPU port switching method of claim 1, wherein returning, by the BMC, the backplane type to the BIOS comprises:
returning, by the BMC, the backplane type to the BIOS via an IPMI command.
5. The CPU port switching method of claim 1, wherein sending, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type to switch the CPU to a port supporting the backplane type protocol comprises: responding to the type of the back plate is the SATA back plate, and sending an instruction to a controller of a CPU port by the BIOS so as to switch the CPU into a port supporting the SATA protocol;
signaling, by the CPU port, with the backplane based on the protocol comprises: and the CPU port transmits signals with the SATA back plate based on the SATA protocol.
6. The CPU port switching method of claim 1, wherein sending, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type to switch the CPU to a port supporting the backplane type protocol comprises: responding to the fact that the type of the backboard is an NVME backboard, and sending an instruction to a controller of a CPU port by the BIOS so that the CPU is switched into a port supporting an NVME protocol;
signaling, by the CPU port, with the backplane based on the protocol comprises: and the CPU port transmits signals with the NVME backboard based on the NVME protocol.
7. The CPU port switching method of claim 1, wherein the CPU is a Milan processor of an AMD platform.
8. A CPU port switching apparatus, comprising:
the judgment module is configured to acquire the backboard information of the backboard by the BMC, judge the backboard type of the backboard based on the backboard information and store the backboard type;
the query module is configured to respond to a query request of the BIOS, and the BMC returns the backplane type to the BIOS;
a switching module configured to send, by the BIOS, a corresponding instruction to a controller of a CPU port based on the backplane type, so that the CPU switches to a port supporting the backplane type protocol; and
and the communication module is configured to be used for carrying out signal transmission with the backboard by the CPU port based on the protocol.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any of the methods 1-7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023160691A1 (en) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | Connector-based port management method and related device |
| CN117459370A (en) * | 2023-12-26 | 2024-01-26 | 深圳鼎信通达股份有限公司 | Main-standby competition method and system of single machine double main control boards, communication gateway and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104008035A (en) * | 2014-06-10 | 2014-08-27 | 浪潮电子信息产业股份有限公司 | A remote monitoring method for implementing state of hard disk back broad |
| US20170277547A1 (en) * | 2014-12-11 | 2017-09-28 | Huawei Technologies Co., Ltd. | Method for Presenting Initialization Progress of Hardware in Server, and Server |
| CN107688376A (en) * | 2017-09-28 | 2018-02-13 | 郑州云海信息技术有限公司 | A kind of hard disk backboard for supporting adaptive hard-disk interface |
| CN208477453U (en) * | 2018-08-07 | 2019-02-05 | 成都海光集成电路设计有限公司 | Server |
-
2021
- 2021-02-09 CN CN202110178095.6A patent/CN112860327A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104008035A (en) * | 2014-06-10 | 2014-08-27 | 浪潮电子信息产业股份有限公司 | A remote monitoring method for implementing state of hard disk back broad |
| US20170277547A1 (en) * | 2014-12-11 | 2017-09-28 | Huawei Technologies Co., Ltd. | Method for Presenting Initialization Progress of Hardware in Server, and Server |
| CN107688376A (en) * | 2017-09-28 | 2018-02-13 | 郑州云海信息技术有限公司 | A kind of hard disk backboard for supporting adaptive hard-disk interface |
| CN208477453U (en) * | 2018-08-07 | 2019-02-05 | 成都海光集成电路设计有限公司 | Server |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023160691A1 (en) * | 2022-02-28 | 2023-08-31 | 华为技术有限公司 | Connector-based port management method and related device |
| CN117459370A (en) * | 2023-12-26 | 2024-01-26 | 深圳鼎信通达股份有限公司 | Main-standby competition method and system of single machine double main control boards, communication gateway and storage medium |
| CN117459370B (en) * | 2023-12-26 | 2024-03-15 | 深圳鼎信通达股份有限公司 | Main-standby competition method and system of single machine double main control boards, communication gateway and storage medium |
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