CN112859377B - Multiplexing register, three-dimensional display device and control method thereof - Google Patents
Multiplexing register, three-dimensional display device and control method thereof Download PDFInfo
- Publication number
- CN112859377B CN112859377B CN201911193660.5A CN201911193660A CN112859377B CN 112859377 B CN112859377 B CN 112859377B CN 201911193660 A CN201911193660 A CN 201911193660A CN 112859377 B CN112859377 B CN 112859377B
- Authority
- CN
- China
- Prior art keywords
- data
- module
- address
- multiplexing
- dimensional image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Controls And Circuits For Display Device (AREA)
Abstract
The invention provides a multiplexing register, a three-dimensional display device and a control method thereof, and relates to the technical field of display. The invention provides a multiplexing register, which comprises a multiplexing module, wherein the multiplexing module comprises an instruction output unit, a parameter output unit and an address output unit; the instruction output unit outputs instruction execution data corresponding to each instruction operation when in an instruction execution state, the parameter output unit outputs configuration data for parameter configuration of the three-dimensional display device when in a data operation state, and the address output unit outputs address data relating to an entry address of the two-dimensional image slice when in an address synthesis state. The instruction register, the data register and the address register are replaced by the multiplexing register, so that the number of registers required to be set in the three-dimensional display device is reduced, the number of registers required to be traversed by the processor is reduced, the resource occupation of the registers on the processor is correspondingly reduced, and the power consumption of the processor is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a multiplexing register, a three-dimensional display device and a control method thereof.
Background
The three-dimensional display device mainly utilizes the human eye vision retention effect to control the rotary display module to switch a two-dimensional image slice for display at a certain rotation angle, and when the rotary display module rotates at a high speed, a plurality of two-dimensional image slices can be simultaneously reserved in human eyes, so that a viewer can view images with three-dimensional effect.
At present, a three-dimensional display device is provided with a plurality of registers, such as an instruction register, a data register and an address register, when the three-dimensional display device displays a three-dimensional image, a processor needs to traverse all registers in real time, and when data stored in the registers are found to be changed, corresponding operations can be executed.
However, when the number of registers provided in the three-dimensional display device is larger, the more registers the processor needs to traverse, the more resources of the processor are occupied by the registers, and the power consumption of the processor is larger.
Disclosure of Invention
The invention provides a multiplexing register, a three-dimensional display device and a control method thereof, which are used for solving the problem that the register occupies more resources of a processor in the conventional three-dimensional display device, so that the power consumption of the processor is larger.
In order to solve the above problems, the present invention discloses a multiplexing register applied to a three-dimensional display device, the multiplexing register comprising a multiplexing module, the multiplexing module comprising an instruction output unit, a parameter output unit and an address output unit;
the instruction output unit is configured to output instruction execution data corresponding to each instruction operation when the multiplexing module is in an instruction execution state;
the parameter output unit is configured to output configuration data for performing parameter configuration on the three-dimensional display device when the multiplexing module is in a data operation state;
the address output unit configured to output address data related to an entry address of a two-dimensional image slice when the multiplexing module is in an address synthesis state;
wherein, at any time, the multiplexing module is in any one of the instruction execution state, the data operation state and the address synthesis state.
Optionally, the multiplexing register further includes an address storage module;
the address storage module is configured to store an entry address of a current two-dimensional image slice and an entry address of a next frame two-dimensional image slice.
Optionally, the multiplexing register further includes an error correction module, where the error correction module includes a data modification unit;
the data modification unit is configured to modify the data stored in the multiplexing module when the number of times that any one device in the three-dimensional display device performs the same operation is greater than a set number of times, so that the multiplexing module outputs instruction execution data for resetting or powering off the three-dimensional display device.
Optionally, the error correction module further includes a parameter passing unit;
the parameter passing unit is configured to pass the join parameter of a plurality of multiplexing registers cascaded with the multiplexing register.
Optionally, the bit width of the multiplexing module is 8 bits.
Optionally, a seventh bit and a sixth bit of the multiplexing module store operation status data, where the operation status data is used to indicate an operation status of the multiplexing module, and the operation status includes the instruction execution status, the data operation status, and the address synthesis status.
Optionally, when the multiplexing module is in the instruction execution state, the fifth bit to the third bit of the multiplexing module store operation data that needs to be executed in the instruction execution data, the second bit to the 0th bit of the multiplexing module store execution parameters corresponding to the operation data, and the execution parameters include direct execution or jump to an initial state.
Optionally, when the multiplexing module is in the data operation state, fifth to fourth bits of the multiplexing module store mode data in the configuration data, and third to 0th bits of the multiplexing module store setting parameters corresponding to the mode data.
Optionally, when the multiplexing module is in the address synthesis state, a fifth bit of the multiplexing module stores address change mode data in the address data; when the address change mode data is the equal-interval gradient data, the fourth bit to the 0th bit of the multiplexing module stores step length, and when the address change mode data is the scattered distribution data, the fourth bit to the 0th bit of the multiplexing module stores indicating data used for indicating the entry address of the next frame of two-dimensional image slice.
In order to solve the above problem, the present invention further discloses a three-dimensional display device, which includes a first memory, a processor and the above multiplexing register, wherein the processor includes a data reading module, an instruction executing module, a parameter configuration module and an address obtaining module;
the first memory configured to store entry addresses of two-dimensional image slices;
the data reading module is configured to read data stored in the multiplexing module in the multiplexing register so as to determine the operating state of the multiplexing module;
the instruction execution module is configured to execute corresponding instruction operation according to the instruction execution data when the multiplexing module is in an instruction execution state;
the parameter configuration module is configured to perform parameter configuration on the three-dimensional display device according to the configuration data when the multiplexing module is in a data operation state;
the address acquisition module is configured to determine, when the multiplexing module is in an address synthesis state, instruction data for instructing an entry address of a two-dimensional image slice according to the address data, and acquire the entry address of the two-dimensional image slice stored in the first memory according to the instruction data.
Optionally, the three-dimensional display device further includes a second memory, a driving module, and a rotating display module, and the processor further includes an address sending module;
the second memory configured to store the two-dimensional image slice;
the address sending module is configured to send an entry address of the two-dimensional image slice to the driving module;
the driving module is configured to acquire the two-dimensional image slice from the second memory according to the entry address and send the two-dimensional image slice to the rotary display module;
and the rotating display module is configured to display the corresponding two-dimensional image slice according to the rotating position so as to realize three-dimensional display.
In order to solve the above problem, the present invention further discloses a control method of a three-dimensional display device, which is applied to the above three-dimensional display device, the method comprising:
reading data stored in a multiplexing module in the multiplexing register to determine the operating state of the multiplexing module;
when the multiplexing module is in an instruction execution state, executing corresponding instruction operation according to the instruction execution data;
when the multiplexing module is in a data operation state, parameter configuration is carried out on the three-dimensional display device according to the configuration data;
and when the multiplexing module is in an address synthesis state, determining indicating data for indicating an entry address of a two-dimensional image slice according to the address data, and acquiring the entry address of the two-dimensional image slice stored in the first memory according to the indicating data.
Optionally, after the step of acquiring an entry address of a two-dimensional image slice stored in the first memory according to the indication data, the method further includes:
and sending the entry address of the two-dimensional image slice to a driving module so as to control the driving module to acquire the two-dimensional image slice from a second memory according to the entry address and send the two-dimensional image slice to a rotary display module, so that the rotary display module displays the corresponding two-dimensional image slice according to the rotating position to realize three-dimensional display.
Compared with the prior art, the invention has the following advantages:
the method comprises the steps that a multiplexing register is provided, the multiplexing register comprises a multiplexing module, and the multiplexing module comprises an instruction output unit, a parameter output unit and an address output unit; the instruction output unit is configured to output instruction execution data corresponding to each instruction operation when the multiplexing module is in an instruction execution state, the parameter output unit is configured to output configuration data for parameter configuration of the three-dimensional display device when the multiplexing module is in a data operation state, and the address output unit is configured to output address data related to an entry address of the two-dimensional image slice when the multiplexing module is in an address synthesis state; at any moment, the multiplexing module is in any one of an instruction execution state, a data operation state and an address synthesis state. The provided multiplexing register can realize the functions of an instruction register, a data register and an address register to replace the instruction register, the data register and the address register which are arranged in the conventional three-dimensional display device, so that the number of registers required to be arranged in the three-dimensional display device is reduced, the less the registers required to be traversed by the processor are, the resource occupation of the registers on the processor can be correspondingly reduced, and the power consumption of the processor is reduced.
Drawings
FIG. 1 illustrates a schematic diagram of a multiplexing register of an embodiment of the present invention;
FIG. 2 shows a schematic diagram of a multiplexing module of an embodiment of the invention;
FIG. 3 is a diagram showing an architecture of a three-dimensional display device according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a method of controlling a three-dimensional display device according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example one
Referring to fig. 1, a schematic diagram of a multiplexing register of an embodiment of the present invention is shown.
The embodiment of the invention provides a multiplexing register 11, which is applied to a three-dimensional display device, wherein the multiplexing register 11 comprises a multiplexing module 111, and the multiplexing module 111 comprises an instruction output unit, a parameter output unit and an address output unit; an instruction output unit configured to output instruction execution data corresponding to each instruction operation when the multiplexing module 111 is in an instruction execution state; a parameter output unit configured to output configuration data for parameter configuration of the three-dimensional display apparatus when the multiplexing module 111 is in a data operation state; an address output unit configured to output address data related to an entry address of the two-dimensional image slice when the multiplexing module 111 is in an address synthesis state; at any time, the multiplexing module 111 is in any one of an instruction execution state, a data operation state and an address synthesis state.
In the embodiment of the present invention, at any time, the multiplexing register 11 may be any one of an instruction register, a data register and an address register, that is, at any time, the multiplexing module 111 in the multiplexing register 11 is in any one of an instruction execution state, a data operation state and an address synthesis state; when the multiplexing register 11 is used as an instruction register, the multiplexing module 111 in the multiplexing register 11 is in an instruction execution state, and at this time, instruction execution data corresponding to each instruction operation is stored in the multiplexing module 111; when the multiplexing register 11 is used as a data register, the multiplexing module 111 in the multiplexing register 11 is in a data operation state, and at this time, configuration data for performing parameter configuration on the three-dimensional display device is stored in the multiplexing module 111; when the multiplexing register 11 is used as an address register, the multiplexing module 111 in the multiplexing register 11 is in an address synthesis state, and at this time, address data related to the entry address of the two-dimensional image slice is stored in the multiplexing module 111.
And, the multiplexing module 111 can switch between any two operation states of the instruction execution state, the data operation state and the address synthesis state, and the rule of the operation state switching is related to the execution code written by the programmer and whether the device in the three-dimensional display device is in failure or not.
For example, after the three-dimensional display device is powered on, the multiplexing module 111 in the multiplexing register 11 is in an instruction execution state, the processor reads instruction execution data for power on self-test stored in the multiplexing module 111 at this time, and after the power on self-test is completed, data stored in the multiplexing module 111 is modified, the instruction execution data is modified into address data, so that the multiplexing module 111 is switched from the instruction execution state to the address synthesis state; or, after the power-on self-test is completed, the data stored in the multiplexing module 111 is modified, and the instruction execution data is modified into the configuration data, so that the multiplexing module 111 is switched from the instruction execution state to the data operation state.
Of course, if the configuration data or the address data is currently stored in the multiplexing module 111, when the three-dimensional display device has a fault, for example, the temperature of a certain device in the three-dimensional display device exceeds a set temperature threshold, and the system of the three-dimensional display device fails to update, the configuration data or the address data stored in the multiplexing module 111 is modified into the instruction execution data, so that the multiplexing module 111 is switched from the data operation state or the address synthesis state to the instruction execution state.
The instruction execution data is used for determining instruction operations to be executed, such as power-on self-test, interrupt priority, system fault processing and the like; the configuration data is used for determining how parameter configuration is required for the three-dimensional display device, such as configuring parameters of color depth, refresh rate and resolution of a display panel in the three-dimensional display device; the address data is used for determining the entrance address of the two-dimensional image slice required to be displayed by the rotary display module.
The three-dimensional display device comprises a rotary display module, wherein the rotary display module comprises a display panel and a driving mechanism, the driving mechanism is connected with the display panel and is used for controlling the display panel to rotate by taking a driving shaft as a center, the driving shaft can be a center line of the display panel, the display panel is used for displaying corresponding two-dimensional image slices according to a rotating position, and one frame of two-dimensional image slice is switched to display when the display panel rotates for a certain angle.
By utilizing the human eye vision retention effect, when the driving mechanism controls the display panel to rotate rapidly, a plurality of two-dimensional image slices can be simultaneously reserved in human eyes, so that a viewer can watch an image with a three-dimensional effect; the rotation frequency of the display panel is greater than or equal to 10Hz, and the refresh frequency of the two-dimensional image slice displayed on the display panel is greater than or equal to 60Hz.
For example, a rotation of the display panel is divided into 16 positions, namely, an angle 1 position, an angle 2 position, and a position up to an angle 16 position, the display panel displays the two-dimensional image slice 1 when the display panel is at the angle 1 position, the display panel displays the two-dimensional image slice 2 when the display panel is rotated from the angle 1 position to the angle 2 position, and so on, and the display panel displays the two-dimensional image slice 16 when the display panel is rotated from the angle 15 position to the angle 16 position. When the display panel is single-sided display, the number of frames of the two-dimensional image slices displayed by the display panel rotating for one circle is r frames/circle, for a viewer watching at any position, 2/r frames of the two-dimensional image slices can be seen, and a three-dimensional image watched by the viewer is formed by the 2/r frames of the two-dimensional image slices; when the display panel is in double-sided display, the number of frames of the two-dimensional image slices displayed by the display panel rotating for one circle is r frames/circle, for a viewer watching at any position, the r frames of the two-dimensional image slices can be seen, and a three-dimensional stereo image watched by the viewer is formed by the r frames of the two-dimensional image slices together.
It should be noted that, the multiplexing register 11 in the embodiment of the present invention is applied to a three-dimensional display device, and a command register, a data register, and an address register are replaced by a multiplexing register, mainly because after a rotating display module in the three-dimensional display device rotates by one angle to display a frame of two-dimensional image slice, the two-dimensional image slice at the previous angle is not needed to be reused subsequently, that is, the two-dimensional image slice at the previous angle can be discarded, and the two-dimensional image slice in the three-dimensional display device has a discardability, so that it is possible for the multiplexing register 11 to switch between a command execution state, a data operation state, and an address synthesis state without affecting the normal display of the two-dimensional image slice; the conventional display apparatus is not suitable for using one multiplexing register instead of the instruction register, the data register, and the address register because the image in the conventional display apparatus is not discardable.
For example, in a conventional display device, an image of a current frame needs to be predicted from images of previous frames to complete display, and therefore, after the previous frames of images are displayed, the previous frames of images need to be retained and cannot be discarded.
Referring to fig. 2, a schematic diagram of a multiplexing module according to an embodiment of the present invention is shown.
In the embodiment of the present invention, the bit width of the multiplexing module 111 is 8 bits, and from high to low, the multiplexing module is respectively a seventh bit 7th, a sixth bit 6th, a fifth bit 5th, a fourth bit 4th, a third bit 3th, a second bit 2nd, a first bit 1st, and a 0th bit.
The seventh bit 7th and the sixth bit 6th of the multiplexing module 111 store operation status data, where the operation status data is used to indicate an operation status of the multiplexing module 111, and the operation status includes an instruction execution status, a data operation status, and an address synthesis status.
When the operation state data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 00, determining that the multiplexing module 111 is in the instruction execution state; when the operation state data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 01, determining that the multiplexing module 111 is in a data operation state; when the operation state data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 10, determining that the multiplexing module 111 is in the address synthesis state; of course, if the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 store the operation status data of 11, this indicates that this function of the multiplexing module 111 is not used, and of course, a corresponding function may be added subsequently.
In addition, the fifth bit 5th to the 0th bit 0th of the multiplexing module 111 store the operation option and the identification data, and when the operation status data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 are different, the specific meanings corresponding to the operation option and the identification data stored in the fifth bit 5th to the 0th bit 0th of the multiplexing module 111 are different, which specifically includes the following three cases.
In the first case: when the multiplexing module 111 is in the instruction execution state, the fifth bit 5th to the third bit 3th of the multiplexing module 111 store operation data that needs to be executed in the instruction execution data, the second bit 2nd to the 0th of the multiplexing module store execution parameters corresponding to the operation data, and the execution parameters include direct execution or jump to the initial state.
When the operation status data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 00, it is determined that the multiplexing module 111 is in the instruction execution state, and the fifth bit 5th to the third bit 3th of the multiplexing module 111 store the operation data to be executed in the instruction execution data. When the operation data stored in the fifth bit 5th to the third bit 3th of the multiplexing module 111 is 000, determining that the instruction operation to be executed is a preprocessing operation; when the operation data stored in the fifth bit 5th to the third bit 3th of the multiplexing module 111 is 001, determining that the instruction operation to be executed is a power-on self-test operation; when the operation data stored in the fifth bit 5th to the third bit 3th of the multiplexing module 111 is 010, determining that the instruction operation to be executed is an interrupt priority operation; when the operation data stored in the fifth bit 5th to the third bit 3th of the multiplexing module 111 is 011, determining that the instruction operation to be executed is a system fault handling operation; when the operation data stored in the fifth bit 5th to the third bit 3th of the multiplexing module 111 is 100, determining that the instruction operation to be executed is a reset or power-off operation; of course, if the operation data stored in the fifth bit 5th to the third bit 3th of the multiplexing module 111 is 101, 110 or 111, this indicates that this function of the multiplexing module 111 is not used, and of course, corresponding functions may be added subsequently.
Correspondingly, when the multiplexing module 111 is determined to be in the instruction execution state, the second bit 2nd to the 0th bit of the multiplexing module store the execution parameters corresponding to the operation data, and the execution parameters include direct execution or jump to the initial state. When the execution parameter corresponding to the operation data stored from the second bit 2nd to the 0th bit 0th of the multiplexing module is 00, determining that the execution parameter is direct execution, and directly executing the instruction operation corresponding to the operation data; when the execution parameter corresponding to the operation data stored in the second bit 2nd to the 0th bit 0th of the multiplexing module is 01, it is determined that the execution parameter is in the initial state, and the data stored in the multiplexing module 111 is directly modified into initial data, and the initial data is pre-programmed in the process of manufacturing the multiplexing register 11.
In the second case: when the multiplexing module 111 is in the data operation state, the fifth bit 5th to the fourth bit 4th of the multiplexing module 111 store the mode data in the configuration data, and the third bit 3th to the 0th of the multiplexing module 111 store the setting parameters corresponding to the mode data.
When the operation status data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 01, it is determined that the multiplexing module 111 is in the data operation status, and the fifth bit 5th to the fourth bit 4th of the multiplexing module 111 store the mode data in the configuration data. When the pattern data stored in the fifth bit 5th to the fourth bit 4th of the multiplexing module 111 is 00, determining that the multiplexing module 111 is in the pixel mode; when the pattern data stored in the fifth bit 5th to the fourth bit 4th of the multiplexing module 111 is 01, determining that the multiplexing module 111 is in the calculation mode; when the fifth bit 5th to the fourth bit 4th of the multiplexing module 111 store the pattern data of 10, it is determined that the multiplexing module 111 is in the calibration mode.
Correspondingly, when the multiplexing module 111 is in the pixel mode, the third bit 3th to the 0th bit of the multiplexing module 111 store setting parameters corresponding to the pixel mode, such as color depth, refresh rate, resolution, and the like; when the multiplexing module 111 is in the calculation mode, the third bit 3th to the 0th of the multiplexing module 111 stores a configuration formula coefficient, where the configuration formula coefficient refers to a coefficient used for calculating a specific gray value of a pixel of a two-dimensional image slice, and because the two-dimensional image slice is stored, in order to reduce an occupied space of the two-dimensional image slice, the two-dimensional image slice is not completely stored according to the gray value of each pixel, and it needs to be calculated according to the gray value of a related pixel, for example, the gray value of the next pixel needs to be calculated according to the gray value of the previous pixel multiplied by the configuration formula coefficient, and if the gray value of the previous pixel is gray10 and the configuration formula coefficient is 4, the gray value of the next pixel is calculated to be gray40; when the multiplexing module 111 is in the calibration mode, the third bit 3th to the 0th bit of the multiplexing module 111 stores correction parameters, such as Gamma (Gamma) correction parameters, color correction parameters, and the like, and marks a correction address.
In the third case: when the multiplexing module 111 is in the address synthesis state, the fifth bit 5th of the multiplexing module 111 stores the address change mode data in the address data; when the address change mode data is the equal interval gradient data, the fourth bit 4th to the 0th bit of the multiplexing module 111 store step sizes, and when the address change mode data is the scattered distribution data, the fourth bit 4th to the 0th bit of the multiplexing module 111 store the indication data for indicating the entry address of the next frame of two-dimensional image slice.
When the operation status data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 10, it is determined that the multiplexing module 111 is in the address synthesis state, and the fifth bit 5th of the multiplexing module 111 stores the address change mode data in the address data. When the address change mode data stored in the fifth bit 5th of the multiplexing module 111 is 0, that is, the address change mode data is the equal interval tapered data, the fourth bit 4th to the 0th bit of the multiplexing module 111 store the step size, that is, the change interval of the address; when the address change manner data stored in the fifth bit 5th of the multiplexing module 111 is 1, that is, the address change manner data is the scattered distribution data, the fourth bit 4th to the 0th bit of the multiplexing module 111 store the indication data for indicating the entry address of the two-dimensional image slice of the next frame, and the indication data is used for indicating the location where the entry address of the two-dimensional image slice is stored.
For example, if the address change pattern data is equal interval gradient data and the step size is 2, if the instruction data of the entry address of the first frame two-dimensional image slice is 1, the instruction data of the entry address of the second frame two-dimensional image slice is 3, if the address change pattern data is not changed, the instruction data of the entry address of the third frame two-dimensional image slice is 5, and so on.
As shown in fig. 1, the multiplexing register 11 further includes an address storage block 112; an address storage module 112 configured to store an entry address of the current two-dimensional image slice and an entry address of the next frame two-dimensional image slice.
When the multiplexing module 111 is in an address synthesis state, address data related to an entry address of a two-dimensional image slice is output, and the processor can determine indicating data for indicating the entry address of the two-dimensional image slice according to the address data, specifically, if address change mode data in the address data is equal-interval tapered data, the step length is directly added according to the indicating data of the entry address of the current two-dimensional image slice to obtain indicating data of the entry address of the next frame of two-dimensional image slice; if the address change mode data in the address data is scattered data, directly acquiring data from the fourth bit 4th to the 0th bit in the address data to obtain indication data; the processor then obtains the entry address of the two-dimensional image slice according to the indication data, writes the entry address of the current two-dimensional image slice and the entry address of the next two-dimensional image slice into the address storage module 112 in the multiplexing register 11, and the address storage module 112 stores the entry address of the current two-dimensional image slice and the entry address of the next two-dimensional image slice.
It should be noted that the instruction data of the entry address of the first frame of two-dimensional image slice is determined by the execution code written by the programmer, the instruction data of the entry address of the second frame of two-dimensional image slice is determined according to the address data stored in the multiplexing module 111, so as to determine the instruction data of the entry addresses of all the two-dimensional image slices, and the entry address of the two-dimensional image slice is obtained according to the instruction data, so as to ensure normal display of the two-dimensional image slice.
As shown in fig. 1, the multiplexing register 11 further includes an error correction module 113, and the error correction module 113 includes a data modification unit; and the data modification unit is configured to modify the data stored in the multiplexing module 111 to enable the multiplexing module 111 to output instruction execution data for resetting or powering off the three-dimensional display device when the number of times that any one device in the three-dimensional display device executes the same operation is greater than a set number of times.
If the number of times that any device in the three-dimensional display device executes the same operation is greater than the set number of times, that is, the device has a fault, an execution instruction has an endless loop, a data modification unit in the error correction module 113 modifies data stored in the multiplexing module 111, for example, modifies data stored in the multiplexing module 111 into instruction execution data 00100xx, so that the multiplexing module 111 outputs instruction execution data 00100xx for resetting or powering off the three-dimensional display device, and then executes resetting or powering off according to the instruction execution data 00100xx, wherein the data in 'xx' can be selected to execute software resetting or hardware resetting and control the power off of the whole device or the power off of the local device, and if the power off of the local device is present, the power off of the display panel can be controlled, but the driving mechanism is not powered off.
In addition, the error correction module 113 further includes a parameter passing unit; a parameter passing unit configured to pass the engagement parameter of a plurality of multiplexing registers cascaded with the multiplexing register.
In the three-dimensional display device, a plurality of cascaded multiplexing registers 11 may be provided, and the error correction module 113 may also pass the connection parameters of a plurality of multiplexing registers 11 cascaded with any multiplexing register 11, such as passing the entry of the cascaded lower multiplexing register 11, besides ensuring the normal execution of the device.
In the embodiment of the invention, a multiplexing register is provided, and the multiplexing register comprises a multiplexing module, wherein the multiplexing module comprises an instruction output unit, a parameter output unit and an address output unit; an instruction output unit configured to output instruction execution data corresponding to each instruction operation when the multiplexing module is in an instruction execution state, a parameter output unit configured to output configuration data for parameter configuration of the three-dimensional display device when the multiplexing module is in a data operation state, an address output unit configured to output address data related to an entry address of the two-dimensional image slice when the multiplexing module is in an address synthesis state; at any moment, the multiplexing module is in any one of an instruction execution state, a data operation state and an address synthesis state. The provided multiplexing register can realize the functions of an instruction register, a data register and an address register to replace the instruction register, the data register and the address register which are arranged in the conventional three-dimensional display device, so that the number of the registers which need to be arranged in the three-dimensional display device is reduced, the less the registers need to be traversed by the processor, the resource occupation of the registers on the processor can be correspondingly reduced, and the power consumption of the processor is reduced.
Example two
Referring to fig. 3, an architecture diagram of a three-dimensional display device according to an embodiment of the present invention is shown.
The invention provides a three-dimensional display device, which comprises a first memory 31, a processor 32 and a multiplexing register 11 of the first embodiment, wherein the processor 32 comprises a data reading module, an instruction executing module, a parameter configuration module and an address obtaining module.
Wherein the first memory 31 is configured to store entry addresses of two-dimensional image slices; a data reading module configured to read data stored in the multiplexing module 111 in the multiplexing register 11 to determine an operation state of the multiplexing module 111; the instruction execution module is configured to execute corresponding instruction operations according to the instruction execution data when the multiplexing module 111 is in an instruction execution state; the parameter configuration module is configured to perform parameter configuration on the three-dimensional display device according to the configuration data when the multiplexing module 111 is in the data operation state; an address acquisition module configured to determine, when the multiplexing module 111 is in the address synthesis state, instruction data for instructing an entry address of the two-dimensional image slice from the address data, and acquire the entry address of the two-dimensional image slice stored in the first memory 31 from the instruction data.
The first memory 31 is used for storing entry addresses of the two-dimensional image slices, such as Add1, add2, add3 through Add (N-1) and Add (N), wherein each entry address corresponds to one two-dimensional image slice; the processor 32 traverses the multiplexing register 11 in real time, and when the data stored in the multiplexing register 11 at this time is different from the data stored in the previous time, the data reading module reads the data stored in the multiplexing module 111 in the multiplexing register 11 to determine the operating state of the multiplexing module 111. When the multiplexing module 111 is in the instruction execution state, the multiplexing module 111 outputs instruction execution data corresponding to each instruction operation, and the instruction execution module executes the corresponding instruction operation according to the instruction execution data; when the multiplexing module 111 is in a data operation state, the multiplexing module 111 outputs configuration data for performing parameter configuration on the three-dimensional display device, and the parameter configuration module performs parameter configuration on the three-dimensional display device according to the configuration data; when the multiplexing module 111 is in the address combining state, the multiplexing module 111 outputs address data associated with the entry addresses of the two-dimensional image slices, and the address acquisition module determines, based on the address data, instruction data for indicating the entry addresses of the two-dimensional image slices, and acquires, based on the instruction data, the entry addresses of the two-dimensional image slices stored in the first memory 31, the instruction data indicating which of all the entry addresses stored in the first memory 31 the entry address of the two-dimensional image slice is.
As shown in fig. 3, the three-dimensional display device further includes a second memory 33, a driving module 34, and a rotating display module 35, and the processor 32 further includes an address sending module; a second memory 33 configured to store two-dimensional image slices; an address transmission module configured to transmit an entry address of the two-dimensional image slice to the driving module 34; the driving module 34 is configured to acquire the two-dimensional image slice from the second memory 33 according to the entry address and send the two-dimensional image slice to the rotating display module 35; and the rotary display module 35 is configured to display the corresponding two-dimensional image slice according to the rotation position to realize three-dimensional display.
The second memory 33 is used for storing two-dimensional image slices, such as Data1, data2, data3, up to Data (m × n-1) and Add (m × n), after the address acquiring module in the processor 32 acquires the entry address Add (k) of the two-dimensional image slice stored in the first memory 31 according to the indication Data, the address transmitting module in the processor 32 transmits the entry address Add (k) of the two-dimensional image slice to the driving module 34, the driving module 34 acquires the two-dimensional image slice Data (k) from the second memory 33 according to the entry address and transmits the two-dimensional image slice Data (k) to the rotating display module 35, and the rotating display module 35 displays the corresponding two-dimensional image slice according to the rotating position, so that the viewer views an image with three-dimensional stereoscopic effect.
The multiplexing register 11 may be built in the processor 32, or may not be built in the processor 32; the second memory 33 refers to a memory storing two-dimensional image slices, which may in fact be more than one memory, e.g. two-dimensional image slices may be stored with scattered spatial partitions of the respective memories.
In addition, the two-dimensional image slices stored in each partition may also have different configuration data, such as setting the two-dimensional image slice in the attention area of human eyes to 16-bit color depth, and setting the two-dimensional image slice in the attention area of non-human eyes to 8-bit color depth, so as to reduce the amount of computation without affecting the display effect of the rotating display module 35.
In the embodiment of the invention, the provided multiplexing register can realize the functions of an instruction register, a data register and an address register to replace the instruction register, the data register and the address register which are arranged in the conventional three-dimensional display device, so that the number of registers required to be arranged in the three-dimensional display device is reduced, the less the registers required to be traversed by a processor are, the resource occupation of the registers to the processor is correspondingly reduced, and the power consumption of the processor is reduced.
EXAMPLE III
Referring to fig. 4, a flowchart of a method for controlling a three-dimensional display device according to an embodiment of the present invention is shown, which may specifically include the following steps:
In the embodiment of the present invention, the processor 32 traverses the multiplexing register 11 in real time, and reads the data stored in the multiplexing module 111 in the multiplexing register 11 when the data stored in the multiplexing register 11 at this time is different from the data stored in the previous time, so as to determine the operating state of the multiplexing module 111.
Specifically, the seventh bit 7th and the sixth bit 6th of the data stored in the multiplexing module 111 are read, when the operation state data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 00, it is determined that the multiplexing module 111 is in the instruction execution state, when the operation state data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 01, it is determined that the multiplexing module 111 is in the data operation state, and when the operation state data stored in the seventh bit 7th and the sixth bit 6th of the multiplexing module 111 is 10, it is determined that the multiplexing module 111 is in the address synthesis state.
And 402, when the multiplexing module is in an instruction execution state, executing data according to the instruction to execute a corresponding instruction operation.
In the embodiment of the present invention, when the multiplexing module 111 is in the instruction execution state, the multiplexing module executes corresponding instruction operations, such as a preprocessing operation, a power-on self-test operation, an interrupt priority operation, a system fault handling operation, a reset or power-off operation, according to the instruction execution data, where the instruction operations are mainly executed when the power-on self-test or the three-dimensional display device fails, and do not participate in the normal display of the two-dimensional image slice by the three-dimensional display device.
And 403, when the multiplexing module is in a data operation state, performing parameter configuration on the three-dimensional display device according to the configuration data.
In the embodiment of the present invention, when the multiplexing module 111 is in the data operation state, the three-dimensional display device is configured according to the configuration data, such as configuring the color depth, the refresh rate and the resolution of the display panel, and configuring the rotation speed of the driving mechanism.
In the embodiment of the present invention, when the multiplexing module 111 is in the address synthesis state, the instruction data for instructing the entry address of the two-dimensional image slice is determined from the address data, and the entry address of the two-dimensional image slice stored in the first memory 31 is acquired from the instruction data.
After step 404, further comprising: and sending the entry address of the two-dimensional image slice to a driving module so as to control the driving module to acquire the two-dimensional image slice from a second storage according to the entry address and send the two-dimensional image slice to a rotary display module, so that the rotary display module displays the corresponding two-dimensional image slice according to the rotating position to realize three-dimensional display.
The processor 32, after acquiring the entry address of the two-dimensional image slice stored in the first memory 31 according to the indication data, sends the entry address of the two-dimensional image slice to the driving module 34, so as to control the driving module 34 to acquire the two-dimensional image slice from the second memory 33 according to the entry address, and sends the two-dimensional image slice to the rotary display module 35, so that the rotary display module 35 displays the corresponding two-dimensional image slice according to the rotation position to realize three-dimensional display, and a viewer views an image with three-dimensional stereoscopic effect.
In the embodiment of the invention, the provided multiplexing register can realize the functions of the instruction register, the data register and the address register to replace the instruction register, the data register and the address register which are arranged in the conventional three-dimensional display device, so that the number of the registers which need to be arranged in the three-dimensional display device is reduced, and the registers which need to be traversed by the processor are fewer, so that the resource occupation of the registers on the processor is correspondingly reduced, and the power consumption of the processor is reduced.
For simplicity of explanation, the foregoing method embodiments are presented as a series of interrelated acts, but it should be appreciated by those skilled in the art that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the present invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus comprising the element.
The multiplexing register, the three-dimensional display device and the control method thereof provided by the present invention are introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A multiplexing register, applied to a three-dimensional display device,
the multiplexing register comprises a multiplexing module, and the multiplexing module comprises an instruction output unit, a parameter output unit and an address output unit;
the bit width of the multiplexing module is 8 bits;
the instruction output unit is configured to output instruction execution data corresponding to each instruction operation when the multiplexing module is in an instruction execution state;
the parameter output unit is configured to output configuration data for performing parameter configuration on the three-dimensional display device when the multiplexing module is in a data operation state;
the address output unit is configured to output address data related to an entry address of a two-dimensional image slice when the multiplexing module is in an address synthesis state;
at any moment, the multiplexing module is in any one of the instruction execution state, the data operation state and the address synthesis state;
when the multiplexing module is in the address synthesis state, a seventh bit and a sixth bit of the multiplexing module store operation state data, where the operation state data is used to indicate an operation state of the multiplexing module, and the operation state includes the instruction execution state, the data operation state, and the address synthesis state;
when the multiplexing module is in the instruction execution state, the fifth bit to the third bit of the multiplexing module store operation data which needs to be executed in the instruction execution data, the second bit to the 0th bit of the multiplexing module store execution parameters corresponding to the operation data, and the execution parameters comprise direct execution or jump to an initial state;
when the multiplexing module is in the data operation state, fifth bit to fourth bit of the multiplexing module store the mode data in the configuration data, and third bit to 0 bit of the multiplexing module store the setting parameters corresponding to the mode data;
a fifth bit of the multiplexing module stores address change mode data in the address data; when the address change mode data is the equal-interval gradient data, the fourth bit to the 0th bit of the multiplexing module stores step length, and when the address change mode data is the scattered distribution data, the fourth bit to the 0th bit of the multiplexing module stores indicating data used for indicating the entry address of the next frame of two-dimensional image slice.
2. The multiplexing register of claim 1, wherein the multiplexing register further comprises an address storage module;
the address storage module is configured to store an entry address of a current two-dimensional image slice and an entry address of a next frame two-dimensional image slice.
3. The multiplexing register of claim 1, further comprising an error correction module, the error correction module comprising a data modification unit;
the data modification unit is configured to modify the data stored in the multiplexing module when the number of times of executing the same operation by any one device in the three-dimensional display device is larger than a set number of times, so that the multiplexing module outputs instruction execution data for resetting or powering off the three-dimensional display device.
4. The multiplexing register of claim 3, wherein the error correction module further comprises a parameter passing unit;
the parameter passing unit is configured to pass the join parameter of a plurality of multiplexing registers cascaded with the multiplexing register.
5. A three-dimensional display device comprising a first memory, a processor and the multiplexing register of any one of claims 1 to 4, the processor comprising a data reading module, an instruction execution module, a parameter configuration module and an address acquisition module;
the first memory configured to store entry addresses of two-dimensional image slices;
the data reading module is configured to read data stored in the multiplexing module in the multiplexing register so as to determine the operating state of the multiplexing module;
the instruction execution module is configured to execute corresponding instruction operation according to the instruction execution data when the multiplexing module is in an instruction execution state;
the parameter configuration module is configured to perform parameter configuration on the three-dimensional display device according to the configuration data when the multiplexing module is in a data operation state;
the address acquisition module is configured to determine, when the multiplexing module is in an address synthesis state, instruction data for instructing entry addresses of two-dimensional image slices according to the address data, and acquire the entry addresses of the two-dimensional image slices stored in the first memory according to the instruction data.
6. The three-dimensional display device according to claim 5, wherein the three-dimensional display device further comprises a second memory, a driving module and a rotating display module, and the processor further comprises an address sending module;
the second memory configured to store the two-dimensional image slice;
the address sending module is configured to send an entry address of the two-dimensional image slice to the driving module;
the driving module is configured to acquire the two-dimensional image slice from the second memory according to the entry address and send the two-dimensional image slice to the rotary display module;
and the rotary display module is configured to display the corresponding two-dimensional image slice according to the rotation position so as to realize three-dimensional display.
7. A control method of a three-dimensional display device, applied to the three-dimensional display device according to claim 6, the method comprising:
reading data stored in a multiplexing module in the multiplexing register to determine the operating state of the multiplexing module;
when the multiplexing module is in an instruction execution state, executing corresponding instruction operation according to the instruction execution data;
when the multiplexing module is in a data operation state, parameter configuration is carried out on the three-dimensional display device according to the configuration data;
and when the multiplexing module is in an address synthesis state, determining indicating data for indicating an entry address of a two-dimensional image slice according to the address data, and acquiring the entry address of the two-dimensional image slice stored in the first memory according to the indicating data.
8. The method of claim 7, further comprising, after the step of obtaining entry addresses of two-dimensional image slices stored in the first memory according to the indication data:
and sending the entry address of the two-dimensional image slice to a driving module so as to control the driving module to acquire the two-dimensional image slice from a second memory according to the entry address and send the two-dimensional image slice to a rotary display module, so that the rotary display module displays the corresponding two-dimensional image slice according to the rotating position to realize three-dimensional display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911193660.5A CN112859377B (en) | 2019-11-28 | 2019-11-28 | Multiplexing register, three-dimensional display device and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911193660.5A CN112859377B (en) | 2019-11-28 | 2019-11-28 | Multiplexing register, three-dimensional display device and control method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112859377A CN112859377A (en) | 2021-05-28 |
| CN112859377B true CN112859377B (en) | 2023-03-14 |
Family
ID=75995765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911193660.5A Active CN112859377B (en) | 2019-11-28 | 2019-11-28 | Multiplexing register, three-dimensional display device and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112859377B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09247239A (en) * | 1996-03-11 | 1997-09-19 | Furukawa Electric Co Ltd:The | Multiplex transmission system |
| CN1173668A (en) * | 1996-08-06 | 1998-02-18 | 三星电子株式会社 | Error correcting apparatus and method of digital processing system |
| CN1334525A (en) * | 2000-06-30 | 2002-02-06 | 英特尔公司 | General register file structure for alignment of single instruction-multiple data |
| CN1556593A (en) * | 2003-12-31 | 2004-12-22 | 中兴通讯股份有限公司 | Digital interface circuit in light synchronous digit transmission system and its data demultiplexing method |
| CN1914592A (en) * | 2003-12-09 | 2007-02-14 | Arm有限公司 | Method and equipment for executing compressed data operation with cell size control |
| CN101504599A (en) * | 2009-03-16 | 2009-08-12 | 西安电子科技大学 | Special instruction set micro-processing system suitable for digital signal processing application |
| CN102866982A (en) * | 2012-09-14 | 2013-01-09 | 复旦大学 | Eight-bit complex instruction set central processor based on FPGA (Field Programmable Gata Array) |
| CN103607583A (en) * | 2013-11-19 | 2014-02-26 | 京东方科技集团股份有限公司 | Display method, display device and display system for shutter type three dimensional image |
| CN104732592A (en) * | 2015-04-03 | 2015-06-24 | 徐超 | Real-time three-dimensional data generation method based on two-dimensional LED rotating screen |
-
2019
- 2019-11-28 CN CN201911193660.5A patent/CN112859377B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09247239A (en) * | 1996-03-11 | 1997-09-19 | Furukawa Electric Co Ltd:The | Multiplex transmission system |
| CN1173668A (en) * | 1996-08-06 | 1998-02-18 | 三星电子株式会社 | Error correcting apparatus and method of digital processing system |
| CN1334525A (en) * | 2000-06-30 | 2002-02-06 | 英特尔公司 | General register file structure for alignment of single instruction-multiple data |
| CN1914592A (en) * | 2003-12-09 | 2007-02-14 | Arm有限公司 | Method and equipment for executing compressed data operation with cell size control |
| CN1556593A (en) * | 2003-12-31 | 2004-12-22 | 中兴通讯股份有限公司 | Digital interface circuit in light synchronous digit transmission system and its data demultiplexing method |
| CN101504599A (en) * | 2009-03-16 | 2009-08-12 | 西安电子科技大学 | Special instruction set micro-processing system suitable for digital signal processing application |
| CN102866982A (en) * | 2012-09-14 | 2013-01-09 | 复旦大学 | Eight-bit complex instruction set central processor based on FPGA (Field Programmable Gata Array) |
| CN103607583A (en) * | 2013-11-19 | 2014-02-26 | 京东方科技集团股份有限公司 | Display method, display device and display system for shutter type three dimensional image |
| CN104732592A (en) * | 2015-04-03 | 2015-06-24 | 徐超 | Real-time three-dimensional data generation method based on two-dimensional LED rotating screen |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112859377A (en) | 2021-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102371906B1 (en) | Display device, mobile device having the same, and method of operating display device | |
| US10134106B2 (en) | Method and device for selective display refresh | |
| CN103530078A (en) | System and method for displaying a mirror | |
| JP6730325B2 (en) | Terminal switching display method and terminal | |
| US8913002B1 (en) | Determining when to perform a flash of a display | |
| CN102750072B (en) | Display method for accelerating updating picture | |
| US10706765B2 (en) | Compression algorithm verification method, storage medium, and display device | |
| CN111477147A (en) | Image processing method and device and electronic equipment | |
| CN106611592A (en) | Display method, device and system based on flexible display screen | |
| GB2564866A (en) | Method of and data processing system for providing an output surface | |
| CN109147664B (en) | AMOLED display screen | |
| CN112859377B (en) | Multiplexing register, three-dimensional display device and control method thereof | |
| US9542721B2 (en) | Display control device and data processing system | |
| CN110456900B (en) | Interface circuit, display driver, terminal device and display control method | |
| CN106918324B (en) | Information processing apparatus, information processing method, and storage medium | |
| JP2010181573A (en) | Image processing apparatus, information processing apparatus, mobile terminal device, and image processing method | |
| US20150317185A1 (en) | Method for switching operating system and electronic device using the method | |
| CN108765541A (en) | A kind of 3D scenario objects display methods, device, equipment and storage medium | |
| CN109992230B (en) | Control method and electronic device | |
| CN115100417A (en) | Image processing method, storage medium, and electronic device | |
| JP2005140958A (en) | Display device and portable equipment using the same | |
| CN109857295A (en) | Control method, device and the storage medium of focus | |
| WO2018086960A1 (en) | Method and device for transmitting data representative of an image | |
| JP6635141B2 (en) | Information processing apparatus, control method, and program | |
| US20200410917A1 (en) | Electronic Display Device And Electronic Display Method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |