CN112769489B - Control-free half-duplex-simplex switching circuit - Google Patents
Control-free half-duplex-simplex switching circuit Download PDFInfo
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- CN112769489B CN112769489B CN201911064552.8A CN201911064552A CN112769489B CN 112769489 B CN112769489 B CN 112769489B CN 201911064552 A CN201911064552 A CN 201911064552A CN 112769489 B CN112769489 B CN 112769489B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/40—Transceivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission
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Abstract
The invention discloses a control-free half-duplex-simplex switching circuit, which comprises: an input-output port; the input end of the transmitting branch is connected with the input/output port, and the transmitting branch outputs a driving signal according to an input electric signal; the input end of the receiving branch circuit receives the detection signal, the output end of the receiving branch circuit is connected with the input/output port, and the receiving branch circuit transmits an electric signal to the input/output port according to the received detection signal; the signal peak detection unit senses whether the receiving branch circuit receives an effective signal or not and outputs a control signal at an output end, when the amplitude of oscillation of an input signal of the receiving branch circuit exceeds a threshold value, the output of the signal peak detection unit is in a first state, and otherwise, the output of the signal peak detection unit is in a second state; and the control logic unit is connected with the output end of the signal peak value detection unit, and when the control signal is in a first state, the control logic unit closes the transmitting branch and opens the receiving branch, and when the control signal is in a second state, the control logic unit opens the transmitting branch and closes the receiving branch.
Description
Technical Field
The invention relates to the technical field of communication. In particular, the invention relates to a control-free half-duplex-simplex switching circuit.
Background
In consumer data interconnect applications, as represented by the USB (Universal Serial Bus) protocol, the origin of the technology is copper wire connection, which enables signal transmission in one and only one direction on the copper wire at the same time, i.e. so-called half-duplex transmission. In optical communication or optical interconnection, there is a need for half duplex-simplex conversion because optical signal transmission in optical fiber is unidirectional.
Fig. 1 shows a block diagram of an existing optical interconnect link structure. As shown in fig. 1, the first end 110 and the second end 120 of the optical interconnect link are interconnected by an optical fiber 130. The first terminal 110 includes separate transmit and receive circuits. The second terminal 120 also includes separate transmit and receive circuits. When a signal is transmitted from the transmitting circuit of the first end 110 to the receiving circuit of the second end 120 along the first direction, the signal transmission path is: the electrical signal to be transmitted enters the input buffer 111 of the transmitting circuit, then is transmitted to the laser 113 via the output driver 112, and is converted into an emitting optical signal by the laser 113, and the emitting optical signal is transmitted to the receiving circuit of the second end 120 through the optical fiber 130; the photodiode 121 at the second end 120 converts the received optical signal into an electrical signal, sends the electrical signal to the transimpedance amplifier 122, is processed by the transimpedance amplifier 122 and then sends the electrical signal to the output end post-amplifier 123, and the output end post-amplifier 123 finally outputs the electrical signal. Similarly, when the signal is transmitted from the transmitting circuit of the second end 120 to the receiving circuit of the first end 110 along the second direction, the signal transmission mode is as follows: the electrical signal to be transmitted enters the input buffer 126 of the transmitting circuit, and then is transmitted to the laser 124 via the output driver 125, and is converted into an emitting optical signal by the laser 124, and the emitting optical signal is transmitted to the receiving circuit of the first end 110 through the optical fiber 130; the photodiode 116 at the first end 110 converts the received optical signal into an electrical signal, sends the electrical signal to the transimpedance amplifier 115, is processed by the transimpedance amplifier 115 and then sends the electrical signal to the output end post-amplifier 114, and the output end post-amplifier 114 finally outputs the electrical signal.
In the prior art, even if the Wavelength Division Multiplexing (WDM) technology is used to transmit signals in two directions in the same optical fiber, the transmitting and receiving circuits are simplex and must be separated.
Therefore, in optical communication or optical interconnection, a circuit capable of performing duplex-simplex conversion is required to solve the problem that optical signal transmission in an optical fiber is unidirectional.
Disclosure of Invention
The present invention is directed to converting an existing simplex optical interconnect link into a duplex link.
According to an embodiment of the present invention, there is provided a control-free half duplex-simplex switching circuit, including:
an input-output port;
the input end of the transmitting branch is connected with the input/output port, and the transmitting branch outputs a driving signal according to an input electric signal;
the input end of the receiving branch circuit receives the detection signal, the output end of the receiving branch circuit is connected with the input/output port, and the receiving branch circuit transmits an electric signal to the input/output port according to the received detection signal;
the signal peak detection unit senses whether the receiving branch circuit receives an effective signal or not and outputs a control signal at an output end, when the amplitude of oscillation of an input signal of the receiving branch circuit exceeds a threshold value, the output of the signal peak detection unit is in a first state, and otherwise, the output of the signal peak detection unit is in a second state; and
and the control logic unit is connected with the output end of the signal peak value detection unit, and when the control signal is in a first state, the control logic unit closes the transmitting branch and opens the receiving branch, and when the control signal is in a second state, the control logic unit opens the transmitting branch and closes the receiving branch.
In an embodiment of the present invention, the receiving branch includes a detector, a transimpedance amplifier, and an output buffer, the detector generates an electrical signal after detecting an optical signal, the transimpedance amplifier receives the electrical signal output by the detector and outputs a differential signal at an inverting output terminal and an non-inverting output terminal thereof, the non-inverting input terminal and the inverting input terminal of the output buffer are respectively connected to the inverting output terminal and the non-inverting output terminal of the transimpedance amplifier, and the non-inverting output terminal and the inverting output terminal of the output buffer are respectively connected to the input/output port.
In one embodiment of the invention, the transimpedance amplifier comprises a limiting amplifier.
In one embodiment of the invention, in the initial state, only the trans-impedance amplifier parts of the transmitting branch and the receiving branch work, and the output buffer does not work.
In one embodiment of the present invention, an input terminal of the signal peak detection unit is connected to an inverting output terminal and a non-inverting output terminal of the transimpedance amplifier.
In one embodiment of the present invention, a signal detection circuit includes: the circuit comprises a differential peak value detection circuit, a common mode extraction circuit, a common mode level lifting circuit and a comparator. The differential peak value detection circuit is connected to the in-phase output end and the reverse-phase output end of the trans-impedance amplifier and used for receiving the detected differential signal so as to extract the highest level of the input differential signal; the common mode extraction circuit is connected to the in-phase output end and the reverse-phase output end of the trans-impedance amplifier and used for receiving the detected differential signal so as to extract the common mode level of the input differential signal; the common mode level lifting circuit increases a difference value on the basis of the extracted common mode level; the comparator compares the output of the common mode extraction level boost circuit with the output of the differential peak detection, and when the swing amplitude of the input differential signal exceeds the boost difference value, the output result of the comparator is in a first state.
In an embodiment of the present invention, the differential peak detection circuit is a differential follower composed of two triodes, the common mode extraction circuit includes a first resistor and a second resistor connected in parallel, one end of the first resistor and one end of the second resistor are respectively connected to the detected differential signal, and the other end of the first resistor and the other end of the second resistor are connected to output the common mode level.
In one embodiment of the invention, the first state is high and the second state is low.
In one embodiment of the present invention, the control logic unit is an SR flip-flop.
In one embodiment of the invention, the drive signal output by the transmit branch is used to drive a laser or modulator.
According to an embodiment of the present invention, there is provided a control method for a control-free half-duplex-simplex switching circuit, including:
in the initial state, the transmitting branch is in the standby state, the receiving branch is in the blocking and standby state,
when the receiving branch detects a signal, blocking the transmitting branch and then starting the receiving branch, wherein the blocking of the transmitting branch must occur before the starting of the receiving branch;
when the receiving branch loses the signal, it returns to the initial state, in which the receiving branch enters the blocking state and the standby state should enter the standby state prior to the transmitting branch.
Wherein the state that the emission branch is opened (on) is connoted as: all circuit units are started, the signal detection circuit finds that the input/output port to-be-transmitted electric signal exists, and a drive circuit of the signal detection circuit is started;
the Standby (Standby) state of the transmitting branch circuit is defined as follows: the driving circuit is closed, and the signal detection circuit monitors whether the input/output port has an electric signal to be transmitted in real time;
the transmitting branch blocks (Block) state, the connotation is: the driving circuit is closed, and the first-stage circuit connected with the input/output port is disconnected, namely, the signal on the input/output port is not transmitted to the interior of the transmitting branch circuit, and the signal detection unit does not sense the existence of the signal on the input/output port;
the receiving branch circuit is in an open (on) state, and the connotation is as follows: all circuit units are opened, and the signal detection unit finds a signal to be detected and opens the output stage of the signal detection unit to be connected with the external input/output port;
the receiving branch is blocked and stands by (Block & Standby), and the connotation is as follows: the output stage is closed, i.e. disconnected from the external input/output port; the signal detection unit monitors whether a signal to be detected exists in real time;
note that: the commonality of the block state is that the circuit elements connected to the input/output ports are disconnected.
In another embodiment of the present invention, when the transmitting branch detects a signal, the transmitting branch is turned on, and the receiving branch is in a blocking and standby state; and when the transmitting branch loses the signal, returning to the initial state.
In another embodiment of the invention, the initial state is returned when both the transmitting branch and the receiving branch lose signals.
According to yet another embodiment of the present invention, there is provided an optical interconnect link of a duplex-simplex conversion circuit, including:
a left duplex-simplex switching circuit;
a duplex-simplex switching circuit on the right side,
wherein left side and right side duplex-simplex converting circuit all include: an input-output port; the input end of the transmitting branch is connected with the input/output port, and the transmitting branch outputs a driving signal according to an input electric signal; the input end of the receiving branch circuit receives the detection signal, the output end of the receiving branch circuit is connected with the input/output port, and the receiving branch circuit transmits an electric signal to the input/output port according to the received detection signal; the signal peak detection unit senses whether the receiving branch circuit receives an effective signal or not and outputs a control signal at an output end, when the amplitude of oscillation of an input signal of the receiving branch circuit exceeds a threshold value, the output of the signal peak detection unit is in a first state, and otherwise, the output of the signal peak detection unit is in a second state; and a control logic unit, the control logic unit is connected with the output end of the signal peak value detection unit, when the control signal is in a first state, the control logic unit blocks the transmitting branch and starts the receiving branch, wherein the blocking of the transmitting branch must occur before the starting of the receiving branch, when the control signal is in a second state, the control logic unit starts the transmitting branch and blocks the receiving branch,
wherein the left transmitting branch is connected to the right receiving branch through a first unidirectional transmission channel, the left receiving branch is connected to the right receiving branch through a second unidirectional transmission channel,
wherein the opening of the left or right transmitting branch triggers a condition for the opposite receiving branch to detect a signal.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
Fig. 1 shows a block diagram of an existing optical interconnect link structure.
FIG. 2A shows a schematic block diagram of an optical interconnect link for a duplex-simplex conversion circuit for an optical interconnect, according to one embodiment of the invention.
FIG. 2B illustrates the timing relationship of a plurality of nodes in the circuit shown in FIG. 2A.
Fig. 2C shows a state machine for an optical interconnect link comprised of two-sided duplex-simplex switching circuits.
Fig. 3A shows a schematic diagram of a duplex-simplex switching circuit for optical interconnects, according to one embodiment of the invention.
Fig. 3B shows a schematic diagram of a duplex-simplex switching circuit for optical interconnects according to another embodiment of the present invention.
FIG. 4 illustrates the timing relationships of a plurality of nodes in the circuit shown in FIG. 3A.
FIG. 5 shows a schematic block diagram of a signal detection circuit according to one embodiment of the present invention.
FIG. 6 shows a schematic diagram of a signal detection circuit according to one embodiment of the invention.
Detailed Description
In the following description, the invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention may be practiced without specific details. Further, it should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Reference in the specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
Noun interpretation
In describing the present invention, the following terms are used in their conception and are briefly explained in order to facilitate the understanding of the present invention.
Simplex worker
Simplex means that terminal a can only signal and terminal B can only receive signals, and the communication is unidirectional.
Half duplex
Half duplex means that terminal a can signal terminal B and terminal B can signal terminal a, but the two processes cannot be performed simultaneously.
Full duplex
Full duplex means that both terminals a and B can be used as the transceiving ends of signals, and the transceiving of signals can be performed simultaneously.
It should be noted that the duplex communications described in the present invention refer to half duplex communications, that is, signals transmitted in only one direction exist at the same time. Signals in both directions do not exist simultaneously.
FIG. 2A shows a schematic block diagram of an optical interconnect link for a duplex-simplex conversion circuit for an optical interconnect, according to one embodiment of the invention. As shown in fig. 2A, the left and right sides of the optical interconnect link are interconnected by unidirectional transmission channels. The left and right sides are substantially identical in structure, and therefore, the left side will be described in detail hereinafter, and the description of the right side will be omitted.
In the case of a device with duplex transmission requirements, only one differential Input/output port (I/O port) 211 and 221 are provided on the left side and the right side, respectively. The switching circuit needs to have an automatic sense of the port's transmission direction requirements and then the configuration circuit provides only transmission from left to right or only transmission from right to left.
As shown in fig. 2A, at the left side, the duplex-simplex switching circuit for optical interconnection includes: an input output port 211, an optical transmitting branch 212, an optical receiving branch 213, a signal peak detection unit 214 and a control logic unit 215. The input/output port 211 is connected to other devices, and can transmit/receive an electrical signal to/from other devices. The optical transmit branch 212 has an input connected to the input/output port 211 and an output connectable to an optical fiber for transmitting optical signals into the optical fiber. In other embodiments of the present invention, the output of the optical transmit branch 212 only outputs a drive signal for driving a laser or modulator in a unidirectional transmission channel, such that the laser or modulator generates an optical signal based on the drive signal. And transmits the optical signal to the optical fiber.
The optical receiving branch 213 has an output terminal connected to the input/output port 211, and an input terminal connectable to a unidirectional transmission channel for receiving electrical or optical signals therefrom. The input end of the signal peak detection unit 214 is connected to the optical receiving branch 213, and when the input signal swing of the optical receiving branch 213 exceeds a certain threshold, the output of the signal peak detection unit 214 is in the first state, otherwise, the output is in the second state.
In a specific embodiment of the present invention, the first state may be a high level and the second state may be a low level. The output of the signal peak detection unit 214 is connected to a control logic unit 215. When the signal peak detection unit output is at a high level, the control logic unit 215 controls the optical transmitting branch 212 to make its output in a high impedance balanced state, i.e. the output of the optical transmitting branch 212 is not affected by its input, and its positive and negative terminals are equal. The control logic unit 215 controls the light receiving branch 213 to operate when the output of the signal peak detecting unit 214 is at a high level, i.e. the output is a response of the input. When the signal peak detection unit 214 output is at a low level, the optical transmitting branch 212 is active, i.e. the output is a response of the input, and the optical receiving branch 213 is inactive, i.e. the output is in a high impedance balanced state.
FIG. 2B illustrates the timing relationship of a plurality of nodes in the circuit shown in FIG. 2A.
Fig. 2C shows a state machine for an optical interconnect link comprised of two-sided duplex-simplex switching circuits.
Referring to fig. 2B to 2C, in the initial state, the transmitting branch is in the standby state, and the receiving branch is in the blocking and standby state, when the receiving branch detects a signal, the transmitting branch is blocked first, and then the receiving branch is opened, wherein the blocking of the transmitting branch must occur before the receiving branch is opened; when the receiving branch loses the signal, the initial state is returned, wherein the receiving branch enters the blocking state and the standby state is prior to the transmitting branch entering the standby state. When the transmitting branch detects a signal, the transmitting branch is opened, and the receiving branch is in a blocking and standby state; and when the transmitting branch loses the signal, returning to the initial state. And when the transmitting branch and the receiving branch lose signals at the same time, returning to the initial state.
In the above description, the state of the transmitting branch being on (on) implies: all circuit units are started, the signal detection circuit finds that an electric signal to be transmitted exists at the input/output port, and a laser driving circuit of the signal detection circuit is started;
wherein the state that the emission branch is opened (on) is connoted as: all circuit units are started, the signal detection circuit finds that the input/output port to-be-transmitted electric signal exists, and a drive circuit of the signal detection circuit is started;
the Standby (Standby) state of the transmitting branch circuit is defined as follows: the driving circuit is closed, and the signal detection circuit monitors whether the input/output port has an electric signal to be transmitted in real time;
the transmitting branch blocks (Block) state, the connotation is: the driving circuit is closed, and the first-stage circuit connected with the input/output port is disconnected, namely, the signal on the input/output port is not transmitted to the interior of the transmitting branch circuit, and the signal detection unit does not sense the existence of the signal on the input/output port;
the receiving branch circuit is in an open (on) state, and the connotation is as follows: all circuit units are opened, and the signal detection unit finds a signal to be detected and opens the output stage of the signal detection unit to be connected with the external input/output port;
the receiving branch is blocked and stands by (Block & Standby), and the connotation is as follows: the output stage is closed, i.e. disconnected from the external input/output port; the signal detection unit monitors whether a signal to be detected exists in real time;
note that: the commonality of the block state is that the circuit elements connected to the input/output ports are disconnected.
Specifically, in the initial state, the transmitting branches on the left and right sides are in the standby state, and the receiving branches are in the blocking and standby state. When the left transmitting branch detects a signal, the transmitting branch is started, and the receiving branch sleeps, so that the right receiving branch is triggered to detect the signal, the right transmitting branch is blocked first, and then the right receiving branch is started. When the left side transmitting branch signal is lost, the left side circuit returns to the initial state. When the right receiving branch loses the signal, the right circuit returns to the initial state. When the left receiving branch detects a signal, the left transmitting branch is blocked first, then the left receiving branch is opened, and when the left receiving branch loses the signal, the left circuit returns to the initial state.
When the receiving branch and the transmitting branch lose signals at the same time, the circuit returns to the initial state.
Fig. 3A shows a schematic diagram of a duplex-simplex switching circuit for optical interconnects, according to one embodiment of the invention. The duplex-simplex switching circuit shown in fig. 3A may be disposed either on the left or on the right. As shown in fig. 3A, the duplex-simplex switching circuit for optical interconnection includes: input/output port 301, optical transmitting branch, optical receiving branch, signal peak detecting unit 307 and control logic unit 306. The input-output port 301 may be connected to a copper cable for bi-directional signal communication with other devices, i.e., may send electrical signals to or receive electrical signals to be transmitted from other devices.
The input end of the optical transmitting branch is connected to the input/output port 301, and the output end thereof is connected to the optical fiber, and transmits an optical signal into the optical fiber according to an input electrical signal. In the particular embodiment shown in fig. 3A, the optical transmit branch may include an input buffer 302, a gain stage 303, a driver stage 304, and a laser 305. The anode of the laser 305 is connected to the non-inverting output + of the driver stage 304 and the non-inverting + and inverting inputs-of the driver stage 304 are connected to the inverting output-and non-inverting output of the gain stage 303, respectively. The inverting-and non-inverting-inputs of gain stage 303 are connected to the non-inverting + and inverting + outputs of input buffer 302, respectively. The inverting input terminal-and the non-inverting input terminal of the input buffer 302 are connected to the two signal lines of the input/output port 301, respectively. In other embodiments of the present invention, the optical transmitting branch may not include a laser, and only outputs the driving signal, as shown in fig. 3B. The drive signal may be used to drive an external device, such as a laser or modulator. The optical or electrical signal generated by the laser or modulator based on the drive signal may be connected to other optoelectronic devices, such as an optical fiber.
It will be understood by those skilled in the art that the configuration of the optical transmit branch described in the present invention is not limited to the circuit shown in fig. 3A, and in embodiments of the present invention, the optical transmit branch may have only one amplification stage, i.e., only include a driver stage. Alternatively, the light emitting branch may comprise two stages, i.e. an input buffer and a driving stage. Other optical transmission circuits may also be incorporated into aspects of the present invention in conjunction with the present disclosure.
The output end of the optical receiving branch is connected to two signal lines of the input/output port 301, and the input end thereof is connected to the optical fiber, and receives an optical signal from the optical fiber. In the particular embodiment shown in fig. 3A, the light receiving branch comprises a detector 310, a transimpedance amplifier 309 and an output buffer 308. After the detector 310 detects the optical signal, an electrical signal is generated, and the transimpedance amplifier 309 receives the electrical signal output by the detector 310 and outputs a differential signal at its inverting output terminal-and its non-inverting output terminal +. The signal peak detection unit 307 is connected to the inverting output-and the non-inverting output + of the transimpedance amplifier 309. The transimpedance amplifier (TIA)309 comprises a limiting amplifier, or may comprise only a TIA without a limiting amplification section. In other embodiments of the present invention, the input end of the light receiving branch may not include the detector 310, as shown in fig. 3B. That is, the input end of the light receiving branch receives a detection signal, which may be a signal processed by an external detection unit. For example, the input end of the light receiving branch is connected to an external photodiode.
The non-inverting input + and the inverting input-of the output buffer 308 are connected to the inverting output-and the non-inverting output + of the transimpedance amplifier 309, respectively. The non-inverting + and inverting-outputs of the output buffer 308 are connected to the two signal lines of the input/output port 301, respectively.
It should be understood by those skilled in the art that the structure of the light receiving branch described in the present invention is not limited to the circuit shown in fig. 3A. In embodiments of the present invention, other light receiving circuits may also be incorporated into aspects of the present invention.
The signal peak detection unit 307 detects an output differential signal of the transimpedance amplifier 309. When the swing of the differential signal exceeds a certain threshold, the output SD of the signal peak detection unit 307 is in the first state, otherwise, the output SD is in the second state. In a specific embodiment of the present invention, the first state may be a high level and the second state may be a low level. The output SD of the signal peak detection unit 307 is connected to the control logic unit 306.
In an embodiment of the present invention, the control logic unit 306 may be an SR flip-flop. The SR flip-flop may include an inverter 3061, a first nor gate 3062, and a second nor gate 3063. The input terminal of the inverter 3061 is connected to the SD terminal, and the output terminal of the inverter 3061 is an LOS terminal. The first nor gate 3062 has inputs connected to the SD terminal and an output of the second nor gate 3063, respectively, and an output connected to the light emitting branch, enabling control of the light emitting branch. The second nor gate 3063 has inputs connected to the LOS terminal and the output of the first nor gate 3062, respectively, and an output connected to the light receiving branch for enabling control of the light receiving branch.
In other embodiments of the present invention, the control logic unit 306 may also generate a control signal depending on the output terminal SD signal through a logic circuit with similar functions.
The core of the invention is a signal peak detection unit 307 placed between the optical transmitting branch and the optical receiving branch. The circuit is responsible for sensing the output of the transimpedance amplifier of the light receiving part, and if the output is in a static balanced state (the levels of the positive and negative output ends are the same), the SD of the signal detection circuit is 0, and the LOS end in the control logic unit 306 is 1. When the output of the transimpedance amplifier is valid data, SD of the signal detection circuit is 1, and LOS is 0.
FIG. 4 illustrates the timing relationships of a plurality of nodes in the circuit shown in FIG. 3A. After the transimpedance amplifier of the optical receiving branch receives the effective signal, SD is changed from 0 to 1, the SR flip-flop output SR-A is set to be 0 and SR-B is set to be 1, the control signal SR-A turns off the output of the input buffer or the gain stage of the optical transmitting branch (output balanced state), and the control signal SR-B turns on the output buffer of the optical receiving branch. In other words, at the beginning of the burst signal, the control logic unit controls the optical transmitting branch before the optical receiving branch in terms of timing. When at the end of the burst signal SD changes from 1 to 0 setting LOS to 1, SR-B to 0 and SR- A to 1, the control signal SR-B turns off the output buffer of the optical receiving branch and the control signal SR- A turns on the output of the input buffer or gain stage of the optical transmitting branch, i.e. the control logic unit controls the optical receiving branch chronologically before the optical transmitting branch. Since for half-duplex applications, there will be only one direction of signal at a time, only one side of the signal detection circuit will detect valid signals on the left or right side of the fiber, so as to establish a complete transmission channel in the corresponding transmission direction.
For example, the signal detection circuit on the B-side detects a valid signal, and transmission from the left side to the right side is established by turning off the right-side light-emitting channel circuit and turning on the output buffer of the own light-receiving channel. Conversely, if the left signal detection circuit detects a valid signal, transmission from the right side to the left side is established.
In the circuit configuration described in the present invention, in the initial state, only the transimpedance amplifier portions of the light emitting portion and the light receiving portion on the left and right sides operate, and the output buffers of the light receiving portions on both sides do not operate (or are referred to as being turned off). The non-operation means that the output of the circuit is in a high-impedance balanced state, that is, the positive and negative ports are equal in level and the differential pair pull-down current source is 0.
FIG. 5 shows a schematic block diagram of a signal detection circuit according to one embodiment of the present invention. As shown in fig. 5, the signal detection circuit includes a differential peak detection circuit 510, a common mode extraction circuit 520, a common mode level boosting circuit 530, and a comparator 540. The differential peak detection 510 is connected to the non-inverting + and inverting outputs of the transimpedance amplifier, and receives the detected differential signals VI _ P and VI _ N, thereby extracting the highest level of the input differential signal. The common mode extraction circuit 520 is connected to the non-inverting output terminal + and the inverting output terminal-of the transimpedance amplifier, and receives the detected differential signals VI _ P and VI _ N, thereby extracting the common mode level of the input differential signal. The common mode level boosting circuit 530 adds a difference value based on the extracted common mode level. The comparator 540 compares the output of the common mode extraction level boosting circuit with the output of the differential peak detection, and when the swing of the input differential signal exceeds the boosting difference, the output result of the comparator is high level (or low level).
FIG. 6 shows a schematic diagram of a signal detection circuit according to one embodiment of the invention. As shown in fig. 6, VI _ P and VI _ N are detected differential signals, which are sent to two bases of a differential follower formed by transistors 607 and 608, forming a peak detection circuit. The emitters of transistors 607 and 608 are connected together and output a peak voltage VOP at the connection node. The emitters of the transistors 607 and 608 are also connected to the drain of a transistor 615 of the current source bias circuit. The current source bias circuit comprises transistors 612, 613, 614 and 615, which have their gates connected to the input current Iin and their sources connected to a current source. The width to length ratio of transistor 615 is twice that of transistor 614.
The common mode extraction circuit, which is composed of resistors 601 and 602 and capacitor 603, obtains the common mode level of the detected differential signal. One end of each of the resistors 601 and 602 is connected to the differential signals VI _ P and VI _ N to be detected, the other end of each of the resistors 601 and 602 is connected to one end of the capacitor 603, and the other end of the capacitor 603 is connected to a current source. The other end of the resistors 601, 602 outputs a common mode level to the input of a differential amplifier formed by transistors 610 and 611. The gate of the transistor 610 is connected to the other end of the resistors 601, 602. A drain of transistor 610 is connected to the drain of transistor 604. Transistors 604 and 605 form a current mirror. The drains of the transistors 610, 611 are connected to the drain of the transistor 613 of the current source biasing circuit. The drain and gate of the transistor 611 are connected to one terminal of the resistor 609. The other terminal of the resistor 609 is connected to the drain of the transistor 605. The other end of resistor 609 is connected as an output terminal to the base of transistor 606. The collectors of transistors 606,607, 608 are interconnected and connected to the sources of transistors 604 and 605, while being connected to a power supply VCC. The emitter areas of the transistors 606, 607, 608 are the same. The emitter of transistor 606 outputs a common mode level VON as an output. The comparator receives the common mode level VON and the peak level VOP for comparison.
The output of resistor 609 is fed back to the negative terminal of the differential amplifier to form a 1:1 follower. The output of resistor 609 is fed to the follower of transistor 606, the output of which is compared to the peak detection followed by the difference described previously. The output of resistor 609 is higher than the input common mode level by an offset amount, which is determined by the resistor and the magnitude of the differential pair pull-down current source. Therefore, the comparator will output a high level, indicating that a valid signal is coming, only if the output VOP of the peak detection is higher than the common mode level VON by an amount larger than the offset.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (14)
1. A control-free half-duplex-simplex switching circuit, comprising:
an input-output port;
the input end of the transmitting branch is connected with the input/output port, and the transmitting branch outputs a driving signal according to an input electric signal;
the input end of the receiving branch circuit receives the detection signal, the output end of the receiving branch circuit is connected with the input/output port, and the receiving branch circuit transmits an electric signal to the input/output port according to the received detection signal;
the signal peak detection unit senses whether the receiving branch circuit receives an effective signal or not and outputs a control signal at an output end, when the amplitude of oscillation of an input signal of the receiving branch circuit exceeds a threshold value, the output of the signal peak detection unit is in a first state, and otherwise, the output of the signal peak detection unit is in a second state; and
and the control logic unit is connected with the output end of the signal peak value detection unit, blocks the transmitting branch and starts the receiving branch when the control signal is in a first state, wherein the blocking of the transmitting branch must occur before the receiving branch is started, and starts the transmitting branch and blocks the receiving branch when the control signal is in a second state.
2. The control-free half-duplex-simplex switching circuit according to claim 1, wherein the receiving branch comprises a detector, a transimpedance amplifier and an output buffer, the detector generates an electrical signal after detecting the optical signal, the transimpedance amplifier receives the electrical signal output by the detector and outputs a differential signal at its inverting output terminal and its non-inverting output terminal, the non-inverting input terminal and the inverting input terminal of the output buffer are respectively connected to the inverting output terminal and the non-inverting output terminal of the transimpedance amplifier, and the non-inverting output terminal and the inverting output terminal of the output buffer are respectively connected to the input/output port.
3. The control-less half duplex-simplex conversion circuit of claim 2, wherein the transimpedance amplifier comprises a limiting amplifier.
4. The control-free half duplex-simplex switching circuit of claim 2, wherein in an initial state, only the transimpedance amplifier portions of the transmit and receive branches are active and the output buffer is inactive.
5. The control-free half-duplex-to-simplex conversion circuit of claim 2, wherein an input of the signal peak detection unit is connected to the inverting output and the non-inverting output of the transimpedance amplifier.
6. The control-free half-duplex-to-simplex conversion circuit of claim 5, wherein the signal detection circuit comprises: the differential peak detection circuit is connected to the in-phase output end and the anti-phase output end of the transimpedance amplifier and used for receiving a detected differential signal so as to extract the highest level of an input differential signal; the common mode extraction circuit is connected to the in-phase output end and the reverse-phase output end of the trans-impedance amplifier and used for receiving the detected differential signal so as to extract the common mode level of the input differential signal; the common mode level lifting circuit increases a difference value on the basis of the extracted common mode level; the comparator compares the output of the common mode extraction level lifting circuit with the output of the differential peak value detection circuit, and when the swing amplitude of the input differential signal exceeds a lifting difference value, the output result of the comparator is in a first state.
7. The control-free half duplex-simplex switching circuit according to claim 6, wherein the differential peak detection circuit is a differential follower consisting of two transistors, the common mode extraction circuit comprises a first resistor and a second resistor connected in parallel, one end of the first resistor and one end of the second resistor are respectively connected to the detected differential signal, and the other end of the first resistor and the other end of the second resistor are connected to output the common mode level.
8. The control-less half duplex-to-simplex transition circuit of claim 1, wherein the first state is high and the second state is low.
9. The control-less half duplex-to-simplex conversion circuit of claim 1, wherein the control logic unit is an SR flip-flop.
10. The control-less half duplex-to-simplex conversion circuit of claim 1, wherein the drive signal output by the transmit branch is used to drive a laser or a modulator.
11. A method of controlling a control-free half-duplex-to-simplex conversion circuit as claimed in any one of claims 1 to 10, comprising:
in the initial state, the transmitting branch is in the standby state, the receiving branch is in the blocking and standby state,
when the receiving branch detects a signal, blocking the transmitting branch and then starting the receiving branch, wherein the blocking of the transmitting branch must occur before the starting of the receiving branch;
when the receiving branch loses the signal, the initial state is returned, wherein the receiving branch enters the blocking state and the standby state is prior to the transmitting branch entering the standby state.
12. The control method of claim 11, wherein when the transmitting branch detects a signal, the transmitting branch is turned on, the receiving branch is turned off and stands by; and when the transmitting branch loses the signal, returning to the initial state.
13. The control method of claim 12, wherein the initial state is returned when the transmitting branch and the receiving branch lose signals at the same time.
14. An optical interconnect link for a half-duplex-to-simplex conversion circuit, comprising:
a left half duplex-simplex switching circuit;
a half duplex-simplex switching circuit on the right side,
wherein left side and right side half duplex-simplex converting circuit all include: an input-output port; the input end of the transmitting branch is connected with the input/output port, and the transmitting branch outputs a driving signal according to an input electric signal; the input end of the receiving branch circuit receives the detection signal, the output end of the receiving branch circuit is connected with the input/output port, and the receiving branch circuit transmits an electric signal to the input/output port according to the received detection signal; the signal peak detection unit senses whether the receiving branch circuit receives an effective signal or not and outputs a control signal at an output end, when the amplitude of oscillation of an input signal of the receiving branch circuit exceeds a threshold value, the output of the signal peak detection unit is in a first state, and otherwise, the output of the signal peak detection unit is in a second state; and a control logic unit, the control logic unit is connected with the output end of the signal peak value detection unit, when the control signal is in a first state, the control logic unit blocks the transmitting branch and starts the receiving branch, wherein the blocking of the transmitting branch must occur before the starting of the receiving branch, when the control signal is in a second state, the control logic unit starts the transmitting branch and blocks the receiving branch,
wherein the left transmitting branch is connected to the right receiving branch through a first unidirectional transmission channel, the left receiving branch is connected to the right receiving branch through a second unidirectional transmission channel,
wherein the opening of the left or right transmitting branch triggers a condition for the opposite receiving branch to detect a signal.
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| CN1716827A (en) * | 2004-06-28 | 2006-01-04 | Jds尤尼弗思公司 | Flexible control and status architecture for optical modules |
| CN209283248U (en) * | 2018-11-29 | 2019-08-20 | 深圳市易飞扬通信技术有限公司 | 100Gbps optical module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716827A (en) * | 2004-06-28 | 2006-01-04 | Jds尤尼弗思公司 | Flexible control and status architecture for optical modules |
| CN209283248U (en) * | 2018-11-29 | 2019-08-20 | 深圳市易飞扬通信技术有限公司 | 100Gbps optical module |
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