CN112749119A

CN112749119A - IP core for realizing ASI interface function based on FPGA resource

Info

Publication number: CN112749119A
Application number: CN202011602030.1A
Authority: CN
Inventors: 应雯漪; 谢达; 谢文虎; 季振凯; 章敏; 董宜平
Original assignee: CETC 58 Research Institute; Wuxi Zhongwei Yixin Co Ltd
Current assignee: CETC 58 Research Institute; Wuxi Zhongwei Yixin Co Ltd
Priority date: 2020-12-29
Filing date: 2020-12-29
Publication date: 2021-05-04
Anticipated expiration: 2040-12-29
Also published as: CN112749119B

Abstract

The invention discloses an IP core for realizing an ASI interface function based on FPGA resources, which relates to the technical field of FPGA and comprises a sending module and a receiving module, wherein the sending module processes user parallel data into a data format conforming to an ASI standard through a data packing unit, a coding unit and a serialization processing unit, the receiving module processes the data received by the ASI interface into the parallel data convenient for the user to use by utilizing an oversampling deserializing unit, a data extracting unit, a word aligning unit, a decoding unit and a synchronizing unit, the IP core uses a small amount of FPGA internal resources when realizing a transceiving function, other functions are realized by soft logic, the IP core does not depend on off-chip hardware resources, can reduce the system cost and power consumption, is packaged into an IP core form convenient to use, and has portability, reusability and convenience for updating and upgrading.

Description

IP core for realizing ASI interface function based on FPGA resource

Technical Field

The invention relates to the technical field of FPGA (field programmable gate array), in particular to an IP (Internet protocol) core for realizing an ASI (application specific interface) function based on FPGA (field programmable gate array) resources.

Background

At present, an asynchronous serial interface (ASI interface) and a synchronous parallel interface (SPI interface) are two general MPEG-2 video transmission modes, 11 useful signals are totally used in the SPI interface, and each signal is transmitted in a differential mode to improve the anti-interference performance of transmission, so that the connection is multiple and complex, the transmission distance is short, and faults are easy to occur. The ASI interface has a constant transmission rate, has few connection lines, and facilitates long-distance transmission, so in the DVB system, the ASI interface is widely used in point-to-point transmission due to its characteristics of high speed, reliability, accuracy, and the like.

Currently, a special ASI chip is generally used to implement an ASI interface, for example, an ASI sending-end chip CY7B923 and an ASI receiving-end chip CY7B933 of CYPRESS are generally used at present, but the adoption of the special ASI chip may increase power consumption and cost of the entire system. Another way is to use a programmable logic device such as a CPLD or an FPGA to implement an ASI interface, but in the prior art, the ASI interface is implemented based on an ASI core of an IP library of a programmable logic device, so that only a programmable logic device (for example, FPGA of ALTERA corporation) providing an IP core corresponding to a function can implement the ASI interface at present, and a programmable logic device (for example, FPGA of Xilinx corporation) not providing an IP core corresponding to a function cannot implement the ASI interface, and the ASI interface is limited by the device itself and is not high in portability.

Disclosure of Invention

The invention provides an IP core for realizing an ASI interface function based on FPGA resources aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

an IP core for realizing an ASI interface function based on FPGA resources is characterized in that the FPGA resources comprise clock resources, IO resources and FIFO, and the IO resources at least comprise OBUFDS and IBUFDS; the IP core comprises: the device comprises a sending module and a receiving module, wherein the sending module is used for realizing an ASI interface data sending function, and the receiving module is used for realizing an ASI interface data receiving function;

the transmitting module comprises a data packing unit, a coding unit and a serialization processing unit, wherein the data packing unit generates data to be transmitted according to the data in the FIFO and transmits the data to the coding unit; the coding unit codes data to be transmitted according to a preset lookup table and transmits the coded data to be transmitted to the serialization processing unit; the serialization processing unit converts the coded data to be sent in a parallel data form into serial data conforming to the ASI transmission rate, and sends the serial data into the OBUFDS to be output in a differential form;

the receiving module comprises an oversampling deserializing unit, a data extracting unit, a word aligning unit, a decoding unit and a synchronizing unit, wherein the oversampling deserializing unit oversamples and deserializes a serial input code stream received by the IBUFDS based on a clock signal generated by a clock resource to obtain a parallel data stream and stores the parallel data stream into the FIFO; the data extraction unit extracts data points from the parallel data stream to obtain a parallel stable data stream corresponding to the ASI transmission rate and stores the parallel stable data stream into the FIFO; the word alignment unit synchronously completes word alignment processing on the bit sequence of the parallel stable data stream; the decoding unit decodes the parallel stable data stream which completes the word alignment processing according to a preset lookup table; and the synchronization unit performs synchronization processing on the decoded parallel stable data stream, extracts a data packet and writes the data packet into FIFO for a user to read.

The beneficial technical effects of the invention are as follows:

the application discloses IP core for realizing ASI interface function based on FPGA resource, the IP core uses a small amount of FPGA internal resource when realizing the receiving and transmitting function of the ASI interface, other functions are realized by soft logic, the IP core does not depend on off-chip hardware resource and is packaged into an IP core form convenient to use, and the IP core has portability and reusability, so that the FPGA without an official ASI core, which is injected into Xilinx Virtex4 series FPGA, can also realize the receiving and transmitting of the ASI interface.

Drawings

FIG. 1 is a logical block diagram of an IP core as disclosed herein.

Fig. 2 is a schematic diagram of an execution flow of the data packing unit in the present application.

FIG. 3 is a diagram of an oversampling decoding unit in the present application for a serial input code stream

Fig. 4 is an implementation logic structure of the oversampling decoding unit in the present application to implement the oversampling function.

Fig. 5 is a schematic diagram of data extraction by the data extraction unit in the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses IP core for realizing ASI interface function based on FPGA resource, the IP core comprises a sending module for realizing ASI interface data sending function, a receiving module for realizing ASI interface data receiving function, user data interfaces of the sending module and the receiving module, and a data interface form compatible with FIFO read-write interface in FPGA. The IP core is used for processing the parallel data format into a data format conforming to an ASI standard, the receiving module is used for processing the data format of the ASI standard into the parallel data format convenient for a user to use, the IP core uses a small amount of FPGA internal resources when realizing the receiving and sending functions of an ASI interface, other functions are realized by soft logic, do not depend on off-chip hardware resources, and are packaged into an IP core form convenient to use, and the IP core has portability and reusability, and is particularly suitable for an Xilinx FPGA which is a common FPGA but does not provide the ASI core by an official party, such as an Xilinx Virtex4 series FPGA. The FPGA internal resources used by the IP core mainly comprise clock resources, IO resources, FIFO and BRAM, wherein the IO resources mainly comprise OBUFDS and IBUFDS.

First, send the module.

Referring to fig. 1, the sending module of the IP core includes a data packing unit, an encoding unit, and a serialization processing unit, wherein the data packing unit generates data to be sent according to data in the FIFO and sends the data to the encoding unit. And the coding unit codes the data to be transmitted according to a preset lookup table and transmits the coded data to be transmitted to the serialization processing unit. The serialization processing unit converts the coded data to be transmitted in a parallel data form into serial data conforming to the ASI transmission rate, the serial data is sent to the OBUFDS to be output in a differential form, and finally the serial data conforming to the DVB-ASI EN50083-9 standard is output to an interface. Specifically, the method comprises the following steps:

(1) the data packing unit mainly includes a data packet splicing state machine, the parallel data written by the user is stored in the FIFO, the execution flow of the data packet splicing state machine is shown in fig. 2, the data packet splicing state machine detects whether the data in the FIFO has a first character when detecting that the FIFO is not empty, the first character is a preset character, and the first character is HEX47 in this application. When the first packet character is detected, the packet splicing state machine detects whether the data in the FIFO reaches a predetermined data volume, wherein the predetermined data volume is the data volume contained in a preset data packet. In this application, the user interface of the sending module includes, in addition to the user data interface for acquiring parallel data, an interface for acquiring a packet length control signal, and the user provides the packet length control signal to indicate the packet length, i.e. the data size, of a single packet, and the common packet length is 188Byte or 204 Byte. And if the data packet splicing state machine determines that the first packet character exists in the FIFO and the data reaches the preset data volume, the data packet splicing state machine reads the data in the FIFO and packs the data to form a data packet, and the data packet is sent to the encoding unit. If the first character packet exists in the FIFO and the data does not reach the preset data volume, or the first character packet is not detected, the data packaging unit generates an idle code and sends the idle code to the encoding unit, and the first character packet and the data volume are circularly detected again. The idle code in this application is a Comma character, i.e., HEXbc. In the state of reading data, the packet splicing state will transfer the first character of the packet and other data carried by the packet to the following function, and in other states, will transfer the Comma character backward, so that the backward transferred packet is separated from the data packet by the Comma character, and all the backward transferred Comma characters will be identified by character signals.

(2) The encoding unit of the present application encodes the received data packet or idle code with 8B10B encoding program, 8B10B encoding, mainly in the form of a predetermined lookup table, and the encoding format conforms to the definition of the DVB-ASI EN50083-9 standard.

(3) The coded data to be sent is parallel data with a bit width of 10 bits under a clock with the frequency of 27MHz, and the data to be sent is sent into a serialization processing unit, the serialization processing unit converts the serial data which accords with the ASI transmission rate, and the standard ASI transmission rate is 270Mbps, so that the serialization processing unit converts the coded data to be sent into serial data with a bit width of 1bit under a clock with the frequency of 270MHz, and the serial data is sent into the OBUFDS to be output in a differential mode.

And II, a receiving module.

Referring to fig. 1, the receiving module includes an oversampling deserializing unit, a data extracting unit, a word aligning unit, a decoding unit, and a synchronizing unit, where the oversampling deserializing unit oversamples and deserializes a serial input code stream received through the IBUFDS based on a clock signal generated by a clock resource to obtain a parallel data stream, and stores the parallel data stream in the FIFO; the data extraction unit extracts data points from the parallel data stream to obtain a parallel stable data stream corresponding to the ASI transmission rate and stores the parallel stable data stream into the FIFO; the word alignment unit synchronously completes word alignment processing on the bit sequence of the parallel stable data stream; the decoding unit decodes the parallel stable data stream which completes the word alignment processing according to a preset lookup table; and the synchronization unit performs synchronization processing on the decoded parallel stable data stream, extracts a data packet and writes the data packet into FIFO for a user to read. Specifically, the method comprises the following steps:

(1) in order to obtain stable and effective data from an asynchronous serial data line, the application performs oversampling on a serial input code stream, the ASI transmission rate is 270Mbps, therefore, the serial input code stream received through the IBUFDS is transmitted at a fixed rate of 270Mbps, so the IP core five times samples the serial input code stream using the oversampling deserializing unit, but FPGAs do not support five times sampling of asynchronous data directly using a 1350MHz clock, therefore, in the present application, the oversampling deserializing unit respectively uses four clock signals with 337.5MHz frequency and different phases, which are different in phase, same in frequency, and same in phase, generated by a clock resource (DCM) as the trigger clocks of the four first-stage triggers DFF1 to sample the serial input code stream, so as to obtain an effect of obtaining a plurality of sampling points in one clock cycle, and the result is equivalent to oversampling the serial input code stream by using a high-frequency clock. The phases of the four clock signals are respectively 0 °, 90 °, 180 °, and 270 °, an oversampling schematic diagram of the serial input code stream is shown in fig. 3, and a functional implementation logic structure is shown in fig. 4, and the four clock signals are respectively input into the four first-stage flip-flops DFF1_1 to DFF1_ 4. And then splicing the sampled data under the four clock signals to obtain data for performing five-time oversampling on the serial input code stream. Because the subsequent data extraction unit extracts data points by using a clock signal with the frequency of 67.5MHz and the data points are not in the same clock domain with the over-sampled data, the over-sampled deserializing unit also splices the data obtained by over-sampling into parallel data with the bit width of 20 bits in sequence to obtain parallel data flow and stores the parallel data flow into the FIFO. Optionally, as shown in fig. 4, after the data obtained by sampling the serial input code stream by each first-stage flip-flop DFF1 sequentially passes through the second-stage flip-flop DFF2 and the third-stage flip-flop DFF3, the sampled data under the corresponding clock signal is obtained, and all the second-stage flip-flops DFF2 and the third-stage flip-flops DFF3 use clock signals with 337.5MHz frequency and 0 phase. Taking a sampling path where a clock signal with a phase of 0 ° is located as an example, a Q end of the first-stage flip-flop DFF1_1 is connected to a D end of the corresponding second-stage flip-flop DFF2_1, a Q end of the second-stage flip-flop DFF2_1 is connected to a D end of the corresponding third-stage flip-flop DFF3_1, a Q end of the third-stage flip-flop DFF3_1 outputs sampling data of the clock signal with the phase of 0 °, other paths are connected in the same way, and the second-stage flip-flop DFF2 and the third-stage flip-flop DFF3 are used for eliminating indeterminate states of data in the circuit and eliminating jitter, and data obtained by sampling four phases are unified in the same clock domain.

(2) After oversampling deserializing to obtain a parallel data stream, the data extraction unit extracts data points from the parallel data stream to obtain a parallel stable data stream corresponding to the ASI transmission rate, specifically: the data extraction unit determines a corresponding data window according to the data value of each bit in each group of data in the parallel data stream, the data window corresponding to each group of data takes the position of different data values of two adjacent bits in the group of data as a window boundary, and the data value of each bit is 0 or 1, so the window boundary of the data window is actually determined by judging the position of the change edge of 0 and 1 in the group of data. The sampling position of the first group of data is the middle position of the data window corresponding to the first group of data.

Starting with the second set of data, the sampling position of each set of data is obtained according to the sampling position of the set of data above it: (a) if the data window corresponding to the current group of data deviates to the high bit direction relative to the data window corresponding to the previous group of data, the sampling position of the previous group of data deviates to the high bit direction by one bit to obtain the sampling position of the current group of data. (b) If the data window corresponding to the current group of data is shifted to a low bit direction relative to the data window corresponding to the previous group of data, shifting the sampling position of the previous group of data to the low bit direction by one bit to obtain the sampling position of the current group of data. (c) And if the data window corresponding to the current group of data is not offset relative to the data window corresponding to the previous group of data, directly taking the sampling position of the previous group of data as the sampling position of the current group of data. Data values of the current set of data at the sampling location are extracted.

As shown in the example of FIG. 5, the data values of bit1 and bit2 in the first set of data are different, and the position is taken as one window boundary of the data window, and the data values of bit6 and bit7 are different, and the position is taken as the other window boundary of the data window, so that the range of the data window can be determined to be bit 2-6, and the sampling position is determined to be the position of bit 4. For the second group of data, the same method is adopted to determine that the range of the data window is the range from bit4 to bit8, at this time, if the sampling position is still kept at the bit4 position, the data window is obviously not suitable, because the data window is shifted to the left relative to the data window of the first group of data, namely to the direction of high bit, at this time, the sampling position of the first group of data is also shifted to the direction of bit by one bit, and the sampling position of the second data is determined to be the position of bit 5.

In addition, the data extraction unit detects whether the sampling position of the current group of data is included in the range of the data window corresponding to the current group of data after obtaining the sampling position of the current group of data according to the sampling position of the previous group of data, and if the sampling positions of the continuous K groups of data are detected to be beyond the range of the corresponding data window, the data extraction unit determines that the sampling positions do not correspond to the ASI transmission rate and increases or decreases the data value of one bit position for the data window corresponding to the current group of data, wherein K is a preset threshold value. The operation logic of increasing or decreasing the data value of one bit to the data window corresponding to the current group of data is as follows:

if the sampling position of the current set of data is higher than the highest bit of the data window corresponding to the current set of data, that is, in the example structure shown in fig. 5, the sampling position is located at the left side of the left window boundary of the data window, it is determined that the sampling position is slower than the ASI transmission rate, and the data value of the lowest bit in the data window corresponding to the current set of data is discarded, for example, the discarding bit4 for the second set of data in fig. 5.

If the sampling position of the current group of data is lower than the lowest bit of the data window corresponding to the current group of data, that is, in the example structure shown in fig. 5, the sampling position is located at the left side of the right window boundary of the data window, and it is determined that the sampling position is faster than the ASI transmission rate, the data value is increased at a bit higher than the highest bit of the data window corresponding to the current group of data, for example, a bit1 is increased between the existing bits 8 and bit9 for the second group of data in fig. 5.

The extracted parallel stable data stream is stored in FIFO for subsequent synchronization of clock domains where the logic such as word alignment, decoding and synchronization is located.

(3) The data transmitted by the ASI standard transmits idle codes, i.e., Comma characters, which fixedly use K28.5 characters in idle, and are mainly used for synchronization, so that the word alignment unit compares and adjusts the extracted parallel stable data stream with the Comma characters, searches for a relative displacement relationship, correspondingly shifts the bit sequence of the extracted parallel stable data stream until the extracted parallel stable data stream is completely aligned with the Comma characters, and completes word alignment processing.

(4) The decoding unit of the present application employs an 8B10B decoding procedure, which decodes data in the form of a predetermined look-up table similar to the encoding unit in the transmitting module. Optionally, when the decoding unit in the present application decodes the parallel stable data stream that has been word aligned, the decoding unit labels errors in the aligned parallel stable data stream to obtain error flag bits, where the error flag bits include error flag bits obtained by labeling coding errors and/or polarity errors in the parallel stable data stream, and the error flag bits are also sent to a subsequent synchronization unit for use in a back-end synchronization function.

(5) The synchronization unit in the application comprises a state machine synchronization unit and a packet synchronization unit, wherein a parallel stable data stream obtained by decoding by a decoding unit is sent to the state machine synchronization unit, when the state machine synchronization unit detects continuous M idle codes, the decoded parallel stable data stream is determined to be in a synchronization state, the decoded parallel stable data stream in the synchronization state is transmitted to the packet synchronization unit for packet synchronization processing, M is a preset threshold value, and M is usually equal to 2 in the application, so that the parallel stable data stream is determined to be in the synchronization state when a 2Byte error-free Comma character is continuously detected. Meanwhile, the error flag bit generated by the decoding unit is also sent to the state machine synchronization unit, after the state machine synchronization unit determines that the decoded parallel stable data stream is in a synchronization state, if the error flag bit of continuous N bits is monitored, it is determined that the decoded parallel stable data stream loses the synchronization state, and data transmission to the packet synchronization unit is stopped, and the state machine synchronization unit needs to perform synchronization judgment again, that is, determines synchronization again by detecting whether there are continuous M idle codes. N is a preset threshold, and N is 4 in this application, so that when 4 error flag codes are detected to continuously appear, it is determined that synchronization is lost, and it is necessary to find out a error-free Comma character of 2Byte again for resynchronization.

The packet synchronization unit detects the first character of the packet from the decoded parallel stable data stream in the synchronization state and extracts a data packet with a preset length and writes the data packet into the FIFO for reading by a user, wherein the data packet comprises the first character of the packet and other carried parallel data which are convenient for the user to use. Likewise, the first character is a predetermined character, and in this application the first character is HEX 47. After detecting the first character of the packet, the packet synchronization unit stores the decoded parallel stable data stream in the synchronization state and counts the data, as mentioned above, the common packet length is 188Byte or 204Byte, so the packet synchronization unit first compares the count result with 188Byte, when the count reaches 188Byte, if two successive Comma characters are obtained, the length of the current packet is determined to be 188Byte, if two successive Comma characters are not obtained, the count is stored and compared with 204Byte, when the count reaches 204Byte, if two successive Comma characters are obtained, the length of the current packet is determined to be 204Byte, if no successive Comma character is found, the format of the packet is determined to be wrong, and a packet structure error flag bit is generated. In this application, the user interface of the receiving module comprises, in addition to the user data interface for outputting parallel data, data for outputting error flags, which comprise error flags generated by the decoding unit for indicating coding errors and/or polarity errors, and/or packet structure error flags generated by the packet synchronization unit, which are stored in the FIFO.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims

1. An IP core for realizing an ASI interface function based on FPGA resources is characterized in that the FPGA resources comprise clock resources, IO resources and FIFO, and the IO resources at least comprise OBUFDS and IBUFDS; the IP core comprises: the device comprises a sending module and a receiving module, wherein the sending module is used for realizing an ASI interface data sending function, and the receiving module is used for realizing an ASI interface data receiving function;

the transmitting module comprises a data packing unit, a coding unit and a serialization processing unit, wherein the data packing unit generates data to be transmitted according to the data in the FIFO and transmits the data to the coding unit; the coding unit codes the data to be sent according to a preset lookup table and transmits the coded data to be sent to the serialization processing unit; the serialization processing unit converts the coded data to be transmitted in a parallel data form into serial data conforming to the ASI transmission rate, and sends the serial data into the OBUFDS to be output in a differential form;

the receiving module comprises an oversampling deserializing unit, a data extracting unit, a word aligning unit, a decoding unit and a synchronizing unit, wherein the oversampling deserializing unit oversamples and deserializes a serial input code stream received by the IBUFDS based on a clock signal generated by a clock resource to obtain a parallel data stream and stores the parallel data stream into the FIFO; the data extraction unit extracts data points from the parallel data stream to obtain a parallel stable data stream corresponding to the ASI transmission rate and stores the parallel stable data stream into the FIFO; the word alignment unit synchronizes the bit sequence of the parallel stable data stream to complete word alignment processing; the decoding unit decodes the parallel stable data stream which completes the word alignment processing according to the preset lookup table; and the synchronization unit performs synchronization processing on the decoded parallel stable data stream, extracts a data packet and writes the data packet into FIFO for a user to read.

2. The IP core of claim 1, wherein the data packing unit generates data to be transmitted according to the data in the FIFO and transmits the data to the encoding unit, and the data packing unit comprises:

the data packing unit detects whether the data in the FIFO has a first packing character when detecting that the FIFO is not empty;

when detecting that the first packet character exists, detecting whether the data in the FIFO reaches a preset data volume;

if the first packet character exists in the FIFO and the data reaches the preset data volume, the data packaging unit reads the data in the FIFO and packages the data to form a data packet and sends the data packet to the encoding unit;

and if the first packet character exists in the FIFO and the data does not reach the preset data volume, or the first packet character is not detected, the data packaging unit generates an idle code and sends the idle code to the encoding unit.

3. The IP core according to claim 1, wherein the ASI transmission rate is 270Mbps, the oversampling deserializing unit samples the serial input code stream by using four clock signals with 337.5MHz frequency and different phases generated by a clock resource as trigger clocks of four first-stage flip-flops, splices sampled data under the four clock signals to obtain data for performing quintuple oversampling on the serial input code stream, splices the data obtained by oversampling into parallel data with a bit width of 20 bits in order to obtain parallel data stream, and stores the parallel data stream in the FIFO.

4. The IP core according to claim 3, wherein each first stage trigger samples the serial input code stream and the data sequentially passes through a second stage trigger and a third stage trigger to obtain the sampled data under a corresponding clock signal, and all the second stage trigger and the third stage trigger use a clock signal with 337.5MHz frequency and 0 phase.

5. The IP core of claim 3, wherein the data extraction unit extracts data points with a clock signal having a frequency of 67.5MHz, and the data extraction unit determines a corresponding data window according to data values of bits in each group of data in the parallel data stream, and the data window corresponding to each group of data has a window boundary at a position where the data values of two adjacent bits in the group of data are different; if the data window corresponding to the current group of data deviates to the high bit position direction relative to the data window corresponding to the previous group of data, the sampling position of the previous group of data deviates to the high bit position direction by one bit to obtain the sampling position of the current group of data; if the data window corresponding to the current group of data deviates to the low bit direction relative to the data window corresponding to the previous group of data, the sampling position of the previous group of data deviates to the low bit direction by one bit to obtain the sampling position of the current group of data; extracting data values of the current set of data at the sampling position; the sampling position of the first group of data is the middle position of the data window corresponding to the first group of data.

6. The IP core of claim 5, wherein the data extraction unit detects whether the sampling position of the current set of data is included in a range of a data window corresponding to the current set of data after obtaining the sampling position of the current set of data according to the sampling position of the previous set of data, and determines that the sampling position does not correspond to the ASI transmission rate and adds or subtracts a data value of one bit to the data window corresponding to the current set of data if the sampling position of the consecutive K sets of data is detected to be out of the range of the corresponding data window.

7. The IP core of claim 6, wherein determining that a sampling location does not correspond to an ASI transfer rate and increasing or decreasing a data value of one bit for a data window corresponding to a current set of data comprises:

if the sampling position of the current group of data is higher than the highest bit of the data window corresponding to the current group of data, determining that the sampling position is slower than the ASI transmission rate, and discarding the data value of the lowest bit in the data window corresponding to the current group of data;

and if the sampling position of the current group of data is lower than the lowest bit of the data window corresponding to the current group of data, determining that the sampling position is faster than the ASI transmission rate, and increasing the data value at the high bit of the highest bit of the data window corresponding to the current group of data.

8. The IP core of claim 1, wherein the synchronization unit comprises a state machine synchronization unit and a packet synchronization unit, the state machine synchronization unit determines that the decoded parallel stable data stream is in a synchronization state when the state machine synchronization unit detects M consecutive idle codes, and the packet synchronization unit detects a first packet character from the decoded parallel stable data stream in the synchronization state and extracts a data packet having a predetermined length and writes the data packet into the FIFO for a user to read.

9. The IP core according to claim 8, wherein the decoding unit marks errors in the parallel stable data stream after word alignment processing to obtain an error flag bit and sends the error flag bit to the state machine synchronization unit when decoding the parallel stable data stream after word alignment processing; and after the state machine synchronization unit determines that the decoded parallel stable data stream is in a synchronization state, if the error flag bit of continuous N bits is monitored, the state machine synchronization unit determines that the decoded parallel stable data stream loses the synchronization state.

10. The IP core of claim 9, wherein the decoding unit stores the error flag bit in the FIFO, and wherein the packet synchronization unit generates the packet structure error flag bit and stores the packet structure error flag bit in the FIFO when detecting a packet format error when extracting the packet.