CN112737761B

CN112737761B - Apparatus and method for acknowledging communications via bus

Info

Publication number: CN112737761B
Application number: CN202011162158.0A
Authority: CN
Inventors: A·德阿梅尔
Original assignee: STMicroelectronics Grenoble 2 SAS
Current assignee: STMicroelectronics Grenoble 2 SAS
Priority date: 2019-10-28
Filing date: 2020-10-27
Publication date: 2024-01-12
Anticipated expiration: 2040-10-27
Also published as: CN112737761A; US11283550B2; EP3816808B1; US20210126740A1; FR3102584B1; FR3102584A1; EP3816808A1

Abstract

An embodiment method comprises: receiving at least one frame comprising successive bits transmitted over a serial bus; estimating an arrival period of a last bit of the consecutive bits; and starting transmission of the reception acknowledgement before the estimated arrival period ends.

Description

Apparatus and method for acknowledging communications via bus

Cross reference to related applications

The present application claims priority from french application No. 1912046 filed on 10, 28 in 2019, which is incorporated herein by reference.

Technical Field

The present invention relates generally to electronic devices and methods, and more particularly to devices and related methods intended to be coupled to a serial bus.

Background

Some applications, particularly in the automotive industry, include a number of devices, such as computing units, sensors, etc., that are coupled to each other via a serial bus, such as a Controller Area Network (CAN) bus. These devices communicate with each other via a CAN bus. Coupling via the CAN bus allows a reduction in the number of cables used compared to other communicative couplings.

Disclosure of Invention

In known systems comprising a conventional serial bus, such as a CAN bus, it is desirable to speed up its operation and/or to increase the length of the serial bus and/or to increase its operational reliability with respect to parasitics affecting the serial bus.

One embodiment addresses all or part of the disadvantages of known methods of communicating via a serial bus.

One embodiment addresses all or part of the disadvantages of known devices intended to be coupled to a serial bus.

One embodiment addresses all or part of the shortcomings of known systems including devices coupled to a serial bus.

One embodiment provides a method comprising the steps of: receiving at least one frame comprising successive bits transmitted over a serial bus; estimating an arrival period of a last bit of the consecutive bits; and starting transmission of the reception acknowledgement before the estimated arrival period ends.

According to one embodiment, consecutive bits have the same bit duration.

According to one embodiment, the estimated arrival period ends at a multiple of the bit duration after the edge is received.

According to one embodiment, the acknowledgement of receipt has a duration greater than or equal to the bit duration, preferably equal to the bit duration.

According to one embodiment, the method comprises the following steps; the transmission of the reception acknowledgement is ended before the end of the further cycle having a bit duration and starts at the end of the arrival cycle, the transmission of the reception acknowledgement preferably having a duration equal to the bit duration.

According to one embodiment, the sending of the reception acknowledgement is performed at least up to the sampling point of the reception acknowledgement.

According to one embodiment, the transmission of the reception acknowledgement is started at the end of a delay after the sampling point of the last bit of the consecutive bits.

According to one embodiment, the delay is less than three cycles of the clock, preferably less than a single cycle.

An embodiment provides an apparatus configured to implement the method defined above.

According to one embodiment, the apparatus is further configured to read the value of the last one of the consecutive bits at the sampling point of the last one of the consecutive bits.

According to one embodiment, the delay is programmable.

According to one embodiment, the apparatus includes a clock.

One embodiment provides a system comprising a serial bus (preferably of the CAN type) and one or more first devices coupled to the serial bus as defined above.

According to one embodiment, the delay is common to the first devices.

According to one embodiment, the system includes a second device coupled to the serial bus, the second device configured to transmit: a first message conveying a set of steps performed by a first device; and a second message addressed to a portion of the first device, the second message conveying a corresponding identifier of the first device to which the second message is addressed, the second message requesting the first device to which the second message is addressed to send a corresponding response to the second device at a corresponding expected time interval. The first apparatus is configured to: receiving a first message, reading a set of steps to be performed, and implementing the steps according to the read set; and receiving the second message and reacting to the second message by sending a reaction destined for the second device over the serial bus at corresponding expected time intervals.

Drawings

The above features and advantages and other features and advantages will be described in detail in the following description of specific embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which:

FIG. 1 shows in a schematic way a system comprising a serial bus and devices coupled to the bus, of a type suitable for the described embodiments; and

fig. 2 shows a timing diagram of one embodiment of a method for communicating in a system of the type shown in fig. 1.

Detailed Description

Like features have been designated by like reference numerals throughout the various figures. In particular, structural and/or functional features common in the various embodiments may have the same reference numerals and may have the same structural, dimensional, and material characteristics.

For clarity, only the operations and elements that are helpful in understanding the embodiments described herein have been illustrated and described in detail. In particular, the parts of the device circuitry intended to be coupled to the serial bus, in particular the transceiver unit, are not described and/or shown in detail. Indeed, embodiments may be compatible with conventional devices intended to be coupled to a serial bus, such compatibility being particularly potentially obtained by configuring such devices to implement the method embodiments described below in a manner that will be appreciated by those skilled in the art.

Unless otherwise indicated, when referring to two elements being connected together, this means that there is no direct connection of any intermediate element (other than a conductor), and when referring to two elements being coupled together, this means that the two elements may be connected or coupled by one or more other elements.

In the following disclosure, unless otherwise indicated, when referring to absolute positional definitions (such as the terms "front", "rear", "upper", "lower", "left", "right", etc.) or relative positional definitions (such as "above", "below", etc.) or directional definitions (such as "horizontal", "vertical", etc.), reference is made to the directions shown in the figures.

Unless otherwise specified, the expressions "left and right", "approximately", "substantially" and "in … scale" mean within 10%, preferably within 5%.

Fig. 1 shows in a schematic way a system 100 comprising a serial bus 110, a device 120 and a plurality of devices 130. The described embodiments are applicable to the same type of system as system 100. Two devices 130 are shown as examples, but the system 100 may include one or several devices 130.

The serial bus 110 is typically defined by two wires. Preferably, the bus 110 is of the CAN type, which is generally defined by standard ISO 11898. More preferably, the CAN bus is of the flexible data rate CAN (FD CAN) type.

Devices 120, 130 are coupled (preferably connected) to bus 110. During operation, devices 120 and 130 communicate data with each other via bus 110. To this end, the devices send and/or receive data transmitted by the bus 110. Preferably, each device transmits one or more frames for transmitting data. Successive bits set in a predetermined order are understood by the frame. Preferably, each frame includes at least one frame start bit and a plurality of frame end bits. The data (or information) bits transferred between devices are composed of specific bits of a frame. During the duration TBIT (not shown in FIG. 1), each bit corresponds to a logic level of the bus 110. Two potential levels (potential levels) of the bus 110 are understood by logic levels, preferably corresponding to corresponding recessive and dominant levels of the CAN bus 110. Preferably, the duration TBIT is common to the bits of the frame. The duration TBIT is generally comprised between about 0.1 and 2 μs, for example equal to 1 μs, which corresponds to a data rate lower than about 1Mbits/s, for example equal to 1Mbits/s.

Preferably, the communication method implemented by the system 100 is orchestrated by a device 120, referred to as a master device. Thus, the device 130 is referred to as a slave device. In particular, each slave device 130 transmits data on the bus 110 only after receiving other data transmitted by the master device 120 indicating that it may or must transmit data. Preferably, each slave device 130 transmits its data only in the time interval indicated by the master device 120. The master device 120 ensures that only one of the devices 120, 130 transmits data on the bus at a time. Thus, the transmission priority is exclusively managed by the master device 120.

Preferably, the apparatus 120, 130 implements the method described in italian patent application No. 102018000003980 (17-GRA-0844) filed on day 26, 3, 2018, which is incorporated herein by reference. This communication method includes transmitting, by the host device 120: a first message conveying a set of steps to be performed by the slave device 130; and second messages addressed to a portion of the slave device 130, the second messages conveying a corresponding identifier of the slave device 130 to which the second messages are addressed. The second message requests that the slaves 130 to which they are addressed send corresponding reactions to the master 120 in corresponding expected time intervals. The communication method further includes implementing, by the slave device 130: receiving a first message, reading the executed step set and implementing the steps according to the read set; and receiving the second message and reacting to the second message by sending a reaction destined for the master device 120 over the bus at corresponding expected time intervals.

Each device 120, 130 generally includes a transceiver unit (122, 132, respectively) and circuitry (124, 134, respectively). More specifically, transceiver units 122, 132 couple circuits 124, 134 to bus 110. Preferably, the transceiver units 122, 132 are connected to the circuits 124, 134 and the bus 110, i.e. the units 122, 132 connect the circuits 124, 134 to the bus 110. More specifically, the units 122, 132 have input/outputs 126, 136 connected to the bus 110. Each input/output 126, 136 typically includes two nodes that are each connected to two wires that make up bus 110. During operation, to transmit data, the circuits 124, 134 transmit signals T120, T130 that pass the logic levels to be applied to the bus 110. The transceiver units 122, 132 provide signals R120, R130 to the circuits 124, 134 that convey the logic level of the bus 110, e.g., the signals R120, R130 are at a high level for the recessive state of the bus and the signals R120, R130 are at a low level for the dominant state of the bus 110. Thus, the circuits 124, 134 receive data communicated by the bus 110.

Circuits 124 and 134 may correspond to any conventional circuit that uses data transferred by a serial bus and/or provides data to be transferred by a serial bus. Further, the circuits 124, 134 are generally configured to perform logic and/or digital processing of data. The one or more circuits 134 may include one or more sensors and/or actuators (not shown). In a preferred example, one or more of the circuits 134 couple, preferably connect, light emitting diodes of the LED lights of the vehicle and enable control of various visual effects of the LED lights. Each circuit 134 may include processing circuitry, such as a microprocessor, for sequentially processing data.

Fig. 2 illustrates a timing diagram of one embodiment of a method of communicating in a system of the same type as system 100 illustrated in fig. 1. More specifically, the figure shows, in a very schematic way, the curves of the following parameters as a function of time: signal T120 of device 120 to be applied to bus 110 by unit 122; a level V130 of the input/output 136 of one of the devices 130, which corresponds, for example, to the potential of one node of the input/output 126; signal T130 of device 130 provided by unit 132 to circuit 134; signal T130 of device 130 to be applied to bus 110 by unit 132; a level V120 of the input/output 126 of the device 120, which corresponds to, for example, the potential of one node of the input/output 126; and a signal R120 of the device 120 provided by the unit 122 to the circuit 124.

The signal and level change between values corresponding to the two levels of the bus 110, preferably corresponding to the dominant (D) and recessive (R) states of the CAN bus 110. The signal and level are shown during a portion of a frame transmitted by device 120 and received by device 130. The method is described in the following example in which device 120 is a master and device 130 is a slave, but this example is not limiting, and the described embodiments are compatible with any method of transmitting and receiving frames transmitted by a serial bus, preferably a CAN bus.

The master device 120 continuously transmits the bits 210, 210A until time t0. Bit 210A ends at time t0. It is understood by this succession that the level of the signal T120 to be applied to the bus 110 does not change between two successive bits of the same value, and the channel (passage) between successive bits of different value corresponds to the rising edge 240 or the falling edge 242. The successive bits are defined by instants tS, in other words, each instant tS is located at the end of transmitting one bit and at the beginning of transmitting the next bit. The rising edge 240 corresponds here to a channel from the dominant state to the recessive state, while the falling edge 242 corresponds here to a channel from the recessive state to the dominant state. Preferably, bit 240A is in a recessive state. For bits in the dominant state, the application of signal T120 includes placing bus 110 low. For bits in the recessive state, the application of signal T120 includes bringing bus 110 high. For example, during the transmission of bits 210 and 210A, signal R120 received by master device 120 remains in an implicit state.

Preferably, the bits have a predetermined duration, which allows distinguishing between consecutive bits of the same level. More preferably, the bits of the frame have the same bit duration TBIT, which is generally defined by the above-mentioned standard for CAN buses. Thus, the time tS is regularly repeated.

Preferably, the bits of the frame have the order predetermined by the standard mentioned above for the CAN bus. Thus, consecutive bits 210, 210A preferably include data bits and possibly padding bits. Furthermore, the set of consecutive bits typically ends with an error detection bit, such as a Cyclic Redundancy Check (CRC) type, followed by a boundary bit ending at time t0 (bit 210A).

Starting at time t0, and preferably until time t1, master device 120 does not send further bits, but rather expects to receive an acknowledgement of receipt transmitted by bus 110. In other words, bit 210A is the last bit in the succession of bits. More specifically, between times t0 and t1, at sampling point SP220 (i.e., the time at which the state of bus 110 is read), master device 120 determines whether the state of bus 110 corresponds to the result of transmitting a reception acknowledgement by slave device 130 or at least one slave device 130. To this end, preferably, if the bus 110 is placed in a dominant state by the slave 130 or at least one slave 130 at the sampling point SP220, the master 120 places the bus 110 in a recessive state and performs reception of a reception acknowledgement. The period from time t0 to time t1 preferably has a duration equal to the bit duration TBIT.

Preferably, after time t1, master device 120 retransmits bit 230, typically a receipt of an acknowledgement boundary bit and an end of frame bit.

The rising edge 240 and falling edge 242 of the signal T120 prior to application on the bus 110 are toggled by the corresponding rising edge 250 and falling edge 252 as they arrive at the input/output 136. Thus, edges 250 and 252 define the arrival period of bits sent by master device 120 at input/output 136.

At sample points SP, SPA, unit 132 reads the value of the corresponding bit 210, 210A that arrives at input/output 136. At each sampling point SP, SPA, the unit 132 holds a read value. For each sampling point SP, SPA, the signal R130 provided by the unit 132 takes the value saved at that sampling point until the next sampling point. Thus, after each rising edge 240 or falling edge 242 of signal T120, signal R130 has a rising edge 260 or falling edge 262, respectively. In the example shown, the reading of bit 210A corresponds to one of the rising edges 260 of signal R130. Thus, signal R130 passes bits from cell 132 to circuit 134. Thus, communication between device 120 and device 130 is obtained.

The unit 132 uses the edges 250 and/or 252 to define the sampling points SP in a synchronized manner with respect to the arrival periods at the input/output 136. To this end, the unit 132 receives an edge, preferably a falling edge 252, for synchronization. Synchronization is performed from the moment the edge is received.

For unit 132, the synchronization includes: the time tE defining the arrival period at the input/output 136 is estimated (i.e., determined or evaluated). Within a certain accuracy, the arrival period of each bit starts and ends at time tE. In other words, the time tE defines an estimated arrival period for bits at the input/output 136 that corresponds to the arrival period of bits within the estimated accuracy of the time tE.

The processing unit evaluates the instant tE such that: within the clock accuracy comprised in the slave device 130, the instants tE are regularly repeated with a time interval equal to the bit duration TBIT or substantially equal to the duration TBIT; and those instants tE at which bits are separated by edges for synchronization coincide or substantially coincide with the reception of the front-end. In other words, the instant tE is located at the reception of the edge and/or at an integer or substantially integer multiple of the duration TBIT after the reception of the edge. Preferably, the unit 132 comprises a circuit (not shown) for detecting the arrival of an edge for synchronization, so that the reception of an edge is defined by the moment in time at which the signal inside the unit 132 switches to a level corresponding to the detected edge. The described embodiments are compatible with conventional methods of synchronizing the reception of bits with the arrival of bits (i.e., obtaining the estimated time instant tE).

In the estimated arrival period of each bit, that is, between the estimated start time tE of the arrival period of the bit and the estimated end time tE of the arrival period of the bit, the sampling point is a time at which a predetermined portion SP% of the bit duration TBIT has elapsed from the estimated start time tE of the arrival period of the bit. For example, the predetermined portion SP% represents between 50% and 80% of the bit duration TBIT, preferably approximately 70% of the bit duration TBIT.

In the example shown, the reception acknowledgement is sent from the device 130 by placing the signal T130 applied to the bus 110 in a dominant state. Preferably, the signal T130 remains in an recessive state during reception of the bits 210, 210A as long as the last bit 210A is not read, i.e. at least up to the sampling point SPA. Therefore, it is preferable to transmit the reception acknowledgement after the sampling point SPA.

It is suggested here that the transmission of the receipt acknowledgement begins before the end of the estimated arrival period 265 at bit 210A. The transmission of the reception acknowledgement starts at a time T272 when the signal T130 has a falling edge 272. Thus, time t272 is located before the estimated end time tE of the arrival period of the last bit 210A. Preferably, the reception acknowledgement is sent up to a time T270, and the signal T130 has a rising edge 270 at this time T270. In the example shown, between a start time t272 and an end time t270 of receipt of the acknowledgement, the unit 132 places the bus 110 in a dominant state. For example, during the transmission of the reception acknowledgement, the signal R130 received from the device 130 remains in an implicit state.

The falling edge 272 and rising edge 270 of the signal T130 are respectively transitioned by falling edge 282 and rising edge 280 at the input/output 126 where they reach the master device 120. The receipt acknowledgement is received by the device 120 at the sampling point SP220 (dominant state between the edges 290 and 292 of the signal R120).

In effect, edges 250 and 252 reach input/output 136 during the transfer of bits 210 and 210A from master device 120 to slave device 130, after edges 240 and 242 of signal T120. In other words, there is a lag between the sending of bits by the master device 120 and the arrival of those bits at the input/output 136. In addition, edges 250 and 252 are not as steep as edges 240 and 242 of signal T120 as they reach input/output 136. In other words, the change in level V430 during edges 250, 252 is longer than the change in level of signal T120 to be applied. The level change V430 during edges 250 and 252 may further have noise aspects (not shown), such as oscillations before stabilizing at the edge ends.

Similarly, in practice, edges 282 and 280 arrive after edges 272 and 270 during the transfer of a receipt acknowledgement from device 130 to master device 120. In other words, there is a lag between the sending of a receipt acknowledgement by the master device 120 and the arrival of the receipt acknowledgement at the input/output 126. In addition, edges 282 and 280 are not as steep as edges 272 and 270 of signal T130 when they reach input/output 136. The level change V120 during edges 282 and 280 may also have a noise aspect (not shown).

These hysteresis and these noise aspects are caused by various phenomena (such as attenuation and parasitics) that occur during propagation from input/output 126 to input/output 136 and from input/output 136 to input/output 126 on bus 110. The longer the bus 110 and the more parasitics the input/output experiences, the greater the hysteresis and the more significant the noise aspect.

Furthermore, during the transmission of bits 210 and 210A, edges 240 and 242 of signal T120 are transformed by edges 240 'and 242' of level V120 of input/output 126, potentially exhibiting noise aspects and lags (not shown) in practice with respect to edges 240 and 242, which are combined with those (noise aspects and lags) generated by propagation on bus 110. Similarly, during the transmission of a reception acknowledgement, edges 272 and 270 of signal T130 are transformed by edges 272 'and 270' of level V130 of input/output 136, potentially exhibiting noise aspects and lags (not shown) in practice with respect to edges 272 and 270, which are combined with those (noise aspects and lags) generated by propagation on bus 110.

As a result of the hysteresis and noise aspects of edge 250, the hysteresis actually occurs between a time tS defining the bit 210 transmitted by master device 120 and a time tE defining the estimated arrival period of the bit on input/output 136 of slave device 130.

It is envisioned that the receipt acknowledgement may be sent only when bit 210A has completed its arrival. For example, it is conceivable that in order to synchronize the reception acknowledgement with the bits of the frame, the reception acknowledgement is transmitted at the time tE at which the end of arrival of the bit 210A is estimated to occur. There is thus a risk of: at the sampling point SP220 for sampling acknowledgements of receipt by the master device 120, the starting edge of the acknowledgement of receipt (dashed line 282') is not completed. In contrast, providing a send-receive acknowledgement before the end of the estimated arrival period 265 at bit 210A makes it possible to reduce the risk that the sampling point is not located after the end of edge 282 for a given length of bus 110 and a given spurious level. Thereby reducing the risk that the master device 120 does not properly receive the receipt acknowledgement. In other words, at a given length, the level of reliability of communications via bus 110 has increased. In the same manner, the length of the bus 110 may be increased at a given level of reliability, which corresponds to the increase in hysteresis mentioned above. It is also possible to maintain a constant hysteresis at a given level of reliability by maintaining the length but increasing the operating frequency of the bus 110 (in other words, decreasing the duration TBIT). Thus, by providing an acknowledgement of the beginning of the transmission of the receipt before the end of cycle 265, the operation may be expedited and/or the length of bus 110 increased and/or operational reliability increased relative to the parasitics affecting bus 110.

Preferably, the transmission end time t270 of the reception acknowledgement is located before the end of the period 295 with duration TBIT, which follows the estimated arrival period 265 of bit 210A. In this way, it can be ensured that transmitting the reception acknowledgement by the slave device 130 does not interrupt the master device 120 from transmitting the bits 230 of the frame following the reception acknowledgement. More preferably, the duration of the transmission of the reception acknowledgement is equal to the bit duration or substantially equal to the bit duration, within the accuracy of the clock cycle time.

Preferably, the sending of the reception acknowledgement is performed at least before the sampling point SP220 of the reception acknowledgement. In other words, the time t270 follows the sampling point SP 220. In this way, it can be ensured that the level of the bus 110 is always at the transmission level of the reception acknowledgement when the reception acknowledgement is read by the master device 120.

The fact that the reception acknowledgement is sent after the sampling point SPA of bit 210A allows the slave device 130 to verify that all consecutive bits 210, 210A before the reception acknowledgement has been received before the reception acknowledgement was sent. More preferably, in the case where the slave device 130 includes a clock and a processing unit for processing data in clock beat order, a delay DLY of at least one cycle time of the clock inside the slave device 130 is provided between the sampling point SPA and the transmission start time t272 of the reception acknowledgement.

Preferably, the delay DLY between the sampling point SPA and the instant t272 is less than three clock cycles time, more preferably equal to one clock cycle. This allows to increase the time between the transmission start instant t272 of the reception acknowledgement and the end of the estimated arrival period 265 of the bit 210A compared to a longer delay and thus to increase the reliability and/or the length and/or frequency of the bus as mentioned above. To this end, all verification operations (e.g., verification of the CRC) are preferably performed prior to sampling point SPA, such that once bit 210A is received, a single operation to verify the value of received bit 210A is still performed prior to sending a receipt acknowledgement.

Preferably, the slave device 130 is configured such that, for example, it is programmed such that the delay DLY between the sampling point SPA and the transmission start instant t272 of the reception acknowledgement can be programmed, preferably selected from multiples of the clock cycle time. For example, the selection is made by providing a value to the program. This allows slave device 130 to accommodate various lengths of bus 110 and/or various operating frequencies of bus 110 and/or various levels of parasitics to which bus 110 is subjected.

The system implementing the method described above with reference to fig. 2 preferably includes a plurality of slave devices 130. In this case, more preferably, the delay DLY between the sampling point SPA and the transmission start time t272 in each slave device 130 has the same duration for all slave devices 130. This allows the master device 120 to optimize the reception of the reception acknowledgement.

Various embodiments and modifications have been described. Those skilled in the art will appreciate that certain features of the embodiments can be combined and that other variations will be readily apparent to those skilled in the art.

Finally, the actual implementation of the embodiments and variations described herein is within the ability of those skilled in the art to describe based on the functionality provided above.

Claims

1. A method for acknowledging communications via a bus, comprising:

receiving at least one frame, the at least one frame comprising consecutive bits transmitted over a serial bus;

estimating an arrival period of a last bit of the consecutive bits; and

before the estimated arrival period ends, transmission of a reception acknowledgement is started.

2. The method of claim 1, wherein each of the consecutive bits has the same bit duration.

3. The method of claim 2, wherein the estimated arrival period ends at a multiple of the bit duration after receiving an edge.

4. The method of claim 2, wherein the receipt acknowledgement has a duration greater than or equal to the bit duration.

5. The method of claim 2, wherein the receipt acknowledgement has a duration equal to the bit duration.

6. The method of claim 2, further comprising: the transmission of the receipt acknowledgement ends before the end of a further cycle having the bit duration and starts at the end of the arrival cycle.

7. The method of claim 6, wherein the transmission of the receipt acknowledgement has a duration equal to the bit duration.

8. The method of claim 1, wherein the sending of the receipt acknowledgement is performed at least up to a sampling point of the receipt acknowledgement.

9. The method of claim 1, wherein the sending of the receipt acknowledgement begins at the end of a delay after a sample point of the last one of the consecutive bits.

10. The method of claim 9, wherein the delay is less than three cycles of a clock.

11. The method of claim 10, wherein the delay is a single cycle time of the clock.

12. An electronic device configured to:

estimating an arrival period of a last bit of the consecutive bits; and

the transmission of the reception acknowledgement is started before the estimated end of the arrival period.

13. The electronic device of claim 12, wherein the transmission of the receipt acknowledgement begins at an end of a delay after a sampling point of the last one of the consecutive bits; and is also provided with

Wherein the electronic device is further configured to read a value of the last one of the consecutive bits at the sampling point of the last one of the consecutive bits.

14. The electronic device of claim 13, wherein the delay is programmable.

15. The electronic device of claim 12, further comprising a clock; and is also provided with

Wherein the sending of the receipt acknowledgement begins at the end of a delay after the sampling point of the last one of the consecutive bits; and is also provided with

Wherein the delay is less than three cycles of the clock.

16. An electronic system, comprising:

a serial bus; and

one or more first devices coupled to the serial bus, wherein each of the first devices is configured to:

receiving at least one frame, the at least one frame comprising consecutive bits transmitted over the serial bus;

estimating an arrival period of a last bit of the consecutive bits; and

17. The electronic system of claim 16, wherein the serial bus is a Controller Area Network (CAN) bus.

18. The electronic system of claim 16, wherein the transmission of the receipt acknowledgement begins at an end of a delay after a sampling point of the last one of the consecutive bits, and wherein the delay is common to the first device.

19. The electronic system of claim 16, further comprising a second device coupled to the serial bus, wherein the second device is configured to transmit:

a first message conveying a set of steps performed by the first device; and

a second message addressed to a portion of the first device, the second message conveying a corresponding identifier of the first device to which the second message is addressed, the second message requesting the first device to which the second message is addressed to send a corresponding response to the second device at a corresponding expected time interval,

wherein the first device is configured to receive the first message, read the set of steps to be performed, and implement steps according to reading the set of steps; and is also provided with

Wherein the portion of the first device is configured to receive the second message and react to the second message by sending a corresponding reaction on the serial bus destined for the second device at the corresponding expected time interval.

20. The electronic system of claim 16, wherein each of the first devices further comprises a clock; and is also provided with

Wherein, for each of the first devices, the sending of the receipt acknowledgement begins at the end of a delay after a sample point of the last one of the consecutive bits, and the delay is less than three cycles of the clock.