CN112701094A - Power device packaging structure and power electronic equipment - Google Patents
Power device packaging structure and power electronic equipment Download PDFInfo
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- CN112701094A CN112701094A CN202011483308.8A CN202011483308A CN112701094A CN 112701094 A CN112701094 A CN 112701094A CN 202011483308 A CN202011483308 A CN 202011483308A CN 112701094 A CN112701094 A CN 112701094A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 92
- 229910052751 metal Inorganic materials 0.000 claims abstract description 92
- 230000017525 heat dissipation Effects 0.000 abstract description 39
- 238000005485 electric heating Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 9
- 230000009977 dual effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- WSNMPAVSZJSIMT-UHFFFAOYSA-N COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 Chemical compound COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 WSNMPAVSZJSIMT-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a power device packaging structure and power electronic equipment, the power device packaging structure includes: the lead frame comprises a base island and a first pin electrically connected with the base island; a metal sheet; the power chip is provided with a first electrode and a second electrode on two opposite surfaces respectively; the first electrode is combined on the front surface of the metal sheet through the conductive combination layer; the second electrode is combined with the base island through the conductive combination layer; a package body encapsulating the power chip, a portion of the lead frame, and a portion of the metal sheet; the back surface of the metal sheet is exposed out of the packaging body, and a part of the first pin is exposed out of the packaging body. The power electronic equipment comprises the power device packaging structure. According to the power device packaging structure, the metal sheet is arranged on the electrode on one surface of the power chip and exposed, so that an electric heating conduction path is shortened, an electric heating conduction path is enlarged, the heat dissipation performance is improved, and the reliability of a product is improved; the power electronic equipment has better performance.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power device packaging structure and power electronic equipment.
Background
The existing semiconductor packaging structure packages the chip to play the roles of placing, fixing, sealing and protecting the chip; by the packaging technology, the chip is isolated from the outside so as to prevent the electrical performance from being reduced due to the corrosion of impurities in the air to a chip circuit. In a typical package structure, the electrode contacts on the chip are typically routed to pins on the package housing, which in turn make connections to other devices via wires on the circuit board. For many power electronic device products, the packaging structure is of great importance.
When the power device works, heat can be generated; high power semiconductor devices need to handle more current and generate more heat. For the packaging structure of the power device, if the heat cannot be efficiently dissipated to the external medium in time, the working performance of the semiconductor device will be greatly affected, and even the failure will be caused. The existing power device packaging structure accelerates heat dissipation by adding a heat sink on the outside, but the heat dissipation mode still cannot meet the heat dissipation requirement.
Disclosure of Invention
One object of an embodiment of the present invention is to: the power device packaging structure shortens a conduction path, enlarges the conduction path, improves the heat dissipation performance of a product, and improves the reliability of the product.
Another object of an embodiment of the present invention is to: provided is a power electronic device having superior performance and higher reliability.
In order to achieve the purpose, the invention adopts the following technical scheme:
a power device package structure, comprising:
the lead frame comprises a base island and a first pin electrically connected with the base island;
a metal sheet;
the power chip is provided with a first electrode and a second electrode on two opposite surfaces respectively; the first electrode is bonded to the front side of the metal sheet by a conductive bonding layer; the second electrode is bonded to the base island by a conductive bonding layer;
a package body encapsulating the power chip, a portion of the lead frame, and a portion of the metal sheet; the back surface of the metal sheet is exposed out of the packaging body, and a part of the first pin is exposed out of the packaging body.
Preferably, at least one of the power chips is a triode chip; a source electrode and a grid electrode are arranged on a first surface of the triode chip, and a drain electrode is arranged on a second surface opposite to the first surface;
the source electrode is a first electrode, and the drain electrode is a second electrode; alternatively, the drain electrode is the first electrode, and the source electrode is the second electrode.
Preferably, the lead frame further comprises a second pin insulated from the base island, and the gate is electrically connected with the second pin through an electric connector;
or, the power device packaging structure further comprises a conductive sheet, the grid is combined on the front surface of the conductive sheet through a conductive combining layer, and the back surface of the conductive sheet is exposed out of the packaging body.
Preferably, the number of the power chips is two;
one power chip is a triode chip, and the other power chip is a diode chip; or, the two power chips are triode chips.
Preferably, the number of the power chips is two; the two power chips are both diode chips;
the first electrode is an anode, and the second electrode is a cathode; or, the first electrode is a cathode and the second electrode is an anode.
Preferably, a surface of the base island remote from the power chip is exposed from the package.
Preferably, the base islands are entirely encapsulated inside the package.
Preferably, the power module comprises two or more power chips and the metal sheets with the same number as the power chips; the first electrode of each power chip is combined with one metal sheet.
Preferably, at least one set of devices is included; each device group comprises two power chips and a metal sheet; in the device group, the first electrodes of the two power chips are both bonded to the metal sheet.
A power electronic device comprises the power device packaging structure and a circuit board, wherein the back surface of the metal sheet is welded on the circuit board, and the pins are welded on the circuit board.
The invention has the beneficial effects that: according to the power device packaging structure, the metal sheet is arranged on the first electrode on one surface of the power chip and exposed, so that the external leading of the first electrode is realized, and the heat dissipation is also realized; the packaging structure shortens an electric heating conduction path, enlarges the electric heating conduction path, improves the heat dissipation performance and improves the reliability of products; the power electronic equipment adopts the power device packaging structure, so that the performance is better and the reliability is higher.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is a longitudinal sectional view of a power device package according to an embodiment of the invention;
fig. 2 is a plan view of an internal structure of a power device package structure according to an embodiment of the present invention;
fig. 3 is a bottom schematic view of a power device package structure according to an embodiment of the invention;
fig. 4 is a top schematic view of a power device package structure according to an embodiment of the invention;
fig. 5 is a longitudinal sectional view of a power device package according to an embodiment of the invention;
fig. 6 is a top schematic view of a power device package structure according to yet another embodiment of the invention;
fig. 7 is a schematic application diagram of a power device package structure according to an embodiment of the present invention;
fig. 8 is a longitudinal sectional view of a power device package according to an embodiment of the invention;
fig. 9 is a plan view of the internal structure of the power device package structure according to the embodiment of the present invention;
fig. 10 is a bottom schematic view of a power device package structure according to an embodiment of the invention;
fig. 11 is a longitudinal sectional view of a power device package according to an embodiment of the invention;
fig. 12 is a longitudinal sectional view of a power device package according to an embodiment of the invention;
fig. 13 is a plan view of the internal structure of the power device package structure according to the embodiment of the present invention;
fig. 14 is a bottom schematic view of a power device package structure according to an embodiment of the invention;
fig. 15 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
fig. 16 is a longitudinal sectional view of a power device package according to an embodiment of the invention;
fig. 17 is a plan view of the internal structure of the power device package structure according to the embodiment of the present invention;
fig. 18 is a bottom schematic view of a power device package structure according to an embodiment of the invention;
fig. 19 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
fig. 20 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
fig. 21 is a plan view of the internal structure of a power device package structure according to an embodiment of the present invention;
fig. 22 is a bottom schematic view of a power device package structure according to an embodiment of the invention;
fig. 23 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
fig. 24 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
fig. 25 is a plan view of the internal structure of a power device package structure according to an embodiment of the present invention;
fig. 26 is a bottom schematic view of a power device package structure according to an embodiment of the invention;
fig. 27 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
fig. 28 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
fig. 29 is a plan view of the internal structure of a power device package structure according to an embodiment of the present invention;
fig. 30 is a bottom schematic view of a power device package structure according to an embodiment of the invention;
fig. 31 is a longitudinal sectional view of a power device package according to an embodiment of the present invention;
in the figure: 10. a power chip; 11. a triode chip; 111. a source electrode; 112. a gate electrode; 12. a diode chip; 20. a lead frame; 21. a base island; 22. a first pin; 23. a second pin; 30. a metal sheet; 40. an electrical connection; 50. a conductive bonding layer; 60. a package body; 80. a circuit board; 90. a heat sink.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise explicitly specified or limited, the terms "connected" and "fixed" are to be understood broadly, e.g., as being fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The invention provides a power device packaging structure which improves the heat dissipation performance of a product and improves the reliability of the product.
As shown in fig. 1 to 31, in an embodiment of the power device package structure of the present invention, the package structure includes:
a lead frame 20 including a base island 21, and a first pin 22 electrically connected to the base island 21;
a power chip 10 having a first electrode and a second electrode respectively disposed on opposite surfaces thereof, the first electrode being bonded to the front surface of the metal sheet 30 by a conductive bonding layer 50, and the second electrode being bonded to the base island 21 by the conductive bonding layer 50;
a package body 60 formed by curing a package material, which encapsulates the power chip 10, a portion of the lead frame 20, and a portion of the metal sheet 30; the back surface of the metal sheet 30 is not encapsulated by the encapsulation body 60, and the back surface of the metal sheet 30 is exposed out of the encapsulation body 60; a portion of the first pins 22 is not encapsulated by the package body 60, and a portion of the first pins 22 is exposed from the package body 60.
Wherein, the base island 21 is used as a carrier of the power chip 10, and the first pin 22 is used for connecting the second electrode with an external circuit; the exposed portion of the metal sheet 30 serves both to connect the first electrode to an external circuit and to conduct heat directly to the external medium of the package structure.
A part of the first pins 22 is exposed out of the package 60, one end of the first pins 22 may extend out of the package 60, or one surface of the first pins 22 is exposed out of the package 60; the metal sheet 30 may be exposed at other positions than the back surface.
As shown in fig. 7, in the application of the power device package structure, the back surface of the metal sheet 30 may be soldered to the circuit board 80, and the first pin 22 is soldered to the circuit board 80, so as to achieve conduction between the first electrode and the circuit on the circuit board 80, and between the second electrode and the circuit on the circuit board 80; in this way, heat generated by the power chip 10 is conducted to the circuit board 80 through the metal sheet 30 without being conducted through pins. It should be noted that this application is not intended to limit the present invention.
In the conventional power device package structure, the first electrode needs to be connected to the pin of the lead frame 20 through a metal wire or a metal bridge to be led out through the pin.
In the power device package structure of the present invention, in order to solve the problems of heat generation and heat dissipation, the metal sheet 30 is disposed in the region of the first electrode, so that the first electrode can be led to an external circuit carrier (such as a circuit board 80) through the metal sheet 30, and thus, the electrical conduction path can be shortened to reduce the resistance and the heat dissipation; moreover, the heat generated by the power chip 10 can be directly and rapidly dissipated outwards through the exposed part of the metal sheet 30 without being guided by a pin, so that the heat conduction path can be shortened, the heat conduction efficiency is improved, and the heat dissipation efficiency is high; furthermore, the area of the metal sheet 30 is large, the area of the metal sheet 30 is equivalent to the area of the first electrode, the contact area of the metal sheet 30 and the first electrode is large, the heat and electricity conduction area can be increased, and the conduction channel is enlarged, so that the resistance is greatly reduced, the heat consumption is reduced, the heat dissipation efficiency is improved, and the heat dissipation performance is improved.
It should be noted that, in this embodiment, the heat dissipation performance is at least affected by the resistance and the heat dissipation efficiency.
The power device packaging structure provided by the invention has the advantages that the heat dissipation performance is improved, and the reliability is improved; and the quantity of metal wires and pins can be reduced, and materials are saved.
Preferably, in order to ensure the highest heat dissipation efficiency, the front surface of the metal sheet 30 covers 70% to 100% of the area of the electrode region of the first electrode.
Specifically, the metal sheet 30 may be, but is not limited to, a copper sheet.
In the present invention, the conductive bonding layer 50 is formed by curing a conductive bonding material, the conductive bonding material is coated on the first electrode or the metal sheet 30, and the first electrode and the metal sheet 30 are bonded by welding or adhesion. The bonding material may be one or more of a lead-tin-silver alloy, a gold-silicon alloy, and a silver paste, or may be other bonding materials, and the components of the bonding material are not limited to the invention.
The power device package structure includes one or two or more power chips 10. In the embodiment of the present invention, the number of the power chips 10 is one or two.
In other embodiments, the number of the power chips 10 in the package structure may also be multiple, such as four, six, etc., for example, in the smart power module package structure, multiple power chips 10 may be included.
The power chip 10 may adopt a triode chip 11, and when the package structure includes the triode chip 11, a first side of the triode chip 11 is provided with a source 111 and a gate 112, and a second side is provided with a drain, and the first side and the second side are opposite sides.
Specifically, the package structure uses the source 111 as a first electrode, the metal sheet 30 is disposed on the source 111, and the drain is used as a second electrode; alternatively, the package structure has the drain electrode as the first electrode, the metal sheet 30 on the drain electrode, and the source electrode 111 as the second electrode.
The power chip 10 may also employ a diode chip 12, and when the package structure includes the diode chip 12, a first side of the diode chip 12 is provided with an anode, a second side is provided with a cathode, and the first side and the second side are opposite sides.
Specifically, the package structure uses the anode as a first electrode, the metal sheet 30 is disposed on the anode, and the cathode as a second electrode; alternatively, the package structure has the cathode as the first electrode, the metal sheet 30 on the cathode, and the anode as the second electrode.
The power device packaging structure of the invention can be implemented by at least the following specific embodiments:
the first implementation mode comprises the following steps: the power device packaging structure comprises a power chip 10, wherein the power chip 10 is a triode chip 11.
Preferably, the first surface of the triode chip 11 faces the front surface of the metal sheet 30, the source electrode 111 serves as a first electrode, and the source electrode 111 is bonded to the front surface of the metal sheet 30 by the conductive bonding layer 50.
The second embodiment: the power device packaging structure comprises two power chips 10, wherein the two power chips 10 are both triode chips 11.
Preferably, the first faces of the two triode chips 11 are both facing the front face of the metal sheet 30, and both adopt the source electrode 111 as the first electrode, and the source electrode 111 is combined with the metal sheet 30.
Of course, one of the triode chips 11 may use the source 111 as the first electrode, and the other triode chip 11 may use the drain as the first electrode.
The third embodiment is as follows: the power device package structure includes two power chips 10, wherein one power chip 10 is a triode chip 11, and the other power chip 10 is a diode chip 12.
When the power device package structure is applied to a power electronic device, the diode chip 12 has functions of forward conduction and reverse cut-off, and when the gate 112 is turned off by matching the triode chip 11 and the diode chip 12, a reverse current generated due to inductance or the like can be cut off by the diode chip 12. Therefore, the power device packaging structure meets the working requirement of higher power.
Preferably, the first surface of the triode chip 11 faces the metal sheet 30, the source 111 serves as a first electrode, and the source 111 is combined with the metal sheet 30.
The fourth embodiment: the power device packaging structure comprises two power chips 10, wherein both the two power chips 10 are diode chips 12.
In the first to third embodiments, the triode chip 11 preferably uses the source 111 as the first electrode, the source 111 is soldered to the metal sheet 30 in a downward direction, and the drain is soldered to the base island 21 of the lead frame 20 in an upward direction, and in contrast to the flip-chip scheme where "the drain is used as the first electrode, the drain is soldered to the metal sheet 30 in a downward direction, and the source 111 is soldered to the base island 21 in an upward direction", in the packaging process, the side of the power chip 10 where the source 111 is located has only one electrode, and the drain can be directly bonded to the base island 21 by a conductive bonding material such as spot soldering, which is more convenient for packaging.
The triode chip 11 of the present invention can be, but is not limited to, a MOSFET chip; the triode chip 11 is a switching device.
The power device packaging structure of the invention can realize heat dissipation by at least adopting the following two modes:
first, as shown in fig. 1, 8, 12, 16, 20, 24, and 28, the power device package structure is a double-sided heat dissipation structure, and one side of the base island 21 away from the power chip 10 is exposed outside the package body 60; in this way, a portion of the heat may be dissipated outward through the exposed portion of the bottom metal sheet 30 of the package structure, and a portion of the heat may be dissipated outward through the exposed portion of the top base island 21 of the package structure.
Specifically, when the power device package structure with double-sided heat dissipation is applied, as shown in fig. 7, a heat sink 90, such as a tooth-shaped heat sink 90, may be additionally installed on the exposed surface of the base island 21, so as to achieve higher heat dissipation performance and working performance.
Second, as shown in fig. 5, 11, 15, 19, 23, 27, and 31, the power device package structure is a single-sided heat dissipation structure, and the base island 21 is entirely encapsulated in the package body 60. The power device packaging structure with the single-side heat dissipation is adopted, the packaging cost is relatively low, and the heat dissipation performance is improved compared with the traditional packaging structure.
For the power device package structure including the triode chip 11, the external leading of the gate 112 can be realized in at least two ways:
first, the lead frame 20 further includes a second pin 23 electrically insulated from the base island 21, the gate 112 is electrically connected to the second pin 23 through an electrical connector 40, and the gate 112 is led out through the second pin 23 to connect the gate 112 to an external circuit. Electrical connection 40 may be, but is not limited to, a conductive metal wire or a conductive metal bridge, such as a copper wire, a copper bridge, etc.
Secondly, the package structure further includes a metal conductive sheet, the gate 112 is bonded to the front surface of the conductive sheet through the conductive bonding layer 50, the back surface of the conductive sheet is exposed out of the package body 60, and the gate 112 is directly led out through the conductive sheet, so as to realize the connection between the gate 112 and an external circuit. The conductive sheet may be, but is not limited to, a copper sheet. Both the conductive sheet and the metal sheet 30 are exposed from the bottom of the package body 60.
For a power device package structure including at least two power chips 10, the metal sheet 30 can be disposed in at least two ways:
first, when two or more power chips 10 are included, the same number of metal sheets 30 as the number of the power chips 10 are provided; the first electrode of each power chip 10 is bonded to one of the metal sheets 30.
The embodiment of the invention is as follows: the power device packaging structure comprises two power chips 10 and two metal sheets 30; the two metal sheets 30 are a first metal sheet and a second metal sheet, respectively; the first electrode of one power chip 10 is bonded to the first metal sheet through the conductive bonding layer 50, and the first electrode of the other power chip 10 is bonded to the second metal sheet through the conductive bonding layer 50.
For the package structure in which the two first electrodes of the two power chips 10 do not need to be electrically connected, two independent metal sheets 30 may be used to respectively realize the external leading of the two first electrodes.
Secondly, one, two or more groups of devices are included; each group of devices comprises two power chips 10 and a metal sheet 30; in each device group, the first electrodes of the two power chips 10 are bonded to the metal sheet 30.
The embodiment of the invention is as follows: the power device packaging structure comprises two power chips 10; the two first electrodes are bonded to the same metal sheet 30 by a conductive bonding layer 50. For the package structure in which the two first electrodes of the two power chips 10 need to be electrically connected, the same metal sheet 30 is directly led out, so that the two power chips 10 can radiate heat outwards, and a metal wire or a metal bridge is not required to be specially used for connecting the two first electrodes, so that the package process is simple.
The present invention provides the following fourteen power device package structures, which should be noted, but the fourteen structures should not be taken as limitations of the present invention, and other types of structures may also be adopted:
the structure I is as follows: as shown in fig. 1-4, the single chip structure includes a power chip 10, where the power chip 10 is a triode chip 11; it is a double-sided heat dissipation structure.
The structure II is as follows: as shown in fig. 5, 2, 3, and 6, the single chip structure includes a power chip 10, where the power chip 10 is a triode chip 11; it is a single-side heat dissipation structure.
The structure is three: as shown in fig. 8, 9, 10 and 4, the dual-chip structure includes two power chips 10, and both the two power chips 10 are triode chips 11; it is a double-sided heat dissipation structure, and includes two metal sheets 30.
The structure is four: as shown in fig. 11, 9, 10, and 6, the dual-chip structure includes two power chips 10, where the two power chips 10 are both triode chips 11; it is a single-side heat dissipation structure, and includes two metal sheets 30.
The structure is five: as shown in fig. 12, 13, 14 and 4, the dual-chip structure includes two power chips 10, where both the two power chips 10 are triode chips 11; it is a double-sided heat dissipation structure, and two power chips 10 share one metal sheet 30.
The structure is six: as shown in fig. 15, 13, 14 and 6, the dual-chip structure includes two power chips 10, and both the two power chips 10 are triode chips 11; the single-side heat dissipation structure is provided, and the two power chips 10 share one metal sheet 30.
The structure is seven: as shown in fig. 16, 17, 18 and 4, the dual chip structure includes two power chips 10, one of the power chips 10 is a transistor chip 11, and the other power chip 10 is a diode chip 12; it is a double-sided heat dissipation structure, and includes two metal sheets 30.
The structure eight: as shown in fig. 19, 17, 18 and 6, the dual chip structure includes two power chips 10, one of the power chips 10 is a transistor chip 11, and the other power chip 10 is a diode chip 12; it is a single-side heat dissipation structure, and includes two metal sheets 30.
The structure is nine: as shown in fig. 20, 21, 22 and 4, the dual chip structure includes two power chips 10, one of the power chips 10 is a transistor chip 11, and the other power chip 10 is a diode chip 12; it is a double-sided heat dissipation structure, and two power chips 10 share one metal sheet 30.
The structure is ten: as shown in fig. 23, 21, 22 and 6, the dual chip structure includes two power chips 10, one of the power chips 10 is a transistor chip 11, and the other power chip 10 is a diode chip 12; the single-side heat dissipation structure is provided, and the two power chips 10 share one metal sheet 30.
The structure eleven: as shown in fig. 24, 25, 26 and 4, the dual chip structure includes two power chips 10, where both power chips 10 are diode chips 12; it is a double-sided heat dissipation structure, and includes two metal sheets 30.
The structure twelve: as shown in fig. 27, 25, 26 and 6, the dual chip structure includes two power chips 10, where both power chips 10 are diode chips 12; it is a single-side heat dissipation structure, and includes two metal sheets 30.
Structure thirteen: as shown in fig. 28, 29, 30 and 4, the dual chip structure includes two power chips 10, where both power chips 10 are diode chips 12; it is a double-sided heat dissipation structure, and two power chips 10 share one metal sheet 30.
The structure is fourteen: as shown in fig. 31, 29, 30 and 6, the dual chip structure includes two power chips 10, where both power chips 10 are diode chips 12; it is a double-sided heat dissipation structure, and two power chips 10 share one metal sheet 30.
The invention also provides the power electronic equipment which has better heat dissipation performance and working performance and higher reliability.
The power electronic device comprises the power device packaging structure in the above embodiment, and further comprises a circuit board 80, the back surface of the metal sheet 30 is soldered to the circuit board 80, and the pins are soldered to the circuit board 80.
The power electronics may be, but is not limited to, a drive, a frequency converter, an inverter power supply, an air conditioner, and the like.
In the description herein, it is to be understood that the terms "upper", "lower", "left", "right", and the like are used in an orientation or positional relationship based on that shown in the drawings, and are used for convenience of description and simplicity of operation only, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A power device package structure, comprising:
a lead frame (20) including a base island (21), and a first pin (22) electrically connected to the base island (21);
a metal sheet (30);
a power chip (10) having a first electrode and a second electrode on opposite surfaces thereof, respectively; the first electrode is bonded to the front side of the metal sheet (30) by a conductive bonding layer (50); the second electrode is bonded to the base island (21) by a conductive bonding layer (50);
a package (60) encapsulating the power chip (10), a portion of the lead frame (20) and a portion of the metal sheet (30); the package (60) is exposed from the back surface of the metal sheet (30), and a part of the first pin (22) is exposed from the package (60).
2. The power device package structure of claim 1, wherein at least one of the power chips (10) is a triode chip (11); a source electrode (111) and a grid electrode (112) are arranged on a first surface of the triode chip (11), and a drain electrode is arranged on a second surface opposite to the first surface;
the source electrode (111) is a first electrode, and the drain electrode is a second electrode; or, the drain electrode is the first electrode, and the source electrode (111) is the second electrode.
3. The power device package structure of claim 2, wherein the lead frame (20) further comprises a second pin (23) insulated from the base island (21), the gate (112) being electrically connected to the second pin (23) by an electrical connector (40);
or, the power device packaging structure further comprises a conductive sheet, the grid (112) is combined with the front surface of the conductive sheet through a conductive combining layer (50), and the back surface of the conductive sheet is exposed out of the packaging body (60).
4. The power device package structure according to any one of claims 1-3, wherein the number of the power chips (10) is two;
one power chip (10) is a triode chip (11), and the other power chip (10) is a diode chip (12); or, the two power chips (10) are both triode chips (11).
5. The power device package structure according to claim 1, wherein the number of the power chips (10) is two; the two power chips (10) are both diode chips (12);
the first electrode is an anode, and the second electrode is a cathode; or, the first electrode is a cathode and the second electrode is an anode.
6. The power device package structure according to claim 1, wherein a surface of the base island (21) away from the power chip (10) exposes the package body (60).
7. The power device package structure according to claim 1, wherein the base island (21) is entirely encapsulated inside the package body (60).
8. The power device package structure according to any one of claims 1-3 and 5-7, comprising two or more power chips (10) and the same number of metal sheets (30) as the number of the power chips; the first electrode of each power chip (10) is bonded to one of the metal sheets (30).
9. The power device package structure of any one of claims 1-3, 5-7, comprising at least one set of devices; each group of the devices comprises two power chips (10) and a metal sheet (30); in the device group, the first electrodes of the two power chips (10) are bonded to the metal sheet (30).
10. A power electronic device comprising the power device package structure of any one of claims 1-9, and further comprising a circuit board (80), wherein the back surface of the metal sheet (30) is soldered to the circuit board (80), and the pins are soldered to the circuit board (80).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011483308.8A CN112701094A (en) | 2020-12-15 | 2020-12-15 | Power device packaging structure and power electronic equipment |
| PCT/CN2021/101671 WO2022127060A1 (en) | 2020-12-15 | 2021-06-22 | Power device packaging structure and power electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011483308.8A CN112701094A (en) | 2020-12-15 | 2020-12-15 | Power device packaging structure and power electronic equipment |
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| CN112701094A true CN112701094A (en) | 2021-04-23 |
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| WO (1) | WO2022127060A1 (en) |
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| WO2022127060A1 (en) * | 2020-12-15 | 2022-06-23 | 杰群电子科技（东莞）有限公司 | Power device packaging structure and power electronic device |
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| CN218123406U (en) * | 2022-09-09 | 2022-12-23 | 苏州汇川控制技术有限公司 | Power device and power equipment |
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| US20070296077A1 (en) * | 2006-06-27 | 2007-12-27 | Hvvi Semiconductors, Inc. | Semiconductor component and method of manufacture |
| CN102201449A (en) * | 2011-05-27 | 2011-09-28 | 电子科技大学 | Low-heat-resistance packaging structure of power MOS (Metal Oxide Semiconductor) device |
| CN102308383A (en) * | 2009-02-05 | 2012-01-04 | 费查尔德半导体有限公司 | Semiconductor die packages and manufacturing approach thereof |
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| JP4708755B2 (en) * | 2004-10-04 | 2011-06-22 | 富士通テン株式会社 | Regulatory structure of heat dissipation material |
| CN106298722B (en) * | 2016-09-26 | 2019-10-11 | 无锡新洁能股份有限公司 | A kind of encapsulating structure and manufacturing method of high current power semiconductor |
| CN109727943A (en) * | 2019-02-27 | 2019-05-07 | 无锡新洁能股份有限公司 | A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance |
| CN110071079A (en) * | 2019-04-24 | 2019-07-30 | 深圳第三代半导体研究院 | A kind of power device packaging structure and its method |
| CN212084994U (en) * | 2020-05-15 | 2020-12-04 | 杰群电子科技（东莞）有限公司 | Parallel packaged device group |
| CN112701094A (en) * | 2020-12-15 | 2021-04-23 | 杰群电子科技（东莞）有限公司 | Power device packaging structure and power electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070296077A1 (en) * | 2006-06-27 | 2007-12-27 | Hvvi Semiconductors, Inc. | Semiconductor component and method of manufacture |
| CN102308383A (en) * | 2009-02-05 | 2012-01-04 | 费查尔德半导体有限公司 | Semiconductor die packages and manufacturing approach thereof |
| CN102201449A (en) * | 2011-05-27 | 2011-09-28 | 电子科技大学 | Low-heat-resistance packaging structure of power MOS (Metal Oxide Semiconductor) device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022127060A1 (en) * | 2020-12-15 | 2022-06-23 | 杰群电子科技（东莞）有限公司 | Power device packaging structure and power electronic device |
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