CN1126378C - Message receiver - Google Patents
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- CN1126378C CN1126378C CN97102293A CN97102293A CN1126378C CN 1126378 C CN1126378 C CN 1126378C CN 97102293 A CN97102293 A CN 97102293A CN 97102293 A CN97102293 A CN 97102293A CN 1126378 C CN1126378 C CN 1126378C
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Abstract
In a message receiving device, radio paging signals are demodulated into baseband signals, and the baseband signals are decoded into corresponding data. Address information is restored from the data, and message information is restored from the data. The restored message information is subjected to error code correction processing, and on the other hand, that the restored address information is subjected to the error code correction processing is prevented.
Description
Technical field
The present invention relates to this class message (information) receiver of paging receiver or selectivity paging receiver.
Background technology
In the typical wireless paging communication net, each paging receiver distributes respectively and obtains different identification (ID) signal.Can utilize any one paging receiver of ID signal call of being distributed to.Usually, have and represent the signal of message to be sent to the paging receiver of being called out, show this message on the display of paging receiver.
In this wireless paging communication net, along with the length lengthening of processing message, the number of bit errors in the message signals that paging receiver reduced increases, and the electrical power that paging receiver consumed also increases.
Each all comprises radio wave acceptance division and CPU common paging receiver.CPU can produce radio noise, and the radio wave acceptance division is caused interference.Along with CPU unit interval valid function step number (being the activity ratio of CPU) increases, the radio noise level that CPU produces is also raising.
United States Patent (USP) 5,142, the method for 699 the have demonstrated radio noise level that a kind of CPU of inhibition drive clock signal produced at radio wave acceptance division duration of work.Specifically, United States Patent (USP) 5,142,699 radio paging receivers that disclose comprise acceptance division, decoding part and from a plurality of call signals, distinguish certain specific call signal, be the CPU of treated message signals with the special packet signal processing after the specific call signal.Acceptance division is intermittently to devote oneself to work.Decoding part is then devoted oneself to work according to first clock signal that first clock generator provides.One switching circuit is connected with first clock generator CPU selectively with the second clock generator.CPU is that the second clock signal that provides according to the second clock generator when acceptance division is not worked is devoted oneself to work.The frequency of second clock signal is far above the frequency of first clock signal.Thereby CPU does not handle the special packet signal according to the second clock signal with processing speed rapidly when acceptance division is devoted oneself to work, make it to become treated message signals.In a word, CPU is driven by first clock signal when acceptance division is worked.
Summary of the invention
The object of the invention is to provide a kind of improved message receiver.
One aspect of the present invention provides a kind of message receiving system, comprising: first device that radio paging signal is demodulated into baseband signal; Baseband signal is decoded as second device of corresponding data; Alternately carry out the CPU of this data processing and other operations; Produce first clock generator of first clock signal; Produce the second clock generator of second clock signal, the frequency of first clock signal is higher than the frequency of second clock signal; CPU responds the 3rd device of first clock enabling signal CPU action when carrying out described data processing; Response second clock signal made the 4th device of CPU action when CPU carried out described other operation; Wherein when data with m bits/words * n word be unit when staggered CPU have the error correcting capability place of α bit, CPU by first clock start signal receives α data unit, and this α data unit is being stored in buffer is handled m * n bit in the time interval data block.
Description of drawings
Fig. 1 is the block diagram of the wireless message receiver of first embodiment of the invention.
Fig. 2 is the schematic diagram of paging signal form.
Fig. 3 is the schematic diagram that the data two dimension is expressed in the data block.
Fig. 4 is the flow chart of the block of CPU in the control chart 1.
Fig. 5 is the flow chart of functional block among Fig. 4.
Fig. 6 signal provides the map table that concerns between 8 error code sign indicating number type data and the mistake indication bit number.
Fig. 7 is the block diagram of the wireless message receiver of second embodiment of the invention.
Fig. 8 is the flow chart of the block of CPU in the control chart 7.
Fig. 9 is the block diagram of the wireless message receiver of third embodiment of the invention.
Figure 10 is the flow chart of the block of CPU in the control chart 9.
Figure 11 is the block diagram of the wireless message receiver of fourth embodiment of the invention.
Figure 12 is the schematic diagram of paging signal form.
Figure 13 is the schematic diagram that the data two dimension is expressed in the data block.
Figure 14 is the flow chart of the block of CPU among control Figure 11.
Figure 15 is the flow chart of functional block among Figure 14.
Figure 16 signal provides the map table that concerns between 8 error code sign indicating number type data and the mistake indication bit number.
Figure 17 is the block diagram of the wireless message receiver of fifth embodiment of the invention.
Figure 18 is the flow chart of the block of CPU among control Figure 17.
Figure 19 is the time-domain diagram that wireless message receiver receives treatment situation and data processing situation among Figure 17.
Figure 20 is the block diagram of the wireless message receiver of sixth embodiment of the invention.
Figure 21 and Figure 22 are the flow charts of the block of CPU among control Figure 20.
Embodiment
First embodiment
Referring to Fig. 1, wireless message receiver (radio paging receiver) comprises antenna 21 and acceptance division 22 subsequently.Antenna 21 is used to capture the radio wave signal that sends as the base station.Usually radio wave signal comprise have synchronizing information, the paging signal of address information and message information.Synchronizing information is in address information and message information front.Address information then is positioned at the front of message information.Address information comprises information of identification code.The radio wave signal that antenna 21 is captured is fed to acceptance division 22.Acceptance division 22 is demodulated into corresponding baseband signal with radio wave signal.Receive this baseband signal with the decoder after the acceptance division 22 23, baseband signal is decoded as corresponding data.
Decoder 23 links to each other with the CPU 24 with I/O port (interface), handling part, RAM and ROM combination.CPU 24 can be substituted by microcomputer, DSP (digital signal processor) or other similar device.The data of CPU 24 receiver decoders 23 outputs.CPU 24 is by the reduction of data information of identification code (address information) that is received.CPU 24 links to each other with display 25.CPU 24 also is connected with acceptance division 22.CPU 24 works according to inner ROM program stored.
The information of identification code that the wireless message receiver of Fig. 1 will be distributed in the past (predetermined information of identification code or presumptive address information) is stored among the ROM in the CPU 24.Predetermined information of identification code (presumptive address information) can be stored among the ROM of CPU 24 outsides.
CPU 24 makes comparisons with predetermined information of identification code (presumptive address information) to the information of identification code (address information of being reduced) that is reduced according to program.When the information of identification code that is reduced (address information of being reduced) was in fact consistent with predetermined information of identification code (presumptive address information), CPU 24 was by the reduction of data message information that is received.CPU 24 delivers to display 25 with the message information that is reduced subsequently, and control display 25, makes display 25 will show the message information that is reduced.
When the information of identification code that is reduced (address information of being reduced) obviously with predetermined information of identification code (presumptive address information) when inconsistent, CPU 24 is the reduction of data message information from being received not, increases with the activity ratio that prevents CPU 24.Like this, advantage is to suppress the radio noise level that CPU 24 produces.In addition, CPU24 ends acceptance division 22 activities, to save electric power.And CPU 24 also keeps display 25 inertias.In this occasion, do not manifest any message information on the display 25.
Fig. 2 illustrates the form of paging signal 121.A head of paging signal 121 is synchronizing signals (pit synchronization signal) 122, then is data block 123.Synchronizing signal 122 has predetermined logic state with the corresponding bit sequence of given sign indicating number type (synchronous code-type).Data in each data block 123 are that unit is staggered by " n " word, here " n " expression one given integer.The sum of data block 123 equals a given number " j ".Usually, the data block 123 of one or more fronts is represented information of identification code (address information), and the data block 123 of back is then represented message information.
Fig. 3 illustrates the two dimension of data in the data block 123 and expresses.As shown in Figure 3, the capacity of each data block is " m " bit * " n " word, here " m " expression one given integer.Each word has the bit 124 of the main information of representative and represents the bit 125 of error code correction information.Main information comprises information of identification code (address information) or message information.The error correcting code that adopts has and the corresponding error correcting capability of " α " bit, here " α " expression one given integer.Among Fig. 3, label 126 expression stands staggered handle and by the n bit data unit of forming with indexed bits in each word.In the base station (sending station), the data in each data block 123 are divided work " m " individual data unit.Each data block 123 order of base station send " m " individual data unit.
Decoder 23 comprises a bit synchronization portion, by acceptance division 22 output signals one sampling clock signal takes place, and is corresponding with the bit synchronization signal 122 in the paging signal 121.Decoder 23 comprises a sampling portion, and the response sampling clock signal carries out periodic sample to the output signal of acceptance division 22, is first data with the output signal bit by bit decoding of acceptance division 22.Decoder 23 comprises a release of an interleave portion, is second data with the first data release of an interleave.Decoder 23 comprises a pair of buffer storage, each all have with paging signal 121 in a data block 123 corresponding capacity.In second data with paging signal 121 in each data block 123 corresponding parts be according to priority, alternately to be written to buffer storage.
Usually, a certain buffer storage stands data and writes when handling in the decoder 23, and another buffer storage is by CPU 24 accesses, thus CPU 24 sense data (second data) thus.
CPU 24 works according to inner ROM program stored.Fig. 4 is the flow chart of the block of execution when at every turn receiving paging signal 121.
As shown in Figure 4, the first step 31 of block is read 1 latest data of a certain buffer storage in the decoder 23.
Whether step 33 is determined by the address information (information of identification code) of the 1 blocks of data representative of reading in fact consistent with the ROM presumptive address information (predetermined information of identification code) of being stored in the CPU 24.When in fact inconsistent with presumptive address information (predetermined information of identification code) by the address information (information of identification code) of the 1 blocks of data representative of reading, program just enters step 37 by step 33.When in fact consistent with presumptive address information (predetermined information of identification code) by the address information (information of identification code) of the 1 blocks of data representative of reading, program then enters step 36 by step 33.
Error correction code information in 1 blocks of data that step 34 response is read makes the message information in 1 blocks of data of being read stand error code correction and handles.Like this, step 34 just is reduced to the message information of correcting the result by 1 blocks of data of being read.
The next step 35 of step 34 should be corrected as a result message information and store in the CPU24 among the RAM as a message information.Step 35 back program enters step 36.
Be appreciated that by previous explanation CPU 24 does not allow 1 blocks of data of representing the address stand the error code correction processing.Thereby, effective work step number decline (activity ratio that is CPU 24 descends) of CPU 24.After in fact the address information (information of identification code) that discovery is represented by 1 blocks of data of being read was different from presumptive address information (predetermined information of identification code), CPU 24 made acceptance division 22 termination activity given intervals to save electric power.And in this case, CPU 24 is except the step in the execution graph 4 not the step 37.Therefore, effective work step number decline (activity ratio that is CPU 24 descends) of CPU 24.
As shown in Figure 5, step 33 has 33A, 33B and 33C step by step.Map interlinking 4 steps 32 first step by step 33A between the address information (information of identification code) of 1 blocks of data read representative and presumptive address information (being scheduled to information of identification code), carry out exclusive-OR operation.Address information by the 1 blocks of data representative of being read has a given bit number.Presumptive address information also has this given bit number.For example this given bit number number equals 8,32 or 64.Now this given bit number of supposition is 8.The result who carries out exclusive-OR operation generates 8 error code sign indicating number type data.In 8 error code sign indicating number type data, the address information of the bright 1 blocks of data representative of reading of " 0 " bit table is consistent with the logic state of its corresponding positions of presumptive address information, and " 1 " position then shows the address information of the 1 blocks of data representative of being read and the logic state inconsistent (makeing mistakes) of its corresponding positions of presumptive address information.
Meet the 33B step by step of 33A step by step, the map table by storing among the ROM in the reference CPU 24 calculates mistake indication bit number in the 8 bit error code sign indicating number type data.As shown in Figure 6, map table provides the relation between 8 bit code sign indicating number type data and the mistake indication bit number.
Meet the 33C step by step of 33B step by step, mistake indication bit number and is preset number relatively.When mistake indication bit number greater than presetting number, program just enters Fig. 4 step 37 by 33C step by step.Preset when several when mistake indication bit number is no more than, program then enters Fig. 4 step 36 by 33C step by step.This presets number and preferably equals given integer " α ", and it is relevant with the error correcting capability of error correcting code.
Second embodiment
Referring to Fig. 7, wireless message receiver (radio paging receiver) comprises antenna 221 and follow-up acceptance division 222.Antenna 221 is used to capture for example radio wave signal of base station transmission.Usually radio wave signal comprise have synchronizing information, the paging signal of address information and message information.Synchronizing information is in the front of address information and message information.Address information then is positioned at the front of message information.Address information comprises information of identification code.The radio wave signal that antenna 221 is captured is fed to acceptance division 222.Acceptance division 222 is demodulated into corresponding baseband signal with radio wave signal.
The follow-up decoder 223 of acceptance division 222 receives this baseband signal, and baseband signal is decoded as corresponding data.
High frequency clock signal generator 226 inertias when usually, low-frequency clock signal generator 227 is movable.Like this, the low-frequency clock signal work that CPU 224 common response generators 227 take place, the activity ratio of CPU 224 is relatively low.This advantage is to suppress the radio noise level that CPU 224 takes place.Will address CPU 224 response block synchronizing signals starting high frequency clock signal generator 226 and 227 activities of termination low-frequency clock signal generator as the back.During the given after this short period, high frequency clock signal generator 226 and low-frequency clock signal generator 227 are kept activity and inertia respectively, and CPU 224 is the high frequency clock signal that takes place of response generator 226 but not low-frequency clock signal work that generator 227 takes place.
The work of CPU 224 can change between high speed mode and low speed mode.When high frequency clock signal generator 226 inertias and low-frequency clock signal generator 227 when movable, CPU 224 is in the tick-over mode.When 226 activities of high frequency clock signal generator and during low-frequency clock signal generator 227 inertias, CPU 224 is in the high speed operation mode.CPU 224 works in during the low speed mode, and the radio noise level that CPU 224 produces is effectively suppressed.
The information of identification code that the wireless message receiver of Fig. 7 will be distributed in the past (predetermined information of identification code or presumptive address information) is stored among the ROM in the CPU 224.Predetermined information of identification code (presumptive address information) can be stored among the ROM of CPU 224 outsides.
When the information of identification code that is reduced (address information of being reduced) obviously with predetermined information of identification code (presumptive address information) when inconsistent, CPU 224 from the second reduction of data message information, does not increase with the activity ratio that prevents CPU 224.This advantage is to suppress the radio noise level that CPU 224 produces.In addition, CPU 224 ends acceptance division 222 activities, to save electric power.And CPU 224 also keeps display 225 inertias.In this occasion, display 225 does not manifest any message information.
As shown in Figure 2, a head of paging signal 121 is synchronizing signals (bit synchronization signal) 122, then is data block 123.Synchronizing signal 122 has predetermined logic state with the corresponding bit sequence of given sign indicating number type (synchronous code-type).Data in each data block 123 are that unit is staggered by " n " word, here " n " expression one given integer.The sum of data block 123 equals a given number " j ".Usually, the data block 123 of one or more fronts is represented information of identification code (address information), and the data block 123 of back is then represented message information.
As shown in Figure 3, the capacity of each data block is " m " bit * " n " word, here " m " expression one given integer.Each word has the bit 124 of the main information of representative and represents the bit 125 of error code correction information.Main information comprises information of identification code (address information) or message information.The error correcting code that adopts has and the corresponding error correcting capability of " α " bit, here " α " expression one given integer.Among Fig. 3, label 126 expression stands staggered handle and by the n Bit data unit of forming with indexed bits in each word.In the base station (sending station), the data in each data block 123 are divided work " m " individual data unit.Each data block 123 order of base station send " m " individual data unit.
As shown in Figure 8, block first step 251 determines in the block sync signal whether pulse generation is arranged.Pulse generation is arranged in block sync signal, and program enters step 252 by step 251.Otherwise, repeating step 251.
Step 252 starting high frequency clock signal generator 226 makes the 227 termination activities of low-frequency clock signal generator, makes CPU 224 enter the high speed operation mode.The next step 253 of step 252 currently from decoder 223 does not stand a certain buffer storage 223A or 223B that data write processing and reads 1 blocks of data.The next step 254 of step 253 is the 21 blocks of data with the 1 blocks of data release of an interleave of being read.
Whether step 256 is determined by the address information (information of identification code) of the 21 blocks of data representative in fact consistent with the ROM presumptive address information (predetermined information of identification code) of being stored in the CPU 224.When in fact inconsistent with presumptive address information (predetermined information of identification code) by the address information (information of identification code) of the 21 blocks of data representative, program just enters step 260 by step 256.When in fact consistent with presumptive address information (predetermined information of identification code) by the address information (information of identification code) of the 21 blocks of data representative, program then enters step 259 by step 256.Step 33 among step 256 and Fig. 4 and Fig. 5 is similar.
Step 260 makes acceptance division 222 termination activities, one given intervals (predetermined time interval) to save electric power.After the step 260, program enters step 263.
Error correction code information in step 257 response the 21 blocks of data makes the message information in the 21 blocks of data stand error code correction and handles.Like this, step 257 just from the 21 blocks of data reduction correct result's message information.
The next step 258 of step 257 should be corrected as a result message information and store in the CPU224 among the RAM as a message information.Step 258 back program enters step 259.
Step 259 determines whether all data blocks 123 in the paging signal 121 are all handled.All data blocks 123 in paging signal 121 are all handled, and program just enters step 261 by step 259.Otherwise program just enters step 262 by step 259.
Step 262 makes the 226 termination activities of high frequency clock signal generator, and starting low-frequency clock signal generator 227 makes CPU 224 enter the tick-over mode.After the step 262, program is returned step 251.
Step 261 starting display 225 is sent to display 225 with whole part message informations among the RAM in the CPU 224.Whole part message informations are formed the complete message information through reduction.Step 261 control display 225 makes display 225 will show complete message information.After the step 261, program enters step 263.
Step 263 makes the 226 termination activities of high frequency clock signal generator, and starting low-frequency clock signal generator 227 makes CPU 224 enter the tick-over mode.After the step 263, the current execution circulation constipation bundle of this block.
The 3rd embodiment
Referring to Fig. 9, wireless message receiver (radio paging receiver) comprises that the back follows the antenna 321 of receiving unit 322.Antenna 321 is used for catching the radio wave signal by for example base station.Radio wave signal comprises paging signal and the information signal that has the pit synchronization signal sequence usually.Pit synchronization signal comprises logic state and pre-determines bit sequence into the given bit mode of correspondence (synchronization bit pattern).Information signal is represented address information and message information.Address information is prior to message information.Address information comprises information of identification code.The radio wave signal that antenna 321 captures is input to receiving unit 322.Receiving unit 322 is demodulated into corresponding baseband signal with radio wave signal.
Follow at decoder 323 receiving baseband signals of receiving unit 322 back and with it and be decoded as corresponding data.
Decoder 323 is connected to has the CPU 324 that I/O port (interface), processing section, RAM and ROM combine.CPU 324 can use microprocessor, DSP or other similar device to replace.CPU 324 receives the data that produced by decoder 323.CPU 324 detects or calculates the error rate, and this error rate relates to a part of data corresponding with pit synchronization signal that decoder 323 produces.CPU 324 handles the remainder that decoder 323 produces data.CPU 324 according to detect the error rate two kinds dissimilar between the switch data processing mode.CPU 324 basic tasks are that the deinterleaving data that will receive is second data.CPU 324 restores information of identification code (address information) from second data.CPU 324 is connected to display 325.CPU 324 also is connected with receiving unit 322.CPU 324 is according to the program running that is stored among the built-in ROM.
The wireless message receiver of Fig. 9 contains the information of identification code (predetermined information of identification code or predetermined address information) of previous distribution at the ROM of CPU 324 internal memory.Predetermined information of identification code (predetermined address information) also can be stored in the ROM of CPU 324 outsides.
According to program, CPU 324 is second data with the dateout release of an interleave of decoder 323.In addition, CPU 324 restores information of identification code (address information) from second data.And CPU 324 compares the information of identification code (address information of reduction) of reduction with predetermined information of identification code (predetermined address information).When information of identification code (address information of reduction) that reduces and predetermined information of identification code (predetermined address information) basically identical, CPU 324 just restores message information from second data.Subsequently, thus CPU 324 inputs to the message information of reduction display 325 and controls display 325 message data that shows reduction directly perceived on display 325.
Obvious when inconsistent when information of identification code (address information of reduction) and the predetermined information of identification code (predetermined address information) of reduction, CPU 324 can not reduce message information from second data, thereby avoids the activity aggravation of CPU 324.This helps suppressing the radio noise level that CPU 324 produces.In addition, CPU 324 makes receiving unit 322 be in resting state to save electric power usually.And CPU 324 also makes display 325 keep resting state.Thus in this case, be revealed without any message information on the display 325.
As shown in Figure 2, the stem of paging signal 121 is the synchronizing signal (pit synchronization signal) 122 that the back is followed data block 123 in succession.Synchronizing signal 122 comprises logic state and pre-determines bit sequence into the given bit mode of correspondence (synchronization bit pattern).Data in each piece 123 are that unit is staggered with " n " individual word, here the given integer of " n " expression.The sum of piece 123 equals given number " j ".Generally, information of identification code (address information) is represented and the piece 123 expression message informations of back in one or more 123 of fronts.
As shown in Figure 3, the capacity of a piece is " n " individual word of " m " bit, and " m " represents given integer here.Each speech comprises the bit 124 of representing main information and the bit 125 of representing error correction code information.Main information comprises information of identification code (address information) or message information.Used error correcting code can be corrected the mistake of " α " individual bit, and " α " is integer here.In Fig. 3, stand the n Bit data unit that the staggered bit number of handling and being equated by quantity constitutes in label 126 each words of expression.(cell site) locates in the base station, and the data in the piece 123 are divided into " m " individual data unit." m " individual data unit of each piece 123 of base station sequential transmission.
Decoder 323 comprises a bit synchronous part, and it produces sampled clock signal from receiving unit 322 output signals corresponding with pit synchronization signal 122 first halfs the paging signal 121.Decoder 323 comprises a sampling section, its response sample clock signal, periodically to the output signal of receiving unit 322 sample with the output signal bit-by-bit of receiving unit 322 be decoded as first data.The first data first half of decoder 323 pit synchronization signal 122 latter halfs in CPU324 provides corresponding to paging signal 121.Therefore, the first half of first data is the bit synchronous data.Decoder 323 comprises a jumbo buffer storage 323A.Corresponding to the first data first half of each piece 123 in the paging signal 123 by the zones of different of write buffering memory 323A successively.Thereby buffer storage 323A can be visited by CPU 324 first data can be read by CPU 324.
CPU 324 is according to the program running that is stored among the built-in ROM.Figure 10 shows the flow chart of performed block when at every turn receiving paging signal 121.As shown in figure 10, the first step 351 is the bit synchronous data computation bit error rates by decoder 323 outputs.Particularly, step 351 with bit synchronous data and preset reference data bit-by-bit compare.Default reference data has the corresponding given bit mode of bit synchronous data usually.The bit that corresponding bits is equal in logic state and the preset reference data in the bit synchronous data is regarded as correct bit.The bit that logic state is different with corresponding bits in the preset reference data in the bit synchronous data is regarded as error bit.Step 351 is counted to determine the quantity of error bit each error bit.Step 351 is calculated the error rate from the ratio of error bit number and total bit number.
The step 352 of following after step 351 determines that whether the error rate of calculating is greater than predetermined base ratio.When the error rate of calculating during greater than predetermined base ratio, program enters step 353 from step 352.Otherwise program skips to step 354 from step 352.
Step 353 is waited for the given time, during this period the first used data is write the buffer storage 323A in the decoder 323.After the step 353, program enters step 354.
The execution of waiting step 353 has reduced the activity of CPU 324.This helps suppressing the radio noise level that CPU 324 produces.Therefore, if the error rate of calculating greater than predetermined base ratio, then writes less adverse effect receiving unit 322 and decoder 323 operations of CPU 324 during the buffer storage 323A in the decoder 323 in the first used data.
Step 354 is read 1 blocks of data from the buffer storage in the decoder 323.When each execution in step 354,1 blocks of data of being read all changes successively.Following the 1 blocks of data release of an interleave that the step 355 after step 354 will read is the 21 blocks of data.
Follow step 356 after step 355 and determine the 21 blocks of data whether presentation address information (information of identification code) or message information.When the 21 blocks of data presentation address information (information of identification code), program enters step 357 from step 356.When the 21 blocks of data was represented message information, program entered step 358 from step 356.
Step 357 determine address information (information of identification code) that the 21 blocks of data represents whether haply with the ROM that is stored in CPU 324 in to preestablish address date (preestablishing information of identification code) identical.The address information of representing when the 21 blocks of data (information of identification code) basically with predefined address date (preestablishing information of identification code) not simultaneously, program enters step 361 from step 357.When the address information of representing when the 21 blocks of data (information of identification code) was identical with predefined address date (preestablishing information of identification code) basically, program entered step 360 from step 357.Step 33 in step 357 and the Figure 4 and 5 is similar.
Step 361 makes receiving unit 322 (in predetermined time interval) in a given interval be in resting state to save electric power.After step 361, finish the execution circulation of present procedure section.
Error correction information in step 358 response the 21 blocks of data is carried out correction process to the message information in the 21 blocks of data.Therefore, step 358 just restores the final message information after the error correction from the 21 blocks of data.
Follow step 359 after the step 358 final message information after with error correction and deposit RAM among the CPU 324 in as the message information sheet.After step 359, program enters step 360.
Step 360 determines whether all pieces 123 in the paging signal 121 were handled.After piece all in the paging signal 121 123 had all been handled, program entered step 362 from step 360.Otherwise program is returned step 354 from step 360.
Step 362 activates display 325 and sends all message informations of RAM among the CPU 324 to display 325.All message information sheets all are made of the complete message information of reduction.Thereby step 362 control display 325 is the complete message information of demonstration directly perceived on display 325.After step 362, finish the execution circulation of present procedure section.
If when the bit error rate that calculates was not more than predetermined base ratio, program directly entered step 354 from step 352.Therefore in this case, 1 data are sent to CPU 324 and handle subsequently and first data are continuously write in the buffer storage 323A of decoder 323 from the buffer storage 323A in the decoder 323.Like this, the processing of 324 pairs 1 blocks of data of CPU and the first data write buffering memory 323A just carry out synchronously.This helps restoring rapidly complete message information.
The 4th embodiment
Now the fourth embodiment of the present invention will be described.According to the fourth embodiment of the present invention, radio paging signal is demodulated into baseband signal, and baseband signal is interpreted as corresponding data (final decoding data).Address information restores from final decoding data.Message information restores from final decoding data.The message information of reduction stands correction process.The address information of reduction avoids carrying out correction process.
Describe the 4th embodiment now in detail.Referring to Figure 11, wireless message receiver (radio paging receiver) comprises that the back follows the antenna 421 of receiving unit 422.Antenna 421 is used for catching the radio wave signal by for example base station.Radio wave signal comprises the paging signal that has synchronizing information, address information and message information usually.Synchronizing information is prior to address information and message information.Address information is prior to message information.The radio wave signal that antenna 421 captures is input to receiving unit 422.Address information comprises information of identification code.Receiving unit 422 is demodulated into corresponding baseband signal with radio wave signal.
Follow at decoder 423 receiving baseband signals of receiving unit 422 back and with it and be decoded as corresponding data.
Figure 12 shows the form of paging signal 521.The stem of paging signal 521 is the synchronizing signal (pit synchronization signal) 522 that the back is followed data block 523 in succession.Synchronizing signal 522 comprises logic state and pre-determines bit sequence into the given bit mode of correspondence (synchronization bit pattern).Data in each piece 523 are that unit is staggered with " n " individual word, here the given integer of " n " expression.The sum of piece 523 equals given number " j ".Generally, information of identification code (address information) is represented and the piece 523 expression message informations of back in one or more 523 of fronts.
Figure 13 represents for the bidimensional of data in the piece 523.As shown in figure 13, the capacity of a piece is " n " individual word of " m " bit, and " m " represents given integer here.The length of each word is fixed as " m " bit.Each word comprises the bit 524 of representing main information and the bit 525 of representing error correction code information.Main information comprises information of identification code (address information) or message information.Used error correcting code can be corrected the mistake of " α " individual bit, and " α " is integer here.In Figure 13, stand the n Bit data unit that the staggered bit number of handling and being equated by quantity constitutes in label 526 each words of expression.(cell site) locates in the base station, and the data in the piece 523 are divided into " m " individual data unit." m " individual data unit of each piece 523 of base station sequential transmission.
Thereby decoder 423 one of them buffer storage stand usually data write handle and the another one buffer storage by CPU 424 visit sense datas (second data).When writing of each buffer storage in the decoder 424 arrived given numerical value, decoder 423 was to CPU 424 output specific signal.Here, corresponding data block of given numerical value.
Figure 14 shows the flow chart of performed block when at every turn receiving paging signal 521.As shown in figure 14, the first step 431 of block is to close the message receiving flag.The message receiving flag is designated hereinafter simply as sign.After step 431, program enters step 432.Step 432 determines whether buffer is full.When buffer full, program enters step 433.Otherwise repeating step 432.
Step 433 determines whether sign is in opening.When sign was in opening, program entered step 434 from step 433.Otherwise program enters 435 from step 433.Step 434 determines whether the message of passing to relevant wireless message receiver is positioned at current block.When the message of passing to relevant wireless message receiver was positioned at current block, program entered step 435 from step 434.Otherwise program is returned step 432 from step 434.
Step 435 reads a piece.The step 436 of following after step 435 is " 0 " with specification of variables P.Variable P represents the exponent number of code word.After step 436, program enters step 437.Step 437 makes digital P increase 1.The step 438 that is connected on step 437 back determines whether 1 data processing is finished.When 1 data processing was finished, program was back to step 432 from step 438.Otherwise program enters step 439 from step 438.
Step 439 determines whether sign is in closed condition.When sign was in closed condition, program entered step 440 from step 439.Otherwise program enters 441 from step 439.
It is the code word of P that step 440 is taken out exponent number.Step 442 determines whether the address is consistent with each other.When the address was consistent with each other, program entered step 443 from step 442.Otherwise program enters step 444 from step 442.Step 443 makes sign be in opening.After step 443, program is returned step 437.
Step 444 determines whether to check all address informations.After all address informations all were examined, program entered step 445 from step 444.Otherwise program is returned step 437 from step 444.Step 445 makes the operation suspension of receiving unit.After step 445, finish the execution circulation of present procedure section.
Step 441 determines that whether digital P is corresponding to the message code word of passing to relevant wireless message receiver.When digital P when passing to the message code word of relevant wireless message receiver, program enters step 446 from step 441.Otherwise program is returned step 437 from step 441.
It is the code word of P that step 446 is taken out exponent number.The step 447 of following after step 446 is carried out error-correction operation.The step 448 of step 447 back is preserved this message.The step 449 of following after step 448 determines whether the whole message of passing to about wireless message receiver is available.But when the whole message time spent of passing to relevant wireless message receiver, program enters step 450 from step 449.Otherwise program is returned step 437 from step 449.
Step 450 is closed sign.Follow step 451 after step 450 to the peripheral hardware output signal.After step 451, finish the execution circulation of present procedure section.
By aforementioned description as seen, CPU 424 does not carry out correction process to 1 blocks of data of presentation address.This has reduced the number of steps (promptly having reduced the activity of CPU 424) of CPU 424 valid functions.When the address information of finding to be represented by 1 blocks of data that reads (information of identification code) was inequality basically with predetermined address information (predetermined information of identification code), CPU 424 made receiving unit 422 be in resting state to save electric power in given time interval.And in this case, CPU 424 does not carry out other step among Figure 14 except execution in step 445.This has reduced the number of steps (promptly having reduced the activity of CPU 424) of CPU 424 valid functions.
The address information (code word) relevant with wireless message receiver is stored in the ROM of CPU 424.Address information in the ROM of CPU 424 is a code word, and is " m " individual bit, generally equals 32 bits.Address information (code word) in the ROM of CPU424 is divided into " A ", " B ", " C " and " D " four 8 bit section.The m bit codewords of the presentation address information that receives also is divided into " A ", " B ", " C " and " D " four 8 bit section.
As shown in figure 15, step 442 comprises substep 442A, 442B and 442C.For " A ", " B ", " C " and " D " each 8 bit section, the first substep 442A that follows after Figure 14 step 440 carries out xor operation between address information that receives and relevant wireless message receiver address information.Carry out xor operation has produced 8 bits to " A ", " B ", " C " and " D " each 8 bit section error code type data.In each 8 bit difference error code type data, the logic state inconsistent (mistake) of the corresponding bit of the address information that bit " 0 " expression receives address information that bit " 1 " expression receives with the logic state unanimity of the corresponding bit of relevant wireless message receiver address information and relevant wireless message receiver address information.
The substep 442B that follows after substep 442A calculates the indication incorrect bit number of each 8 bit error data with reference to being stored in conversion table in the ROM of CPU 424.As shown in figure 16, conversion table provides 8 bit error data X and the indication incorrect bit is counted relation between the EN (X).Therefore, step 442B has calculated respectively the indication incorrect bit of corresponding 8 bit section " A ", " B ", " C " and " D " and has counted that EN (A), indication incorrect bit count EN (B), the indication incorrect bit is counted EN (C) and indicated incorrect bit to count EN (D).Subsequently, step 442B has calculated the indication incorrect bit and has counted that EN (A), indication incorrect bit count EN (B), the indication incorrect bit is counted EN (C) and indicated incorrect bit to count the summation Res of EN (D).
The substep 442C that follows in substep 442B back compares summation Res and error correcting capability bit number " α ".As summation Res during greater than error correcting capability bit number " α ", the step 444 that program enters Figure 14 from substep 442C.Otherwise the step 443 that program enters Figure 14 from substep 442C.
The 5th embodiment
Now the fifth embodiment of the present invention will be described briefly.According to the 5th embodiment, radio paging signal is demodulated into baseband signal, and baseband signal is interpreted as corresponding data.CPU alternately carries out data processing and other work.First and second clock signals have the first and second predetermined frequencies respectively.The first predetermined frequency is greater than the second predetermined frequency.It responds first clock signal and operates when CPU carries out data processing.Its response second clock signal is operated when CPU carries out other work.The clock generator that produces certain frequency is provided, if the error correcting capability of CPU is that unit is staggered for " α " data with " m " bits/words * " n " word, then CPU has the data processing speed of " m " * " n " bit under this frequency in receiving unit receives between the individual bit period of " n " * " α ".
Referring to Figure 17, wireless message receiver (radio paging receiver) comprises that the back follows the antenna 621 of receiving unit 622.Antenna 621 is used for catching the radio wave signal by for example base station.Radio wave signal comprises the paging signal that has synchronizing information, address information and message information usually.Synchronizing information is prior to address information and message information.Address information is prior to message information.The radio wave signal that antenna 621 captures is input to receiving unit 622.Receiving unit 622 is demodulated into corresponding baseband signal with radio wave signal.
Follow at decoder 623 receiving baseband signals of receiving unit 622 back and with it and be decoded as corresponding data.
Low-frequency clock signal generator 627 generally is in state of activation and high frequency clock signal 626 generally is in unactivated state.Therefore, the low-frequency clock signal that the general response generators 627 of CPU 624 produce and moving, and the activity of CPU 624 is relatively low.This helps suppressing the radio noise level that CPU 624 produces.As described below, CPU 624 response block synchronizing signals and activate high frequency clock signal generator 626 and make low-frequency clock signal generator 627 be in unactivated state.In given short time interval after this, high frequency clock signal generator 626 and low-frequency clock signal generator 627 still are in respectively and activate and unactivated state, and the low-frequency clock signal of the high frequency clock signal of CPU624 response generator 626 generations rather than generator 627 generations is operated.
As shown in figure 12, the stem of paging signal 521 is the synchronizing signal (pit synchronization signal) 522 that the back is followed data block 523 in succession.Synchronizing signal 522 comprises logic state and pre-determines bit sequence into the given bit code type of correspondence (synchronization bit sign indicating number type).Data in each piece 523 are that unit is staggered with " n " individual word, here the given integer of " n " expression.The sum of piece 523 equals given number " j ".Generally, information of identification code (address information) is represented and the piece 523 expression message informations of back in one or more 523 of fronts.
As shown in figure 13, the capacity of a piece is " n " individual word of " m " bit, and " m " represents given integer here.The length of each word is fixed as " m " bit.Each word comprises the bit 524 of representing main information and the bit 525 of representing error correction code information.Main information comprises information of identification code (address information) or message information.Used error correcting code can be corrected the mistake of " α " individual bit, and " α " is integer here.In Figure 13, stand the n Bit data unit that the staggered bit number of handling and being equated by quantity constitutes in label 526 each words of expression.(cell site) locates in the base station, and the data in the piece 523 are divided into " m " individual data unit." m " individual data unit of each piece 523 of base station sequential transmission.
Figure 18 shows the flow chart of performed block when at every turn receiving paging signal 521.As shown in figure 18, the first step 651 of block is to close the message receiving flag.The message receiving flag is designated hereinafter simply as sign.After step 651, program enters step 652.Step 652 determines whether " n " bit is available.As " n " but the bit time spent, program enters step 653 from step 652.Otherwise repeating step 652.
Step 653 determines whether sign is in opening.When sign was in opening, program entered step 654 from step 653.Otherwise program enters 655 from step 653.Step 654 determines whether the message of passing to relevant wireless message receiver is positioned at current block.When the message of passing to relevant wireless message receiver was positioned at current block, program entered step 655 from step 654.Otherwise program is returned step 652 from step 654.
Step 655 reads " n " individual bit.The step 656 of following after step 655 determines whether piece was read.After piece read, program entered step 657 from step 656.Otherwise program is returned step 652 from step 656.
Step 657 makes CPU 624 change the high-speed cruising pattern over to.The step 658 of following after step 657 is carried out the release of an interleave processing.The step 659 of following after step 658 is set at " 0 " with variable P.Variable P represents the exponent number of code word.After step 659, program enters step 660.Step 660 makes digital P increase 1.The step 661 that is connected on step 660 back determines whether 1 data processing is finished.When 1 data processing was finished, program was back to step 662 from step 661.Otherwise program enters step 663 from step 661.
Step 622 makes CPU 624 change low-speed operation mode over to.In step 662, program is returned step 652.Step 663 determines whether sign is in closed condition.When sign was in closed condition, program entered step 664 from step 663.Otherwise program enters step 665 from step 663.
It is the code word of P that step 664 is taken out exponent number.The step 666 of following after step 664 determines whether the address is consistent.When the address was consistent with each other, program entered step 667 from step 666.Otherwise program enters step 668 from step 666.Step 666 is similar with the step 442 in 15 to Figure 14.Step 667 is opened sign.After step 667, program is returned step 660.
Step 668 determines whether to check all address informations.After all address informations all were examined, program entered step 669 from step 668.Otherwise program is returned step 660 from step 668.Step 669 makes the operation suspension of receiving unit.After step 669, program enters step 670.Step 670 makes CPU 624 change low-speed operation mode over to.After step 670, finish the execution circulation of present procedure section.
Step 665 is determined the whether corresponding message code word of passing to relevant wireless message receiver of digital P.When digital P correspondence was passed to the message code word of relevant wireless message receiver, program entered step 671 from step 665.Otherwise program enters step 660 from step 665.
Step 671 is taken out the code word that exponent number equals digital P.The step 672 of following after step 671 is carried out error-correction operation.The step 674 of following after step 673 determines whether the whole message of passing to about wireless message receiver is available.But when the whole message time spent of passing to relevant wireless message receiver, program enters step 675 from step 674.Otherwise program is returned step 660 from step 674.
Step 675 is closed sign.Follow step 676 after step 675 to the peripheral hardware output signal.After step 676, program enters step 670.
Figure 19 shows the sequential of piece 523 data processing and receiving course, and piece is made up of " n " individual word of " m " bit, and error correcting capability is the individual bit of each word " α ".In Figure 19, label 81 expressions receive and store the sequential of " k+1 " piece 523 data sequences, and the data processing sequential of label 82 expression " k " pieces 523.In Figure 19, the sequential of label 83 expression receptions and memory block 523 data sequences, and label 84 is the sequential that receives " α " individual data unit in the current reception piece under the individual bit error correcting capability of each word " α ".In Figure 19, the state of label 85 expression CPU 624 operation clocks.High-frequency clock for example is 1.2288Mhz.Low-speed clock for example is 76.8kHz.Said process is carried out with sequential shown in Figure 19.
The 6th embodiment
Now the sixth embodiment of the present invention will be described briefly.According to the sixth embodiment of the present invention, radio paging signal is demodulated into baseband signal, and baseband signal is interpreted as corresponding data.The error rate to data detects.Determined whether the error rate that is detected is higher than predetermined base ratio.Memory device can be stored data.Treatment facility can reading of data also be handled the data of reading from memory device.If the error rate that detects is greater than predetermined base ratio, the data of operation in being stored in memory device of then suspending treatment facility are whole radio paging signal.After the operation of treatment facility starts from the storage of the whole radio paging signal of correspondence gone into memory device.
Referring to Figure 20, wireless message receiver (radio paging receiver) comprises that the back follows the antenna 721 of receiving unit 722.Antenna 721 is used for catching the radio wave signal by for example base station.Radio wave signal comprises paging signal and the information signal that has the pit synchronization signal sequence usually.Pit synchronization signal comprises logic state and pre-determines bit sequence into the given bit code type of correspondence (synchronization bit sign indicating number type).Information signal is represented address information and message information.Address information is prior to message information.Address information comprises information of identification code.The radio wave signal that antenna 721 captures is input to receiving unit 722.Receiving unit 722 is demodulated into corresponding baseband signal with radio wave signal.
Follow at decoder 723 receiving baseband signals of receiving unit 722 back and with it and be decoded as corresponding data.
As shown in figure 12, the stem of paging signal 521 is the synchronizing signal (pit synchronization signal) 522 that the back is followed data block 523 in succession.Synchronizing signal 522 comprises logic state and pre-determines bit sequence into the given bit code type of correspondence (synchronization bit sign indicating number type).Data in each piece 523 are that unit is staggered with " n " individual word, here the given integer of " n " expression.The sum of piece 523 equals given number " j ".Generally, information of identification code (address information) is represented and the piece 523 expression message informations of back in one or more 523 of fronts.
As shown in figure 13, the capacity of a piece is " n " individual word of " m " bit, and " m " represents given integer here.The length of each word is fixed as " m " bit.Each word comprises the bit 524 of representing main information and the bit 525 of representing error correction code information.Main information comprises information of identification code (address information) or message information.Used error correcting code can be corrected the mistake of " α " individual bit, and " α " is integer here.In Figure 13, stand the n Bit data unit that the staggered bit number of handling and being equated by quantity constitutes in label 526 each words of expression.(cell site) locates in the base station, and the data in the piece 523 are divided into " m " individual data unit." m " individual data unit of each piece 523 of base station sequential transmission.
The block flow chart of carrying out when Figure 21 and 22 is each receiving paging signal 521.As shown in figure 21, the first step 751 of block calculates the error rate.Step 751 is similar to the step 351 among Figure 10.The step 752 of following after step 751 determines whether the error rate is bigger.When the error rate was big, program entered step 753 from step 752.Otherwise program enters step 851 Figure 22 from step 752.
Step 753 is waited for a given time interval.The step 754 of following after step 753 makes CPU 724 change fast mode over to.Follow the step 755 after step 754 to close the message receiving flag.The message receiving flag is designated hereinafter simply as sign.After step 755, program enters step 756.
Step 756 determines whether sign is in opening.When sign was in opening, program entered step 757 from step 756.Otherwise program enters 758 from step 756.Step 757 determines whether the message of passing to relevant wireless message receiver is positioned at current block.When the message of passing to relevant wireless messages receiver was positioned at current block, program entered step 758 from step 757.Otherwise program is returned step 756 from step 757.
Step 758 reads a piece.The step 759 of following after step 758 is carried out the release of an interleave processing.With the step 760 after the step 759 variable P is set at " 0 ".Variable P represents the exponent number of code word.After step 760, program enters step 761.Step 761 makes digital P increase 1.The step 762 that is connected on step 761 back determines whether 1 data processing is finished.When 1 data processing was finished, program was back to step 756 from step 762.Otherwise program enters step 763 from step 762.
Step 763 determines whether sign is in closed condition.When sign was in closed condition, program entered step 764 from step 763.Otherwise program enters 765 from step 763.
Step 764 is taken out the code word that exponent number equals digital P.The step 766 of following after step 764 determines whether the address is consistent.When the address was consistent with each other, program entered step 767 from step 766.Otherwise program enters step 768 from step 766.Step 766 is similar with the step 442 in 15 to Figure 14.Step 767 is opened sign.After step 767, program is returned step 761.
Step 768 determines whether to check all address informations.After all address informations all were examined, program entered step 769 from step 768.Otherwise program is returned step 769 from step 768.Step 769 makes the operation suspension of receiving unit.After step 769, program enters step 770.Step 770 makes CPU 724 be in low-speed operation mode.After step 770, finish the execution circulation of present procedure section.
Step 765 determines whether digital P equals to pass to the message code word of relevant wireless message receiver.When digital P equaled to pass to the message code word of relevant wireless message receiver, program entered step 771 from step 765.Otherwise program is returned step 761 from step 765.
It is the code of P that step 771 is taken out exponent number.The step 772 of following after step 771 is carried out error-correction operation.The step 773 of step 772 back is preserved this message.The step 774 of following after step 773 determines whether the whole message of passing to about wireless message receiver is available.But when the whole message time spent of passing to relevant wireless message receiver, program enters step 775 from step 774.Otherwise program is returned step 761 from step 774.
Step 775 is closed sign.Follow step 776 after step 775 to the peripheral hardware output signal.After step 776, program enters step 770.
Step 851 among Figure 22 is closed sign.After step 851, program enters step 852.Step 852 determines whether " n " bit is available.As " n " but the bit time spent, program enters step 853 from step 852.Otherwise repeating step 852.
Step 853 determines whether sign is in opening.When sign was in opening, program entered step 854 from step 853.Otherwise program enters 855 from step 853.Step 854 determines whether the message of passing to relevant wireless message receiver is positioned at current block.When the message of passing to relevant wireless message receiver was positioned at current block, program entered step 855 from step 854.Otherwise program is returned step 852 from step 854.
Step 855 reads " n " individual bit.The step 856 of following after step 855 determines whether piece read.After piece was read, program entered step 857 from step 856.Otherwise program is returned step 852 from step 856.
Step 857 makes CPU 724 enter the high-speed cruising pattern.The step 858 of following after step 857 is carried out the release of an interleave processing.The step 859 of step 858 back is set at " 0 " with variable P.Variable P represents the exponent number of code word.After step 859, program enters step 860.Step 860 makes digital P increase 1.The step 861 that is connected on step 860 back determines whether 1 data processing is finished.When the data processing of piece 1 was finished, program entered to step 862 from step 861.Otherwise program enters step 863 from step 861.
Step 862 makes CPU 724 enter low-speed operation mode.After step 862, program is returned step 852.Step 863 determines whether sign closes.When sign was closed, program entered step 864 from step 863.Otherwise program enters step 865 from step 863.
It is the code of P that step 864 is taken out exponent number.The step 866 of following after step 864 determines whether the address is consistent.When the address was consistent with each other, program entered step 867 from step 866.Otherwise program enters step 868 from step 866.Step 866 is similar with the step 442 in 15 to Figure 14.Step 867 is opened sign.After step 867, program is returned step 860.
Step 868 determines whether to check all address informations.After all address informations all were examined, program entered step 869 from step 868.Otherwise program is returned step 860 from step 868.Step 869 makes the operation suspension of receiving unit.After step 869, program enters step 870.Step 870 makes CPU 724 be in low-speed operation mode.After step 870, finish the execution circulation of present procedure section.
Step 865 determines whether digital P equals to pass to the message code word of relevant wireless message receiver.When digital P equaled to pass to the message code word of relevant wireless message receiver, program entered step 871 from step 865.Otherwise program is returned step 860 from step 865.
It is the code of P that step 871 is taken out exponent number.The step 872 of following after step 871 is carried out error-correction operation.The step 873 of step 872 back is preserved this message.The step 874 of following after step 873 determines whether the whole message of passing to about wireless message receiver is available.But when the whole message time spent of passing to relevant wireless message receiver, program enters step 875 from step 874.Otherwise program is returned step 860 from step 874.
Step 875 is closed sign.Follow step 876 after step 875 to the peripheral hardware output signal.After step 876, finish the execution circulation of present procedure section.
The advantage of present embodiment is the message information that can regain one's integrity fast.This embodiment has following advantage.If the error rate is higher, then CPU can not move reducing the influence (noise) to receiving course to greatest extent at reception period, thereby obtains receiving sensitivity preferably.If the error rate is lower, then the data of Jie Shouing by the CPU sequential processes, and are only handled data necessary according to the information that structural analysis produced at reception period, thereby have shortened the processing time and reduced power consumption.Also having an advantage is to realize this two performances of mutually promoting.The advantage of this embodiment is similar to the 3rd embodiment's.
Claims (1)
1. message receiving system is characterized in that it comprises:
Radio paging signal is demodulated into first device of baseband signal;
Baseband signal is decoded as second device of corresponding data;
Alternately carry out the CPU of this data processing and other operations;
Produce first clock generator of first clock signal;
Produce the second clock generator of second clock signal, the frequency of first clock signal is higher than the frequency of second clock signal;
CPU responds the 3rd device of first clock enabling signal CPU action when carrying out described data processing;
Response second clock signal made the 4th device of CPU action when CPU carried out described other operation;
Be that unit is when CPU has the error correcting capability of α bit when staggered with m bits/words * n word wherein when data, CPU by first clock start signal receives α data unit, and this α data unit is being stored in buffer is handled m * n bit in the time interval data block.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97102293A CN1126378C (en) | 1997-01-17 | 1997-01-17 | Message receiver |
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| Application Number | Priority Date | Filing Date | Title |
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| CN97102293A CN1126378C (en) | 1997-01-17 | 1997-01-17 | Message receiver |
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| Publication Number | Publication Date |
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| CN1188380A CN1188380A (en) | 1998-07-22 |
| CN1126378C true CN1126378C (en) | 2003-10-29 |
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| CN97102293A Expired - Fee Related CN1126378C (en) | 1997-01-17 | 1997-01-17 | Message receiver |
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| CN103684655B (en) * | 2012-08-31 | 2017-03-15 | 展讯通信(天津)有限公司 | Decoding calibration equipment and method, code translator and method and receiving terminal |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142699A (en) * | 1988-07-15 | 1992-08-25 | Nec Corporation | Radio receiver with clock signal controlled to improve the signal to noise ratio |
| WO1994001841A1 (en) * | 1992-07-02 | 1994-01-20 | Motorola, Inc. | Power conservation method and apparatus for a data communication receiver |
| US5459456A (en) * | 1993-09-13 | 1995-10-17 | Motorola, Inc. | Method and apparatus for selectively forwarding messages received by a radio receiver to an external device |
| CN1139866A (en) * | 1994-12-02 | 1997-01-08 | 株式会社日立制作所 | Radio paging system |
-
1997
- 1997-01-17 CN CN97102293A patent/CN1126378C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142699A (en) * | 1988-07-15 | 1992-08-25 | Nec Corporation | Radio receiver with clock signal controlled to improve the signal to noise ratio |
| WO1994001841A1 (en) * | 1992-07-02 | 1994-01-20 | Motorola, Inc. | Power conservation method and apparatus for a data communication receiver |
| US5459456A (en) * | 1993-09-13 | 1995-10-17 | Motorola, Inc. | Method and apparatus for selectively forwarding messages received by a radio receiver to an external device |
| CN1139866A (en) * | 1994-12-02 | 1997-01-08 | 株式会社日立制作所 | Radio paging system |
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