CN112636861A - Clock synchronization method, device, equipment and storage medium - Google Patents
Clock synchronization method, device, equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a clock synchronization method, a clock synchronization device, clock synchronization equipment and a clock synchronization storage medium. The method comprises the following steps: determining a master node and a slave node in a link, controlling the master node and the slave node to carry out message transmission, and recording the message receiving and sending time of the message transmission; determining a target transmission delay value according to the message transmission time and by combining the interface rates of the master node and the slave node; and performing clock synchronization operation on the slave node based on the target transmission delay value. The invention solves the problem that the time of the master node and the slave node can not be accurately synchronized due to inaccurate calculated transmission delay values caused by different interface rates of the master node and the slave node, and realizes the effect that the time of each node in a clock synchronization network can be accurately synchronized.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a clock synchronization method, a clock synchronization device, clock synchronization equipment and a storage medium.
Background
In a traditional synchronous network, when synchronizing a GPS, one mode is that all equipment nodes are connected with the GPS, and the mode has high cost and great maintenance difficulty; another way is to use 1588 protocol, when the master node in the network is connected with GPS, the other nodes use 1588 protocol synchronization hop by hop.
By utilizing 1588 protocol synchronization time, when the interface rates of the master node and the slave node are the same, the two-way paths between the master node and the slave node are symmetrical, and the stamping time is symmetrical, so that the calculated transmission delay is more accurate; when the interface rates of the master node and the slave node are different, the bidirectional paths between the master node and the slave node are still symmetrical, but the stamping time is asymmetrical due to the fact that the master node and the slave node receive and transmit messages at different rates, so that the accuracy of calculating transmission delay is influenced, and the time of the master node and the time of the slave node cannot be accurately synchronized.
Disclosure of Invention
The invention provides a clock synchronization method, a clock synchronization device, clock synchronization equipment and a clock synchronization storage medium, which are used for realizing accurate synchronization of time of each node in a clock synchronization network.
In a first aspect, an embodiment of the present invention provides a clock synchronization method, including:
determining a master node and a slave node in a link, controlling the master node and the slave node to carry out message transmission, and recording the message receiving and sending time of the message transmission;
determining a target transmission delay value according to the message transmission time and by combining the interface rates of the master node and the slave node;
and performing clock synchronization operation on the slave node based on the target transmission delay value.
Optionally, the controlling the message transmission between the master node and the slave node, and recording the message transceiving time of the message transmission includes:
controlling the master node to send a synchronous message to the slave node, and recording the starting time of sending the synchronous message as a first timestamp;
after receiving the message header of the synchronous message, the slave node records a second timestamp;
controlling the slave node to send a delay request message to the master node, and recording the starting time of sending the delay request message as a third timestamp;
and the master node records a fourth time stamp after receiving the message header of the delay request message.
Optionally, the determining a target transmission delay value according to the packet transmission time and by combining the interface rates of the master node and the slave node includes:
determining alternative transmission delay values of the master node and the slave node according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp;
determining a delay correction value according to the master node interface rate of the master node and the slave node interface rate of the slave node;
and correcting the alternative transmission delay value based on the delay correction value to obtain a target transmission delay value.
Optionally, the determining the alternative transmission delay values of the master node and the slave node according to the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp includes:
subtracting the first time stamp from the second time stamp to obtain a first time difference;
subtracting the second timestamp from the fourth timestamp to obtain a second time difference;
determining an average of the first time difference and the second time as an alternative transmission delay value.
Optionally, the determining a delay correction value according to the master node interface rate of the master node and the slave node interface rate of the slave node includes:
determining a first stamping receiving and sending time according to the total length of the synchronous message and the head length of the synchronous message and by combining the interface rate of the master node and the interface rate of the slave node;
determining second stamping transceiving time according to the total length of the delay request message and the length of a delay request message header of the delay request message and by combining the interface rate of the master node and the interface rate of the slave node;
determining the difference value between the second stamping receiving and sending time and the first stamping receiving and sending time as a stamping deviation value;
and determining half of the stamping deviation value as a delay correction value.
Optionally, the determining, according to the total length of the synchronization packet and the header length of the synchronization packet, the first stamping transmit-receive time by combining the interface rate of the master node and the interface rate of the slave node, includes:
adding the ratio of the total length of the synchronous message to the interface rate of the master node to the ratio of the head length of the synchronous message to the interface rate of the slave node to obtain first stamping receiving and sending time;
correspondingly, the determining a second stamping transceiving time according to the total length of the delay request packet and the header length of the delay request packet in combination with the interface rate of the master node and the interface rate of the slave node includes:
and adding the ratio of the total length of the delay request message to the interface rate of the slave node to the ratio of the header length of the delay request message to the interface rate of the master node to obtain second stamping transceiving time.
Optionally, the master node interface rate is sent to the slave node by the master node through a declaration message.
In a second aspect, an embodiment of the present invention further provides a clock synchronization apparatus, where the apparatus includes:
the message receiving and sending time determining module is used for determining a main node and a slave node in a link, controlling the main node and the slave node to carry out message transmission and recording the message receiving and sending time of the message transmission;
a target transmission delay determining module, configured to determine a target transmission delay value according to the packet transmission time in combination with interface rates of the master node and the slave node;
and the clock synchronization module is used for carrying out clock synchronization operation on the slave nodes based on the target transmission delay value.
In a third aspect, an embodiment of the present invention further provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the clock synchronization method according to any embodiment of the present invention.
In a fourth aspect, embodiments of the present invention further provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are configured to perform a clock synchronization method according to any of the embodiments of the present invention.
The method and the device control the message transmission between the master node and the slave node by determining the master node and the slave node in the link, record the message receiving and sending time of the message transmission, determine a target transmission delay value by combining the master node interface rate of the master node and the slave node interface rate of the slave node according to the message transmission time, and perform clock synchronization operation on the slave node based on the target transmission delay value, thereby solving the problems that the calculated transmission delay values are inaccurate and the time of the master node and the slave node cannot be accurately synchronized due to different interface rates of the master node and the slave node, and realizing the effect that the time of each node in the clock synchronization network can be accurately synchronized.
Drawings
Fig. 1 is a flowchart of a clock synchronization method according to an embodiment of the present invention;
fig. 2 is a flowchart of a clock synchronization method according to a second embodiment of the present invention;
fig. 3 is a block diagram of a clock synchronization apparatus according to a third embodiment of the present invention;
fig. 4 is a block diagram of a computer device according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only a part of the structures related to the present invention, not all of the structures, are shown in the drawings, and furthermore, embodiments of the present invention and features of the embodiments may be combined with each other without conflict.
Example one
Fig. 1 is a flowchart of a clock synchronization method according to an embodiment of the present invention, where the embodiment is applicable to a case where time of each node in a clock synchronization network is precisely synchronized, and the method may be executed by a clock synchronization apparatus, and the apparatus may be implemented by software and/or hardware.
The technical scheme provided by the embodiment of the invention is mainly based on a 1588 protocol to carry out clock synchronization operation.
As shown in fig. 1, the method specifically includes the following steps:
and step 110, determining a master node and a slave node in a link, controlling the master node and the slave node to perform message transmission, and recording the message receiving and sending time of the message transmission.
In this embodiment, before performing clock synchronization operation, clocks of each node in the clock synchronization network may have a deviation, and when performing clock synchronization operation, two nodes may perform transmission and reception of time synchronization information, and record corresponding timestamps, thereby calculating a delay and a time offset of a transmission and reception packet between the two nodes, and correcting a clock of one node to achieve synchronization with a clock of the other node, where a node that transmits time synchronization information may be referred to as a master node, and a node that needs to correct a clock may be referred to as a slave node. In a clock synchronization network, there may be a master node and several slave nodes, and a path space for signals to propagate between a master node and a slave node may be referred to as a link.
Specifically, when performing clock synchronization operation, a master node and a slave node in a synchronization network may be determined first, where there is only one master node and there may be a plurality of slave nodes. The master node may send a clock-synchronized message to the slave nodes, and after receiving the message, the slave nodes may return a delay-requested message to the master node, and the time for receiving and transmitting the two messages may be recorded by the corresponding nodes. After receiving the message of the delay request sent by the slave node, the master node may write the time of receiving the message into a response message and return the response message to the slave node.
And step 120, determining a target transmission delay value according to the message transmission time and by combining the interface rates of the master node and the slave node.
In this embodiment, the interface rates of the master node and the slave node may be different. The interface rate of the node may be 10M, 100M, 1G, 10G, or the like. For example, the interface rate of the master node is 1G, and the interface rate of the slave node is 100M.
Specifically, when the interface rates of the master node and the slave node are different, the time used by the master node and the slave node to send and receive the packet is also different, that is, the time used by the master node and the slave node to timestamp and read the timestamp is also different, so that the transmission delay value calculated according to the packet transmission time is inaccurate, and the clock correction of the slave node is inaccurate. Therefore, the interface rates of the master node and the slave node can be respectively obtained, and the calculated transmission delay value is adjusted according to the two interface rate values to obtain an accurate target transmission delay value.
And step 130, performing clock synchronization operation on the slave nodes based on the target transmission delay value.
Specifically, after a target transmission delay value between the master node and the slave node is obtained, clock synchronization operation can be performed on the slave node according to the target transmission delay value, so that time offset existing between the slave node and the master node is eliminated.
According to the technical scheme of the embodiment, the master node and the slave node in the link are determined, message transmission between the master node and the slave node is controlled, the message receiving and sending time of the message transmission is recorded, the target transmission delay value is determined according to the message transmission time by combining the interface rates of the master node and the slave node, and the slave node is subjected to clock synchronization operation based on the target transmission delay value, so that the problems that the calculated transmission delay values are inaccurate and the time of the master node and the slave node cannot be accurately synchronized due to different interface rates of the master node and the slave node are solved, and the effect that the time of each node in a clock synchronization network can be accurately synchronized is achieved.
Example two
Fig. 2 is a flowchart of a clock synchronization method according to a second embodiment of the present invention. On the basis of the above embodiments, the present embodiment further optimizes the clock synchronization method.
As shown in fig. 2, the method specifically includes:
and step 210, determining a master node and a slave node in the link.
And step 220, controlling the master node to send the synchronous message to the slave node, and recording the starting time of sending the synchronous message as a first timestamp.
Specifically, the master node may send a synchronization packet to the slave node after finishing the timestamp marking, and record the timestamp marked by the master node as the first timestamp.
Specifically, the slave node may stamp a time stamp after receiving a packet header of the synchronization packet sent by the master node, and record the time stamp as the second time stamp.
And step 240, controlling the slave node to send the delay request message to the master node, and recording the starting time of sending the delay request message as a third timestamp.
Specifically, after receiving the synchronization packet sent by the master node, the slave node may send a delay request packet to the master node after completing the timestamp marking, and record the timestamp printed by the slave node this time as a third timestamp.
And step 250, after receiving the message header of the delay request message, the master node records a fourth time stamp.
Specifically, the master node may stamp a timestamp after receiving a packet header of the delay request packet sent by the slave node, and record the timestamp as a fourth timestamp.
And step 260, determining alternative transmission delay values of the master node and the slave node according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp.
Specifically, it may be assumed that the interface rates of the master node and the slave node are consistent, the transmission delay between the master node and the slave node is calculated according to the first time stamp, the second time stamp, the third time stamp, and the fourth time stamp, and the transmission delay value is used as the alternative transmission delay value.
Optionally, step 260 may be implemented by: subtracting the first time stamp from the second time stamp to obtain a first time difference; subtracting the second time stamp from the fourth time stamp to obtain a second time difference; an average of the first time difference and the second time is determined as the alternative transmission delay value.
Specifically, the second time stamp minus the first time stamp may be considered as a synchronization packet transmission time interval considered from the node, the fourth time stamp minus the second time stamp may be considered as a delay request packet transmission time interval considered from the master node, and an average value of the two time intervals is taken as an alternative transmission delay value.
And 270, determining a delay correction value according to the master node interface rate of the master node and the slave node interface rate of the slave node.
Specifically, the difference between the transmission times of two packets caused by the difference between the interface rates of the two nodes can be calculated according to the interface rate of the master node and the interface rate of the slave node, and the difference is recorded as a delay correction value.
Optionally, step 270 may be implemented by: determining first stamping receiving and sending time according to the total length of the synchronous message and the head length of the synchronous message and by combining the interface rate of the master node and the interface rate of the slave node; determining second stamping receiving and sending time according to the total length of the delay request message and the length of the head of the delay request message and by combining the interface rate of the master node and the interface rate of the slave node; determining the difference value between the second stamping receiving and sending time and the first stamping receiving and sending time as a stamping deviation value; and determining half of the stamping deviation value as a delay correction value.
Further, the ratio of the total length of the synchronization message to the interface rate of the master node can be added to the ratio of the header length of the synchronization message to the interface rate of the slave node to obtain the first stamping transceiving time; the ratio of the total length of the delay request packet to the interface rate of the slave node may be added to the ratio of the header length of the delay request packet to the interface rate of the master node to obtain the second stamping transmit-receive time.
Optionally, the master node interface rate may be sent to the slave node by the master node via a declaration message.
And step 280, correcting the alternative transmission delay value based on the delay correction value to obtain a target transmission delay value.
Specifically, the alternative transmission delay value is a transmission delay value calculated under the condition that the interface rates of the master node and the slave node are assumed to be consistent, and the delay correction value is a difference value between the transmission times of the two messages caused by different actual interface rates of the master node and the slave node, so that the alternative transmission delay value can be adjusted according to the delay correction value to obtain an accurate target transmission delay value.
Illustratively, the Master node may be denoted as Master, the slave node may be denoted as slave, the interface rate of the Master is 1G, and the interface rate of the slave is 100M, so as to perform Ethernet networking. The master sends a sync message sync at a rate of 1G, the length of the sync message is 62 bytes, the master sends the sync message after printing a timestamp T1, the slave receives the sync message at a rate of 100M, and after receiving the message header of the sync message, the slave prints a timestamp T2, and the length of the sync message header is 8 bytes. And then after the slave marks the timestamp T3, the slave sends a delay request message del-request at a rate of 100M, the length of the del-request message is 62 bytes, the master receives the message at a rate of 1G, and after the message header 8Byte of the del-request message is received, the slave marks the timestamp T4. At this time, the alternative transmission delay values may be calculated as:
ReserveDelay＝(T2-T1+T4-T3)/2；
between T1 and T2, the first stamping transceiving time for Master sending message and Slave receiving message is:
MSTxTime＝62*8/(1E9)+8*8/(1E8)；
between T3 and T4, the second stamping transceiving time for the Slave to send the message and the Master to receive the message is:
SMTxTime＝62*8/(1E8)+8*8/(1E9)；
thus, a stamping bias value can be calculated as:
AsymmetryDealy＝SMTxTime–MSTxTime＝3.888us；
the delay correction value is as follows:
AsymmetryOffset＝AsymmetryDealy/2＝1.944us；
therefore, when the master uses the 1G interface and the slave uses the 100M interface, since the asymmetric delay generated by the time stamping is 3.888us, the value of the delay to be compensated by the slave is 1.944 us. Assuming that the mterfacerate variable represents the interface rate of the master, and the smterfacerate variable represents the interface rate of the slave, the delay correction value AsymmetryOffset can be expressed as:
AsymmetryOffset＝432/sInterfaceRate–432/mInterfaceRate；
that is, if the sInterfaceRate is equal to the mInterfaceRate, AsymmetryOffset is 0, and if the sInterfaceRate is not equal to the mInterfaceRate, AsymmetryOffset needs to be compensated into the delay value of the slave, then the target transmission delay value of the slave may be:
Delay＝ReserveDelay-AsymmetryOffset。
because the 1588 protocol is transmitted through a network, the master and the slave devices are generally distributed in different regions and maintained by different personnel, so if the master can inform the slave of the interface rate of the master through the Announce message, the slave can automatically calculate the delay correction value AsymmetryOffset through the method and automatically compensate the delay correction value AsymmetryOffset into the delay value of the slave.
The Announce message header format can be as shown in Table 1, the flagField can be as shown in Table 2, the 3 rd bit with the octet of the flagField being 0 can be used for identifying the function of carrying the master interface rate, meanwhile, the device is added with a master interface rate configuration item to allow external configuration, and the reserved field with the Offset being 5 in the Announce message header is used for carrying the master interface rate, as shown in tables 3 and 4. Table 5 is an enumeration definition of master interface rate, and in order to save message field overhead, an enumeration value is used to represent different master interface rates.
Table 1 Announce header format
Table 2 FlagField format definition
TABLE 3 Master interface Rate definitions
| Octets | Offset | |
| Reserved (master interface rate enumeration value) | 1 | 5 |
TABLE 4 Master interface Rate flag definition
TABLE 5 Master interface Rate enumeration Definitions
| Enumerated value | Master interface rate |
| 1 | 10M |
| 2 | 100M |
| 3 | 1G |
| 4 | 1G |
| 5 | Reserved |
According to the technical scheme of the embodiment, the master node and the slave node in the link are determined, the master node is controlled to send the synchronous message to the slave node, the starting time of sending the synchronous message is recorded as a first time stamp, and a second time stamp is recorded after the slave node receives the message header of the synchronous message; the slave node is controlled to send a delay request message to the master node, the starting time of sending the delay request message is recorded as a third timestamp, and a fourth timestamp is recorded after the master node receives a message header of the delay request message; according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp, alternative transmission delay values of the master node and the slave nodes are determined, a delay correction value is determined according to the master node interface rate of the master node and the slave node interface rate of the slave nodes, the alternative transmission delay values are corrected based on the delay correction value, and a target transmission delay value is obtained, so that clock synchronization operation is performed on the slave nodes, the problems that the calculated transmission delay values are inaccurate and the time of the master node and the slave node cannot be accurately synchronized due to different interface rates of the master node and the slave node are solved, and the effect that the time of each node in a clock synchronization network can be accurately synchronized is achieved.
EXAMPLE III
The clock synchronization device provided by the embodiment of the invention can execute the clock synchronization method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method. Fig. 3 is a block diagram of a clock synchronization apparatus according to a third embodiment of the present invention, and as shown in fig. 3, the apparatus includes: a messaging time determination module 310, a target transmission delay determination module 320, and a clock synchronization module 330.
A message transceiving time determining module 310, configured to determine a master node and a slave node in a link, control the master node and the slave node to perform message transmission, and record message transceiving time of the message transmission;
a target transmission delay determining module 320, configured to determine a target transmission delay value according to the packet transmission time and by combining interface rates of the master node and the slave node;
a clock synchronization module 330, configured to perform a clock synchronization operation on the slave node based on the target transmission delay value.
According to the technical scheme of the embodiment, the master node and the slave node in the link are determined, message transmission between the master node and the slave node is controlled, the message receiving and sending time of the message transmission is recorded, the target transmission delay value is determined according to the message transmission time by combining the interface rates of the master node and the slave node, and the slave node is subjected to clock synchronization operation based on the target transmission delay value, so that the problems that the calculated transmission delay values are inaccurate and the time of the master node and the slave node cannot be accurately synchronized due to different interface rates of the master node and the slave node are solved, and the effect that the time of each node in a clock synchronization network can be accurately synchronized is achieved.
Optionally, the message transceiving time determining module is specifically configured to include:
controlling the master node to send a synchronous message to the slave node, and recording the starting time of sending the synchronous message as a first timestamp;
after receiving the message header of the synchronous message, the slave node records a second timestamp;
controlling the slave node to send a delay request message to the master node, and recording the starting time of sending the delay request message as a third timestamp;
and the master node records a fourth time stamp after receiving the message header of the delay request message.
Optionally, the target transmission delay determining module 320 includes:
an alternative transmission delay determining unit, configured to determine alternative transmission delay values of the master node and the slave node according to the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp;
the delay correction determining unit is used for determining a delay correction value according to the master node interface rate of the master node and the slave node interface rate of the slave node;
and the target transmission delay determining unit is used for correcting the alternative transmission delay value based on the delay correction value to obtain a target transmission delay value.
Optionally, the alternative transmission delay determining unit is specifically configured to:
subtracting the first time stamp from the second time stamp to obtain a first time difference;
subtracting the second timestamp from the fourth timestamp to obtain a second time difference;
determining an average of the first time difference and the second time as an alternative transmission delay value.
Optionally, the delay correction determining unit is specifically configured to:
determining a first stamping receiving and sending time according to the total length of the synchronous message and the head length of the synchronous message and by combining the interface rate of the master node and the interface rate of the slave node;
determining second stamping transceiving time according to the total length of the delay request message and the length of a delay request message header of the delay request message and by combining the interface rate of the master node and the interface rate of the slave node;
determining the difference value between the second stamping receiving and sending time and the first stamping receiving and sending time as a stamping deviation value;
and determining half of the stamping deviation value as a delay correction value.
Optionally, the determining, according to the total length of the synchronization packet and the header length of the synchronization packet, the first stamping transmit-receive time by combining the interface rate of the master node and the interface rate of the slave node, includes:
adding the ratio of the total length of the synchronous message to the interface rate of the master node to the ratio of the head length of the synchronous message to the interface rate of the slave node to obtain first stamping receiving and sending time;
correspondingly, the determining a second stamping transceiving time according to the total length of the delay request packet and the header length of the delay request packet in combination with the interface rate of the master node and the interface rate of the slave node includes:
and adding the ratio of the total length of the delay request message to the interface rate of the slave node to the ratio of the header length of the delay request message to the interface rate of the master node to obtain second stamping transceiving time.
Optionally, the master node interface rate is sent to the slave node by the master node through a declaration message.
According to the technical scheme of the embodiment, the master node and the slave node in the link are determined, the master node is controlled to send the synchronous message to the slave node, the starting time of sending the synchronous message is recorded as a first time stamp, and a second time stamp is recorded after the slave node receives the message header of the synchronous message; the slave node is controlled to send a delay request message to the master node, the starting time of sending the delay request message is recorded as a third timestamp, and a fourth timestamp is recorded after the master node receives a message header of the delay request message; according to the first time stamp, the second time stamp, the third time stamp and the fourth time stamp, alternative transmission delay values of the master node and the slave nodes are determined, a delay correction value is determined according to the master node interface rate of the master node and the slave node interface rate of the slave nodes, the alternative transmission delay values are corrected based on the delay correction value, and a target transmission delay value is obtained, so that clock synchronization operation is performed on the slave nodes, the problems that the calculated transmission delay values are inaccurate and the time of the master node and the slave node cannot be accurately synchronized due to different interface rates of the master node and the slave node are solved, and the effect that the time of each node in a clock synchronization network can be accurately synchronized is achieved.
Example four
Fig. 4 is a block diagram of a computer apparatus according to a fourth embodiment of the present invention, as shown in fig. 4, the computer apparatus includes a processor 410, a memory 420, an input device 430, and an output device 440; the number of the processors 410 in the computer device may be one or more, and one processor 410 is taken as an example in fig. 4; the processor 410, the memory 420, the input device 430 and the output device 440 in the computer apparatus may be connected by a bus or other means, and the connection by the bus is exemplified in fig. 4.
The memory 420 serves as a computer-readable storage medium for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the clock synchronization method in the embodiments of the present invention (e.g., the messaging time determination module 310, the target transmission delay determination module 320, and the clock synchronization module 330 in the clock synchronization apparatus). The processor 410 executes various functional applications of the computer device and data processing by executing software programs, instructions, and modules stored in the memory 420, that is, the clock synchronization method described above is implemented.
The memory 420 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, memory 420 may further include memory located remotely from processor 410, which may be connected to a computer device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 430 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus. The output device 440 may include a display device such as a display screen.
EXAMPLE five
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a clock synchronization method, the method including:
determining a master node and a slave node in a link, controlling the master node and the slave node to carry out message transmission, and recording the message receiving and sending time of the message transmission;
determining a target transmission delay value according to the message transmission time and by combining the interface rates of the master node and the slave node;
and performing clock synchronization operation on the slave node based on the target transmission delay value.
Of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the operations of the method described above, and may also perform related operations in the clock synchronization method provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the clock synchronization apparatus, each unit and each module included in the embodiment are only divided according to functional logic, but are not limited to the above division as long as the corresponding function can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method of clock synchronization, comprising:
determining a master node and a slave node in a link, controlling the master node and the slave node to carry out message transmission, and recording the message receiving and sending time of the message transmission;
determining a target transmission delay value according to the message transmission time and by combining the interface rates of the master node and the slave node;
and performing clock synchronization operation on the slave node based on the target transmission delay value.
2. The clock synchronization method according to claim 1, wherein the controlling the message transmission between the master node and the slave node and recording the message transceiving time of the message transmission comprises:
controlling the master node to send a synchronous message to the slave node, and recording the starting time of sending the synchronous message as a first timestamp;
after receiving the message header of the synchronous message, the slave node records a second timestamp;
controlling the slave node to send a delay request message to the master node, and recording the starting time of sending the delay request message as a third timestamp;
and the master node records a fourth time stamp after receiving the message header of the delay request message.
3. The clock synchronization method according to claim 2, wherein the determining a target transmission delay value according to the packet transmission time and in combination with the interface rates of the master node and the slave node comprises:
determining alternative transmission delay values of the master node and the slave node according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp;
determining a delay correction value according to the master node interface rate of the master node and the slave node interface rate of the slave node;
and correcting the alternative transmission delay value based on the delay correction value to obtain a target transmission delay value.
4. The clock synchronization method of claim 3, wherein determining alternative transmission delay values for the master node and the slave node based on the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp comprises:
subtracting the first time stamp from the second time stamp to obtain a first time difference;
subtracting the second timestamp from the fourth timestamp to obtain a second time difference;
determining an average of the first time difference and the second time as an alternative transmission delay value.
5. The clock synchronization method of claim 3, wherein determining the delay correction value based on the master node interface rate of the master node and the slave node interface rate of the slave node comprises:
determining a first stamping receiving and sending time according to the total length of the synchronous message and the head length of the synchronous message and by combining the interface rate of the master node and the interface rate of the slave node;
determining second stamping transceiving time according to the total length of the delay request message and the length of a delay request message header of the delay request message and by combining the interface rate of the master node and the interface rate of the slave node;
determining the difference value between the second stamping receiving and sending time and the first stamping receiving and sending time as a stamping deviation value;
and determining half of the stamping deviation value as a delay correction value.
6. The clock synchronization method according to claim 5, wherein the determining a first stamping transmit-receive time according to the total length of the synchronization packet and the header length of the synchronization packet in combination with the interface rate of the master node and the interface rate of the slave node comprises:
adding the ratio of the total length of the synchronous message to the interface rate of the master node to the ratio of the head length of the synchronous message to the interface rate of the slave node to obtain first stamping receiving and sending time;
correspondingly, the determining a second stamping transceiving time according to the total length of the delay request packet and the header length of the delay request packet in combination with the interface rate of the master node and the interface rate of the slave node includes:
and adding the ratio of the total length of the delay request message to the interface rate of the slave node to the ratio of the header length of the delay request message to the interface rate of the master node to obtain second stamping transceiving time.
7. The clock synchronization method of claim 3, wherein the master node interface rate is sent by the master node to the slave node via an assertion message.
8. A clock synchronization apparatus, comprising:
the message receiving and sending time determining module is used for determining a main node and a slave node in a link, controlling the main node and the slave node to carry out message transmission and recording the message receiving and sending time of the message transmission;
a target transmission delay determining module, configured to determine a target transmission delay value according to the packet transmission time in combination with interface rates of the master node and the slave node;
and the clock synchronization module is used for carrying out clock synchronization operation on the slave nodes based on the target transmission delay value.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the clock synchronization method according to any of claims 1-7 when executing the program.
10. A storage medium containing computer-executable instructions for performing the clock synchronization method of any one of claims 1-7 when executed by a computer processor.
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