CN112636753B - Digital-to-analog converter - Google Patents
Digital-to-analog converter Download PDFInfo
- Publication number
- CN112636753B CN112636753B CN202011486714.XA CN202011486714A CN112636753B CN 112636753 B CN112636753 B CN 112636753B CN 202011486714 A CN202011486714 A CN 202011486714A CN 112636753 B CN112636753 B CN 112636753B
- Authority
- CN
- China
- Prior art keywords
- resistor
- layer
- metal
- electrically connected
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 220
- 239000002184 metal Substances 0.000 claims abstract description 220
- 238000009826 distribution Methods 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229920005994 diacetyl cellulose Polymers 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 241000033695 Sige Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The embodiment of the invention discloses a digital-to-analog converter. The digital-to-analog converter comprises a resistor string comprising 2 N Strings ofThe metal resistor is connected, one end of the resistor string is electrically connected with the reference voltage end, and the other end of the resistor string is connected with the grounding end; wherein N is an integer greater than or equal to 1; the switch module is electrically connected with the resistor string and the decoding module respectively; the decoding module is used for responding to the externally input digital signal and outputting a switch control signal; the switch module is used for responding to the switch control signal and outputting an analog signal matched with the digital signal. The technical scheme provided by the embodiment of the invention can reduce the thermal noise of the digital-to-analog converter.
Description
Technical Field
The embodiment of the invention relates to the technical field of circuits, in particular to a digital-to-analog converter.
Background
Digital-to-analog converters (Digital to Analog Converter, DACs) are used to convert digital quantities into analog quantities and are widely used in electronic devices.
At present, the temperature and the process performance of the polysilicon resistor are better than those of other types of resistors, so that the resistor of the traditional voltage division type DAC usually adopts the polysilicon resistor, but the square resistance value of the polysilicon resistor is larger, and the power spectrum density of the thermal noise of the resistor is in direct proportion to the resistance value, so that the noise of the DAC adopting the polysilicon resistor as the voltage division resistor is quite large.
Disclosure of Invention
The invention provides a digital-to-analog converter, which is used for reducing the thermal noise of the digital-to-analog converter.
In a first aspect, an embodiment of the present invention provides a digital-to-analog converter, including:
a resistor string comprising 2 N The series metal resistors are connected in series, one end of the resistor string is electrically connected with a reference voltage end, and the other end of the resistor string is connected with a grounding end; wherein N is an integer greater than or equal to 1;
the switch module is electrically connected with the resistor string and the decoding module respectively; the decoding module is used for responding to an externally input digital signal and outputting a switch control signal; the switch module is used for responding to the switch control signal and outputting an analog signal matched with the digital signal.
Optionally, the first end of the 1 st metal resistor is connected with the reference voltage end;
the first end of the ith metal resistor is connected with the second end of the (i-1) th metal resistor, and the second end of the ith metal resistor is connected with the first end of the (i+1) th metal resistor; wherein i is an integer, and i is more than or equal to 2 and less than or equal to 2 N -1, n is an integer greater than or equal to 2;
2 nd N The second end of each metal resistor is grounded.
Optionally, the resistance value of each metal resistor is the same.
Optionally, the width of the metal resistor ranges from 0.05um to 2um, and the length of the metal resistor ranges from 0.3um to 4um.
Alternatively, 2 N The metal resistors comprise a first metal resistor extending along the Y direction and a second metal resistor extending along the X direction;
the first metal resistor defines a plurality of first resistor strips, and the first resistor strips are arranged in parallel along the X direction; the second metal resistor defines a plurality of second resistor bars, and the plurality of second resistor bars are arranged along the X direction; the first resistor strips and the second resistor strips are alternately connected.
Optionally, the second resistor strips only comprise one second metal resistor, and two adjacent first resistor strips are connected end to end through the second resistor strips; all the metal resistor distribution areas are rectangular, and the reference voltage end and the grounding end are arranged at two opposite ends of the rectangle or two ends of the same side.
Optionally, the dimensions of each of the metal resistors are the same.
Optionally, the second resistor bar includes only one second metal resistor, and the second resistor bar is divided into a first second resistor bar and a second resistor bar according to the length of the second resistor bar along the X direction, and the size of the first second resistor bar is smaller than that of the second resistor bar;
The (1+4n) th first resistor bar is connected with the (4+4n) th first resistor bar through the second type second resistor bar, and the (2+4n) th first resistor bar is connected with the (3+4n) th first resistor bar through the first type second resistor bar;
the (3+4n) th first resistor bar is connected with the (6+4n) th first resistor bar through the second type second resistor bar, and the (4+4n) th first resistor bar is connected with the (5+4n) th first resistor bar through the first type second resistor bar; wherein n is an integer of 0 or more;
all the metal resistor distribution areas are rectangular, and the reference voltage end and the grounding end are arranged at the same end of the rectangle.
Optionally, the switch module comprises 2 N A plurality of first layer switching transistors and a plurality of second layer switching transistors; the decoding module comprises a first decoder and a second decoder;
a first end of the j-th layer of switching transistor is electrically connected with a second end of the j-th layer of metal resistor, and a control end of the first layer of switching transistor is electrically connected with the first decoder; wherein j is an integer, and j is more than or equal to 1 and less than or equal to 2 N ；
The second end of the first layer of switching transistors electrically connected with the same first resistor strip is electrically connected with the first end of the same second layer of switching transistors, and the control end of the second layer of switching transistors is electrically connected with the second decoder.
Optionally, all the metal resistor distribution areas are rectangular;
the first layer of switching transistors are positioned in the rectangle, the first layer of switching transistors define a plurality of switching tube columns, the switching tube columns are arranged in parallel along the X direction, and the switching tube columns are positioned on one side of the first resistor strip which is electrically connected with the switching tube columns;
the second layer of switching transistors is positioned on one side of the rectangle extending along the X direction;
the first decoder is positioned on one side of a side extending along the Y direction in the rectangle;
the second decoder is positioned on one side of the second layer of switching transistors, which is away from the rectangle.
Alternatively, 2 N Each of the goldThe metal resistor comprises a first metal resistor extending along the Y direction, a second metal resistor extending along the X direction and a third metal resistor extending along the Y direction;
the intersection point of the X axis along the X direction and the Y axis along the Y direction is used as an origin, and all the metal resistor distribution areas are rectangular, and the rectangular covers four quadrants;
in each quadrant, the first metal resistor defines a plurality of first resistor bars, and the plurality of first resistor bars are arranged in parallel along the Y direction; the second metal resistor defines a plurality of second resistor strips, the plurality of second resistor strips are arranged along the X direction, the third metal resistor defines two third resistor strips, and the plurality of third resistor strips are arranged along the X direction; the first resistor strips and the second resistor strips are alternately connected;
A first resistor bar positioned in the fourth quadrant is connected with a first resistor bar positioned in the first quadrant through one third resistor bar, and a first resistor bar positioned in the second quadrant is connected with a first resistor bar positioned in the third quadrant through the other third resistor bar.
Optionally, the switch module comprises 2 N A plurality of first layer switching transistors, a plurality of second layer switching transistors, and a plurality of third layer switching transistors; the decoding module comprises a first decoder, a second decoder, a third decoder and a fourth decoder;
a first end of the j-th layer of switching transistor is electrically connected with a second end of the j-th layer of metal resistor, and a control end of the first layer of switching transistor is electrically connected with the first decoding; wherein j is an integer, and j is more than or equal to 1 and less than or equal to 2 N ；
In each quadrant, the second end of the first layer of open-transistor electrically connected with the same first resistor strip is electrically connected with the first end of the same second layer of switch transistor; the control end of the second-layer switching transistor which is electrically connected with the metal resistor positioned in the first quadrant and the second quadrant through the first-layer switching transistor is electrically connected with the second decoder; the control end of the second-layer switching transistor which is electrically connected with the metal resistor positioned in the third quadrant and the fourth quadrant through the first-layer switching transistor is electrically connected with the third decoder; a second end of the second layer of switching transistors electrically connected with the metal resistor in the same quadrant through the first layer of switching transistors is electrically connected with a first end of the same third layer of switching transistors;
And the control end of the third-layer switching transistor is electrically connected with the fourth decoder.
Optionally, the first layer of switching transistors is located in the rectangle, and in each quadrant, the first layer of switching transistors defines a plurality of switching transistor columns, the plurality of switching transistor columns are arranged in parallel along the X direction, and the switching transistor columns are located on one side of the first resistor strip to which the switching transistor columns are electrically connected;
the first decoder is positioned on one side of a side extending along the Y direction in the rectangle;
the second decoder and the second layer switching transistor electrically connected thereto are located at one side of a side of the rectangle extending in the X direction and are close to the first quadrant and the second quadrant;
the third decoder and the second layer switching transistor electrically connected thereto are located at one side of a side of the rectangle extending in the X direction and are close to the third quadrant and the fourth quadrant;
the fourth decoder is positioned on one side of the first decoder facing away from the rectangle.
Optionally, each two adjacent first-layer switching transistors form a switching transistor group along the Y direction, second ends of two first-layer switching transistors in the same switching transistor group are connected, and a first end of each first-layer switching transistor is flush with a second end of the metal resistor electrically connected with the first-layer switching transistor.
Optionally, the material of the metal resistor comprises aluminum.
The digital-to-analog converter provided by the embodiment of the invention comprises the resistor string, the switch module and the decoding module, wherein the resistor string is composed of the metal resistor, and the thermal noise of the resistor string is smaller due to the smaller square resistance value of the metal resistor. Compared with the polysilicon resistor formed by multiple film layers, the metal resistor can be formed by at least one metal film layer, namely the film layer of the metal resistor has a simple structure; and the minimum width of the metal resistor is far smaller than the minimum width of the polysilicon resistor, i.e. the layout area can be greatly reduced. Therefore, the embodiment of the invention solves the problem of large thermal noise of the digital-to-analog converter, realizes the effect of reducing the thermal noise of the digital-to-analog converter, simplifies the structure of the digital-to-analog converter and reduces the layout area of the DAC.
Drawings
Fig. 1 is a schematic diagram of a digital-to-analog converter according to an embodiment of the present invention;
fig. 2 is a circuit element diagram of a digital-to-analog converter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an arrangement of the digital-to-analog converter shown in FIG. 2 according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another arrangement of the digital-to-analog converter shown in FIG. 2 according to an embodiment of the present invention;
FIG. 5 is a circuit element diagram of another digital-to-analog converter provided by an embodiment of the present invention;
fig. 6 is a schematic diagram of an arrangement of the digital-to-analog converter shown in fig. 5 according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
In view of the problems mentioned in the background, an embodiment of the present invention provides a digital-to-analog converter, including:
resistor string, resistor string includes 2 N The series metal resistors are connected in series, one end of the resistor string is electrically connected with the reference voltage end, and the other end of the resistor string is connected with the grounding end; wherein N is greater thanAn integer equal to 1;
the switch module is electrically connected with the resistor string and the decoding module respectively; the decoding module is used for responding to the externally input digital signal and outputting a switch control signal; the switch module is used for responding to the switch control signal and outputting an analog signal matched with the digital signal.
The foregoing is the core idea of the present application, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present invention. Referring to fig. 1, the digital-to-analog converter includes: resistor string 10, resistor string 10 comprising 2 N The series metal resistors R are connected in series, one end of the resistor string 10 is electrically connected with the reference voltage end Vref, and the other end of the resistor string 10 is connected with the grounding end GND; wherein N represents the bit number of the digital-to-analog converter and is an integer greater than or equal to 1; the switch module 20 and the decoding module 30, the switch module 20 is electrically connected with the resistor string 10 and the decoding module 30 respectively; the decoding module 30 is used for responding to the externally input digital signal and outputting a switch control signal; the switching module 20 is used for outputting an analog signal matched with the digital signal in response to the switching control signal.
Specifically, the specific value of N and the voltage value U of the reference voltage terminal Vref can be set by those skilled in the art according to practical situations, and are not limited herein. Illustratively, n=16 is shown in fig. 1, i.e., resistor string 10 includes 65536 metal resistors R, denoted R1-R65536, respectively, such that the digital-to-analog converter has a precision of U/65536.
Specifically, the metal resistor R refers to a parasitic resistor formed by a metal material, in other words, the metal resistor R is a parasitic resistor of a metal line in the layout design process. The material of the metal resistor R may be selected by those skilled in the art according to the actual situation, and is not limited herein, alternatively, the square resistance of the metal resistor R is in milliohm level, and exemplary, the metal resistor R may be selected from aluminum, and the square resistance is 78mΩ/≡.
It will be appreciated that the parasitic resistance of the metal lines is typically small, so that the noise of the digital to analogue converter can be made small when the metal resistor R (i.e. the metal lines) is arranged to form the resistor string 10.
Specifically, the size of the metal resistor R can be set by those skilled in the art according to the actual situation, and is not limited herein. It can be understood that the smaller the size of the metal resistor R, the smaller the resistance value, so that the width of the metal resistor R can be selected to be the minimum width which can be achieved in the actual preparation process, and the length of the metal resistor R can be reasonably designed according to the layout distribution among all devices in the digital-to-analog converter. Optionally, the width of the metal resistor R ranges from 0.05um to 2um, and the length of the metal resistor R ranges from 0.3um to 4um. Therefore, the metal resistor R can be ensured to have a smaller resistance value, and the thermal noise of the digital-to-analog converter is greatly reduced.
Specifically, the metal resistors R in the resistor string 10 may be located in the same metal film layer, or may be located in different metal film layers, which is not limited herein. Preferably, each metal resistor R is located in the same metal film layer, so that each metal resistor R can be formed by the same manufacturing process, so that the process of the resistor string 10 is simple. The resistor string 10 may be located in a metal film layer separately provided, or may be located in the same film layer as other devices in the digital-to-analog converter, which is not limited herein. Preferably, each metal resistor R is located in the same metal film layer and is not located in the same film layer as other devices, so that the arrangement of the metal resistor R does not influence wiring among other devices, and the design difficulty of wiring among devices in the digital-to-analog converter is reduced.
It will be appreciated that in a practical manufacturing process, a polysilicon resistor is typically formed by stacking a plurality of layers, while a metal resistor R may be formed by at least one metal layer, which is advantageous for simplifying the layer structure of the digital-to-analog converter. In addition, the minimum width that the metal resistor R can reach under the current technology is far less than the minimum width of the polycrystalline silicon resistor, so the layout area of the resistor string 10 can be greatly reduced, and the film structure of the digital-to-analog converter is simplified, and the reduction of the layout area is beneficial to the reduction of the current sheet cost.
Specifically, the connection manner of each metal resistor R in the resistor string 10 can be set by those skilled in the art according to the actual situation, which is not limited herein. Optionally, with continued reference to fig. 1, a first terminal of the 1 st metal resistor R is connected to the reference voltage terminal Vref; the first end of the ith metal resistor R is connected with the second end of the (i-1) th metal resistor R, and the second end of the ith metal resistor R is connected with the first end of the (i+1) th metal resistor R; wherein i is an integer, and i is more than or equal to 2 and less than or equal to 2 N -1, n is an integer greater than or equal to 2; 2 nd N The second ends of the metal resistors R are grounded; the resistance of each metal resistor R is the same.
Illustratively, to illustrate that the use of the metal resistor R reduces thermal noise, a digital-to-analog converter using a polysilicon resistor is compared with a digital-to-analog converter using the metal resistor R. Taking a 16-bit digital-to-analog converter as an example, the two converters are different only in the resistances in the resistor string 10, and the resistor string 10 contains 2 16 A resistor. Taking TSMC 0.35um Sige process as an example, the square resistance value of the polysilicon resistor with smaller deviation under different process angles under TT process angle is 102 omega, the minimum length of the polysilicon layer is 3um, the minimum width is 0.8um, and the minimum area of the polysilicon resistor is 12um 2 The resistance value is 584 Ω. The minimum width of the metal resistor Rmin is 0.45um, the minimum length is 2.7um, and the area is 1.215um 2 The square resistance was 78mΩ/≡and the parasitic resistance was 456mΩ. Assuming that the switching transistors in the switching module 20 are ideal devices, the noise spectral density of the analog-to-digital converter as seen from the intermediate node of the resistor string 10 (in which case the output resistance of the analog-to-digital converter is one half of the total resistance of the resistor string 10) and the minimum area of the resistor string 10 are calculated, and table 1 below can be obtained, as can be seen from table 1, the power spectral density of the output noise after the replacement of the polysilicon resistor with the metal resistor R will be much smaller than that of the resistor string 10 using the polysilicon resistor as the resistor string 10, except that the minimum area of the resistor string 10 constituted by the metal resistor RAbout one tenth of the area of polysilicon as the resistor string 10, the layout area can be greatly reduced, and the cost of the current sheet is reduced.
In particular, the implementation manner of the switch module 20 and the decoding module 30 may be set by those skilled in the art according to the actual situation, which is not limited herein. Exemplary implementations of switch module 20 and decode module 30 are described in detail below and will not be described in detail here.
The digital-to-analog converter provided by the embodiment of the invention comprises the resistor string, the switch module and the decoding module, wherein the resistor string is composed of the metal resistor, and the thermal noise of the resistor string is smaller due to the smaller square resistance value of the metal resistor. In addition, compared with the polysilicon resistor formed by multiple film layers, the metal resistor can be formed by at least one metal film layer, namely the film layer structure of the metal resistor is simple. The digital-to-analog converter structure can solve the problem of large thermal noise of the digital-to-analog converter, and achieve the effects of reducing the thermal noise of the digital-to-analog converter and simplifying the structure of the digital-to-analog converter.
In particular, the metal resistors R in the resistor string 10 may be arranged in various manners in the layout, and a typical example will be described below, which is not intended to limit the present application.
Fig. 2 is a circuit element diagram of a digital-to-analog converter according to an embodiment of the present invention. Fig. 3 is a schematic layout diagram of the digital-to-analog converter shown in fig. 2 according to an embodiment of the present invention. Fig. 4 is a schematic diagram of another arrangement of the digital-to-analog converter shown in fig. 2 according to an embodiment of the present invention. Referring to fig. 2-4, alternatively, 2 N The metal resistors R include a first metal resistor extending along the Y direction 420 and a second metal resistor extending along the X direction 410; the first metal resistor defines a plurality of first resistor bars 11 11 are arranged in parallel along the X direction 410; the second metal resistor defines a plurality of second resistor strips 12, the plurality of second resistor strips 12 being arranged along an X-direction 410; the first resistive strips 11 and the second resistive strips 12 are alternately connected.
It should be noted that the alternate connection described herein means that, for the first resistor 11 located at the head of the resistor string 10, one end is connected to the reference voltage terminal Vref, the other end is connected to the second resistor 12, for the first resistor 11 not located at the head and not located at the tail of the resistor string 10, one end is connected to one second resistor 12, the other end is connected to the other second resistor 12, and for the first resistor 11 located at the tail of the resistor string 10, one end is connected to the second resistor 12, and the other end is connected to the ground GND. Similarly, for the second resistor 12 located at the head of the resistor string 10, one end is connected to the reference voltage terminal Vref, the other end is connected to the first resistor 11, for the second resistor 12 not located at the head and not located at the tail of the resistor string 10, one end is connected to one first resistor 11, the other end is connected to the other first resistor 11, and for the second resistor 12 located at the tail of the resistor string 10, one end is connected to one first resistor 11, and the other end is connected to the ground GND.
Specifically, the number of the first metal resistors, the number of the second metal resistors, the number of the first metal resistors in each first resistor bar 11, and the number of the second metal resistors in each resistor bar may be set by those skilled in the art according to actual situations, and are not limited herein. As an example, n=16 is exemplarily shown in fig. 3 and 4, that is, the resistor string 10 includes 65536 metal resistors R, 256 first metal resistors are included in the first resistor bars 11 directly connected to the reference voltage terminal Vref, 255 first metal resistors are included in the other first resistor bars 11, and the plurality of first resistor bars 11 are aligned along the Y direction 420. Each second metal resistor defines a second resistor bar 12, the second resistor bars 12 being arranged in a plurality of two rows of second resistor bar rows (two second resistor bar rows are shown in fig. 3, four resistor bar rows are shown in fig. 4), a plurality of second electricity in each row of second resistor bar rowsThe barrier ribs 12 are aligned in the X direction 410. Specifically, 65536 metal resistors R are respectively denoted by R1, R2 and R3. R65536, rj represents the jth metal resistor in the resistor string 10, j is an integer, and j is more than or equal to 1 and less than or equal to 2 N . Wherein, R1-R256 define a first resistor 11, R257 define a second resistor 12, R258-R512 define a first resistor 11, R513 define a second resistor 12, R514-R768 define a first resistor 11, and so on, which are not described herein. Note that, for convenience of drawing and clarity, no reference sign is added to each metal resistor in fig. 3 and 4, and those skilled in the art may correspond Rj to each metal resistor in fig. 3 and 4 according to the connection relationship of each resistor in the resistor string 10 described above.
It can be appreciated that, compared with the resistor string 10 in which all the metal resistors R are arranged along the Y direction 420 and connected to form one resistor bar, the above arrangement manner can make the metal resistors R in the resistor string 10 distributed intensively, which is beneficial to reducing the length of the area occupied by the resistor string 10 and making the layout distribution of the resistor string 10 more reasonable.
With continued reference to fig. 3, optionally, the second resistor strip 12 includes only one second metal resistor, and two adjacent first resistor strips 11 are connected end to end through the second resistor strip 12; all the metal resistors R are rectangular in distribution area, and the reference voltage end Vref and the grounding end GND are arranged at two opposite ends of the rectangle or at two ends of the same side.
Specifically, the distance D between two adjacent first resistor strips 11 along the X direction 410 is equal to the length of the second metal resistor along the X direction 410, and the two adjacent first resistor strips 11 are connected end to end through one second metal resistor. For example, as shown in fig. 3, the first resistor 11 defined by R1-R256 and the first resistor 11 defined by R258-R512 are connected through R257, the first resistor 11 defined by R258-R512 and the first resistor 11 defined by R514-R768 are connected through R513, and so on, which are not described herein.
It will be appreciated that the distance between two adjacent first resistive tracks 11 can be adjusted by flexibly setting the length of the second metal resistor in the X direction 410. In addition, the distribution area of all the metal resistors R is rectangular, and the rectangular is in a regular pattern, so that the metal resistors R can be conveniently matched with other devices in the digital-to-analog converter.
With continued reference to fig. 3, the dimensions of the metal resistances R are optionally identical.
Specifically, the width of the first metal resistor in the X direction 410 is the same as the width of the second metal resistor in the Y direction 420, and the length of the first metal resistor in the Y direction 420 is the same as the length of the second metal resistor in the X direction 410. It should be noted that the same dimensions as described herein refer to the same dimensions as can be achieved by the preparation process.
It will be appreciated that by providing the metal resistors R to be the same size, the manufacturing process of the resistor string 10 may be simplified. Moreover, the distance between two adjacent first resistor strips 11 can be smaller, which is beneficial to realizing compact arrangement of the metal resistors R in the resistor string 10.
Fig. 4 is a schematic diagram of another arrangement of the metal resistor R in fig. 2 according to an embodiment of the present invention. Referring to fig. 2 and 4, alternatively, the second resistive track 12 includes only one second metal resistor, the second resistive track 12 is divided into a first type second resistive track and a second type second resistive track according to the length thereof along the X direction 410, the size of the first type second resistive track is smaller than that of the second type second resistive track, the (1+4n) th first resistive track 11 is connected with the (4+4n) th first resistive track 11 through the second type second resistive track, and the (2+4n) th first resistive track 11 is connected with the (3+4n) th first resistive track 11 through the first type second resistive track; the (3+4n) th first resistor bar 11 is connected with the (6+4n) th first resistor bar 11 through the second type second resistor bar, and the (4+4n) th first resistor bar 11 is connected with the (5+4n) th first resistor bar 11 through the first type second resistor bar; wherein n is an integer of 0 or more; the method comprises the steps of carrying out a first treatment on the surface of the All the metal resistors R are rectangular in distribution area, and the reference voltage end Vref and the grounding end GND are arranged at the same end of the rectangle.
It can be understood that the resistance value of the metal resistor R is calculated as: r= (L/W) ×r0, where L is the length of the metal resistor R, W is the width of the metal resistor R, and ro is the resistance value of the square resistor, so that, in order to make the resistance values of the metal resistors R the same, the length (and width) of the second metal resistor connecting adjacent first resistor strips 11 is smaller than the length (and width) of the second metal resistor connecting non-adjacent first resistor strips 11. For example, as shown in fig. 4, the first resistor 11 defined by R1-R256 and the first resistor 11 defined by R258-R512 are connected through R257 (second metal resistor with larger size), the first resistor 11 defined by R258-R512 and the first resistor 11 defined by R514-R768 are connected through R513 (second metal resistor with larger size), and so on, which will not be described herein.
It will be appreciated that the distance between two adjacent first resistive tracks 11 can be adjusted by flexibly setting the length of the smaller second metal resistor in the X direction 410. And all the metal resistors R are distributed in rectangular areas, and the rectangular areas are in regular patterns, so that the metal resistors R can be conveniently matched with other devices in the digital-to-analog converter.
With continued reference to fig. 4, optionally, the second metal resistor having a smaller size may have the same size as the first metal resistor, so that the distance between two adjacent first resistor strips 11 may be smaller, which is advantageous for achieving a compact arrangement of the metal resistors R in the resistor string 10.
With continued reference to fig. 2-4, the switch module 20 optionally includes 2 N A plurality of first layer switching transistors and a plurality of second layer switching transistors; the decoding module comprises a first decoder 31 and a second decoder 32; the first end of the j-th first-layer switching transistor is electrically connected with the second end of the j-th metal resistor R, and the control end of the first-layer switching transistor is electrically connected with the first decoder 31; wherein j is an integer, and j is more than or equal to 1 and less than or equal to 2 N The method comprises the steps of carrying out a first treatment on the surface of the The second terminal of the first layer switching transistor electrically connected to the same first resistor 11 is electrically connected to the first terminal of the same second layer switching transistor, and the control terminal of the second layer switching transistor is electrically connected to the second decoder 32.
Specifically, the switch module 20 includes a plurality of switch transistors S, and the switch transistors S are divided into two layers of switch transistors, i.e., a first layer of switch transistors and a second layer of switch transistors. Specifically, the plurality of first-layer switching transistors define a plurality of switching transistor columns 21, the plurality of switching transistor columns 21 are arranged in parallel along the X direction 410, and the second ends of the first-layer switching transistors located in the same switching transistor column 21 are electrically connected to the second ends of the same second-layer switching transistors, where the first-layer switching transistors corresponding to the second resistor strips 12 and the first-layer switching transistors corresponding to one first resistor strip 11 connected thereto are located in the same switching transistor column 21. The plurality of first-layer switching transistors further define a plurality of switching transistor rows 22, and the plurality of switching transistor rows 22 are arranged in parallel along the Y direction 420, and the control terminals of the first-layer switching transistors located in the same switching transistor row 22 are electrically connected to the same output terminal of the first decoder 31. Thus, the difficulty in designing the connection line between the switch module 20 and the decoding module 30 can be reduced. 2-4, the switch module 20 is shown as including 65536 first-layer switch transistors, denoted as S1, S2, S3, S65536, sj electrically connected to the second terminal of Rj, wherein S1-S256 defines a switch tube column 21, S257-S512 defines a switch tube column 21, S513-S768 defines a switch tube column 21, & S65281-S65536 defines a switch tube column 21; s1, S512, S513, S1024S 65536 define a switch tube row 22, S2, S511, S514, S1023S 65535 define a switch tube row 22, S256, S257, S768, S769S 65281 define a switch tube row 22. It should be noted that, for convenience and clarity of drawing, no reference sign is added to each first layer switching transistor in fig. 3 and 4, and those skilled in the art may correspond Sj to each first layer switching transistor in fig. 3 and 4 according to the fact that the switching transistor array 21 is located on the left side of the first resistor strip 11 electrically connected thereto and the arrangement sequence of S1 to S65526 is the same as the arrangement sequence of R1 to R65526.
Specifically, the number of the second layer switching transistors, the number of the output terminals of the first decoder 31, and the number of the output terminals of the second decoder 32 may be set by those skilled in the art according to the actual situation, and are not limited herein. By way of example, fig. 2-4 exemplarily show that the switching module 20 includes 65536 first layer switching transistors, 256 second-layer switching transistors are also included and are respectively marked as S65537, S65538 and S65539 and S65792. The first decoder 31 includes 256 outputs, denoted A1, A2, A3, A256, A1-A256, and 256, respectivelyThe switching tube rows 22 are correspondingly electrically connected. The second decoder 32 comprises 256 outputs, respectively marked as B1, B2 and B3.multidot.B256, B1-B256 are electrically connected to 256 switch tube columns 21. Wherein the first end of Sj is electrically connected to the second end of Rj, the second ends of S1-S256 are connected to the first end of S65537, the second ends of S257-S512 are connected to the first end of S65538, the second ends of S513-S768 are connected to the first end of S65539, the second ends of S65281-S65536 are connected to the first end of S65792, and the second ends of the second layer switching transistors are connected to the output end of the digital-analog converter. It should be noted that, for convenience and clarity of illustration, no reference numerals are added to each second layer switching transistor in fig. 3 and 4, and those skilled in the art can refer to S m×256 And S 65526+m Corresponding S65527-S65792 to each of the second layer switching transistors of fig. 3 and 4, where m is a positive integer and 1.ltoreq.m.ltoreq.256.
It will be appreciated that, compared to the configuration switch module 20 including only the first layer of switch transistors, the configuration switch module 20 including two layers of switch transistors (the first layer of switch transistors and the second layer of switch transistors), the number of output terminals of the first decoder 31 can be reduced, which is beneficial to reducing the size and design difficulty of the first decoder 31.
With continued reference to fig. 3 and 4, the first layer of switching transistors is located within the rectangle, the first layer of switching transistors defining a plurality of switching tube columns 21, the plurality of switching tube columns 21 being arranged in parallel along the X-direction 410, the switching tube columns 21 being located on one side of the first resistor strip 11 to which they are electrically connected; the second layer of switching transistors is located on one side of the sides of the rectangle extending in the X-direction 410; the first decoder 31 is located on one side of a side of the rectangle extending in the Y direction 420; the second decoder 32 is located on the side of the second layer of switching transistors facing away from the rectangle. In this way, the connection between the decoding module 30 and the switching module 20 can be simplified.
Fig. 5 is a circuit element diagram of another digital-to-analog converter according to an embodiment of the present invention. Fig. 6 is a schematic diagram of an arrangement of the digital-to-analog converter shown in fig. 5 according to an embodiment of the present invention. Referring to fig. 5 and 6, alternatively, 2 N The metal resistors R include a first metal resistor extending along the Y direction 420 and a second metal resistor extending along the X directionA second metal resistor extending in direction 410, and a third metal resistor extending in Y direction 420; the intersection point of the X axis along the X direction 410 and the Y axis along the Y direction 420 is taken as an origin, and the distribution area of all the metal resistors R is rectangular, and the rectangular covers four quadrants; in each quadrant, the first metal resistor defines a plurality of first resistor stripes 11, and the plurality of first resistor stripes 11 are arranged in parallel along the Y direction 420; the second metal resistor defines a plurality of second resistor bars 12, the plurality of second resistor bars 12 are arranged along the X direction 410, the third metal resistor defines two third resistor bars 13, and the plurality of third resistor bars 13 are arranged along the X direction 410; the first resistor strips 11 and the second resistor strips 12 are alternately connected; a first resistor 11 in the fourth quadrant is connected to a first resistor 11 in the first quadrant by a third resistor 13, and a first resistor 11 in the second quadrant is connected to a first resistor 11 in the third quadrant by a further third resistor 13.
Specifically, the number of the first metal resistors, the number of the second metal resistors, the number of the first metal resistors in each first resistor bar 11, the number of the second metal resistors in each second resistor bar 12, and the number of the third metal resistors in each third resistor bar 13 can be set by those skilled in the art according to the actual situation, and are not limited herein. Specifically, each quadrant includes 2 N-2 And a metal resistor R.
In particular, in each quadrant, the specific implementation manner of connecting the two first resistive strips 11 through the second resistive strip 12 may be set by those skilled in the art according to the actual situation, which is not limited herein. Two typical examples are shown below. First, as shown in fig. 6, in each quadrant, the second resistive strip 12 includes only one second metal resistor, the second resistive strip 12 is divided into a first type of second resistive strip and a second type of second resistive strip according to the length of the second resistive strip along the X direction 410, the size of the first type of second resistive strip is smaller than that of the second type of second resistive strip, the (1+4n) th first resistive strip is connected with the (4+4n) th first resistive strip through the second type of second resistive strip, and the (2+4n) th first resistive strip is connected with the (3+4n) th first resistive strip through the first type of second resistive strip; the (3+4n) th first resistor bar is connected with the (6+4n) th first resistor bar through the second type second resistor bar, and the (4+4n) th first resistor bar is connected with the (5+4n) th first resistor bar through the first type second resistor bar; wherein n is an integer of 0 or more; all metal resistors R in the same quadrant are rectangular in distribution area. Second, in each quadrant, the second resistor strips 12 only comprise a second metal resistor, two adjacent first resistor strips 11 are connected end to end through the second resistor strips 12, and the distribution area of all the metal resistors R in the same quadrant is rectangular. It will be appreciated that the arrangement of the metal resistors in each quadrant is similar to that shown in fig. 4 when the metal resistors in each quadrant are arranged according to the first arrangement, and thus, the arrangement of the metal resistors in each quadrant according to the first arrangement is only exemplarily described in detail below, and the situation that the metal resistors in each quadrant are arranged according to the first arrangement is not described again.
By way of example, n=8 is exemplarily shown in fig. 5 and 6, i.e. the resistor string 10 comprises 256 metal resistors R, denoted as R1, R2, R3. R256, respectively, and Rj represents the jth metal resistor in the resistor string 10. R1-R64 are in the fourth quadrant, R2-R128 are in the first quadrant, R129-R248 are in the second quadrant, and R249-R256 are in the fourth quadrant. The first resistor 11 directly connected to the reference voltage terminal Vref includes 8 first metal resistors, and the other first resistor 11 includes 7 first metal resistors. The second resistor bar 12 includes a second metal resistor therein. The third resistor strip 13 includes a third metal resistor. Specifically, in the fourth quadrant, R1-R8 define a first resistor 11, R9 define a second resistor 12, R10-R16 define a first resistor 11, R17 define a second resistor 12, R18-R24 define a first resistor 11, R25 define a second resistor 12, R26-R32 define a first resistor 11, R33 define a second resistor 12, R34-R40 define a first resistor 11, R41 define a second resistor 12, R42-R48 define a first resistor 11, R49 define a second resistor 12, R50-R56 define a first resistor 11, R57 define a second resistor 12, R58-R64 define a first resistor 11. The first resistor 11 and the second resistor 12 defined in the first quadrant, the second quadrant, and the third quadrant are similar, and will not be described herein. In the second quadrant, R65 defines a third resistor bar 13, and in the third quadrant, R183 defines a first third resistor bar 13. Note that, for convenience and clarity of drawing, no reference sign is added to each metal resistor R in fig. 5, and those skilled in the art may correspond Rj to each metal resistor in fig. 5 according to the connection relationship between the resistors in the resistor string 10 described above.
With continued reference to fig. 5 and 6, the switch module 20 optionally includes 2 N A plurality of first layer switching transistors, a plurality of second layer switching transistors, and a plurality of third layer switching transistors; the decoding module 30 includes a first decoder 31, a second decoder 32, a third decoder 33, and a fourth decoder 34; the control end of the first layer of switching transistor is electrically connected with the first decoding; wherein j is an integer, and j is more than or equal to 1 and less than or equal to 2 N The method comprises the steps of carrying out a first treatment on the surface of the In each quadrant, the second end of the first layer of switching transistors electrically connected with the same first resistor bar 11 is electrically connected with the first end of the same second layer of switching transistors; the control end of the second-layer switching transistor which is electrically connected with the metal resistor R positioned in the first quadrant and the second quadrant through the first-layer switching transistor is electrically connected with the second decoder 32; the control end of the second-layer switching transistor which is electrically connected with the metal resistor R positioned in the third quadrant and the fourth quadrant through the first-layer switching transistor is electrically connected with the third decoder 33; the second end of the second layer of switching transistors which are electrically connected with the metal resistor R in the same quadrant through the first layer of switching transistors is electrically connected with the first end of the same third layer of switching transistors; the control terminal of the third switching transistor is electrically connected to the fourth decoder 34.
Specifically, in each quadrant, the plurality of first-layer switching transistors define a plurality of switches Guan Hang, the plurality of switching transistor rows 22 are arranged in parallel along the Y direction 420, and the control ends of the first-layer switching transistors located in the same switching transistor row 22 are electrically connected to the same output end of the first decoder 31; the plurality of first-layer switching transistors define a plurality of switching transistor columns 21, the plurality of switching transistor columns 21 are arranged in parallel along the X direction 410, and second ends of the first-layer switching transistors located in the same switching transistor column 21 are electrically connected to second ends of the same second-layer switching transistors, wherein the first-layer switching transistors corresponding to the second resistor strips 12 and the first-layer switching transistors corresponding to one first electrical group strip connected thereto are located in the same switching transistor column 21. Thus, the difficulty in designing the connection line between the switch module 20 and the decoding module 30 can be reduced. Illustratively, the switch module 20 is shown in FIGS. 5 and 6 as including 256 first layer switch transistors, denoted S1, S2, S3, S256, S j electrically connected to the second terminal of Rj, wherein S1-S64 are in the fourth quadrant, S65-S128 are in the first quadrant, S129-S182 are in the second quadrant, and S183-S256 are in the third quadrant. In the fourth quadrant, S1-S8 define a switch tube row 21, S8-S16 define a switch tube row 21, S17-S24 define a switch tube row 21, & gtS 57-S64 define a switch tube row 21; s1, S16, S17, S32 & S64 define a switch tube row 22, S2, S15, S18, S31 & S63 define a switch tube row 22, S8, S9, S24, S25 & S57 define a switch tube row 22. The switching tube rows 22 and the switching tube columns 21 defined in the first quadrant, the second quadrant, and the third quadrant are similar, and will not be described again. It should be noted that, for convenience of drawing and clarity, no reference sign is added to each first layer of switching transistors in fig. 6, and those skilled in the art may correspond Sj to each first layer of switching transistors in fig. 6 according to the fact that the switching transistor array 21 is located on the left side of the first resistor strip 11 electrically connected thereto, and the arrangement sequence of S1 to S256 is the same as the arrangement sequence of R1 to R256.
Specifically, the number of the second layer switching transistors, the number of the third layer switching transistors, the number of the output terminals of the first decoder 31, the number of the output terminals of the second decoder 32, the number of the output terminals of the third decoder 33, and the number of the output terminals of the fourth decoder 34 may be set by those skilled in the art according to practical situations, and are not limited herein. Exemplary, exemplary is shown in FIGS. 5 and 6The switching module 20 includes 256 first layer switching transistors, denoted S1-S256, respectively; the switch module 20 further includes 32 second layer switch transistors, denoted S257-S288, respectively; the switching module 20 further includes 4 third tier switching transistors, denoted S289-S292, respectively. The first decoder 31 comprises 8 outputs, denoted A1, A2, A3 A8, for each quadrant, A1-A8 are electrically connected with 8 switch tube rows 22 in that quadrant. The second decoder 32 comprises 8 outputs, respectively marked as B1, B2 and B3.multidot.B8, for either of the first and second quadrants, B1-B8 are electrically connected to 8 switch tube columns 21 in that quadrant. The third decoder 33 comprises 8 outputs, denoted C1, C2, C3C 8, for either of the third and fourth quadrants, C1-C8 are electrically connected to 8 switch tube columns 21 in that quadrant. The fourth decoder 34 includes 4 output terminals, denoted as D1, D2, D3, D4, respectively, electrically connected to the four third layer switching transistors. Wherein the first end of Sj is electrically connected to the second end of Rj, the second ends of S1-S8 are connected to the first end of S257, the second ends of S9-S16 are connected to the first end of S258, the second ends of S17-S24 are connected to the first end of S259, &. Cndot. Is, the second ends of S249-S256 are connected to the first end of S288, the second end of S257-S264 is connected to the first end of S289, the second end of S265-S272 is connected to the first end of S290, the second end of S273-S280 is connected to the first end of S291, the second end of S273-S288 is connected to the first end of S292, and the second end of S289-S292 is electrically connected to the output end of the digital-to-analog converter. It should be noted that, for convenience and clarity of illustration, no reference numerals are added to each second layer switching transistor in fig. 6, and those skilled in the art can refer to S p×8 And S 256+p Corresponding S257-S288 to the second layer switching transistors of fig. 6, wherein 1.ltoreq.p.ltoreq.32.
It will be appreciated that the switch module 20 includes three layers of switch transistors (a first layer of switch transistors and a second layer of switch transistors), which can further reduce the number of output terminals of the first decoder 31, and is beneficial to reducing the size and design difficulty of the first decoder 31. And the number of the switching transistors which need to be controlled at the output end of each decoder is reduced, the time delay between the switching transistors which are electrically connected with the output end of the same decoder is reduced, and the response speed of the digital-to-analog converter is further improved.
It should be noted that, fig. 2-4 schematically illustrate that the switch module 20 includes two layers of switch transistors, and fig. 5 and 6 schematically illustrate that the switch module 20 includes three layers of switch transistors, but the embodiment of the present invention is not limited thereto, and those skilled in the art may set the number of layers of switch transistors in the switch module 20 according to the actual situation.
With continued reference to fig. 5 and 6, optionally, the first layer of switching transistors is located within a rectangle, in each quadrant, the first layer of switching transistors defining a plurality of switching tube columns 21, the plurality of switching tube columns 21 being arranged in parallel along the X-direction 410, the switching tube columns 21 being located on one side of the first resistive track 11 to which they are electrically connected; the first decoder 31 is located on one side of a side of the rectangle extending in the Y direction 420; the second decoder 32 and the second layer of switching transistors electrically connected thereto are located on one side of the sides of the rectangle extending in the X direction 410, adjacent to the first quadrant and the second quadrant; the third decoder 33 and the second layer switching transistor electrically connected thereto are located on one side of the rectangle extending in the X direction 410, and are close to the third quadrant and the fourth quadrant; the fourth decoder 34 is located on a side of the first decoder 31 facing away from the rectangle, or the fourth decoder 34 is located on opposite sides of the rectangle from the first decoder 31 (as shown in fig. 6). In this way, the connection between the decoding module 30 and the switching module 20 can be simplified.
With continued reference to fig. 3, 4 and 6, optionally, in the Y direction 420, each two adjacent first layer switching transistors form a switching transistor group, with the second ends of the two first layer switching transistors in the same switching transistor group being connected, the first end of each first layer switching transistor being flush with the second end of the metal resistor R electrically connected thereto.
Specifically, the length of the metal resistor R along the Y direction 420 is the same as the length of the switching transistor group along the Y direction 420. In the same group of switching transistors, a first end of one first layer switching transistor is adjacent to a first end of another first layer switching transistor. As such, the first end of each first layer switching transistor may be flush with the second end of the metal resistor R electrically connected thereto.
It can be appreciated that by providing the first end of each first-layer switching transistor flush with the second end of the metal resistor R electrically connected thereto, the convenience of connection of the first end of the first-layer switching transistor and the second end of the metal resistor R corresponding thereto can be improved.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (14)
1. A digital-to-analog converter, comprising:
a resistor string comprising 2 N The series metal resistors are connected in series, one end of the resistor string is electrically connected with a reference voltage end, and the other end of the resistor string is connected with a grounding end; wherein N is an integer greater than or equal to 1;
the switch module is electrically connected with the resistor string and the decoding module respectively; the decoding module is used for responding to an externally input digital signal and outputting a switch control signal; the switch module is used for responding to the switch control signal and outputting an analog signal matched with the digital signal;
2 N the metal resistors comprise a first metal resistor extending along the Y direction and a second metal resistor extending along the X direction;
the first metal resistor defines a plurality of first resistor strips, and the first resistor strips are arranged in parallel along the X direction; the second metal resistor defines a plurality of second resistor bars, and the plurality of second resistor bars are arranged along the X direction; the first resistor strips and the second resistor strips are alternately connected.
2. A digital to analog converter according to claim 1, characterized in that,
The first end of the 1 st metal resistor is connected with the reference voltage end;
the first end of the ith metal resistor is connected with the second end of the (i-1) th metal resistor, and the second end of the ith metal resistor is connected with the first end of the (i+1) th metal resistor; wherein i is an integer, and i is more than or equal to 2 and less than or equal to 2 N -1, n is an integer greater than or equal to 2;
2 nd N The second end of each metal resistor is grounded.
3. A digital to analog converter according to claim 1, characterized in that,
the resistance value of each metal resistor is the same.
4. The digital to analog converter of claim 1, wherein the width of the metal resistor ranges from 0.05um to 2um and the length of the metal resistor ranges from 0.3um to 4um.
5. A digital to analog converter according to claim 1, characterized in that,
the second resistor strips only comprise one second metal resistor, and two adjacent first resistor strips are connected end to end through the second resistor strips; all the metal resistor distribution areas are rectangular, and the reference voltage end and the grounding end are arranged at two opposite ends of the rectangle or two ends of the same side.
6. The digital to analog converter of claim 5, wherein each of said metal resistors is the same size.
7. A digital to analog converter according to claim 1, characterized in that,
the second resistor strip only comprises one second metal resistor, the second resistor strip is divided into a first type of second resistor strip and a second type of second resistor strip according to the length of the second resistor strip along the X direction, and the size of the first type of second resistor strip is smaller than that of the second type of second resistor strip;
the 4n+1 th first resistor strip is connected with the 4n+4 th first resistor strip through the second type second resistor strip, and the 4n+2 th first resistor strip is connected with the 4n+3 th first resistor strip through the first type second resistor strip;
the 4n+3 first resistor strips are connected with the 4n+6 first resistor strips through the second type second resistor strips, and the 4n+4 first resistor strips are connected with the 4n+5 first resistor strips through the first type second resistor strips; wherein n is an integer of 0 or more;
all the metal resistor distribution areas are rectangular, and the reference voltage end and the grounding end are arranged at the same end of the rectangle.
8. The digital to analog converter of claim 1, wherein said switching module comprises 2 N A plurality of first layer switching transistors and a plurality of second layer switching transistors; the decoding module comprises a first decoder and a second decoder;
A first end of the j-th layer of switching transistor is electrically connected with a second end of the j-th layer of metal resistor, and a control end of the first layer of switching transistor is electrically connected with the first decoder; wherein j is an integer, and j is more than or equal to 1 and less than or equal to 2 N ；
The second end of the first layer of switching transistors electrically connected with the same first resistor strip is electrically connected with the first end of the same second layer of switching transistors, and the control end of the second layer of switching transistors is electrically connected with the second decoder.
9. The digital to analog converter of claim 8, wherein,
all the metal resistor distribution areas are rectangular;
the first layer of switching transistors are positioned in the rectangle, the first layer of switching transistors define a plurality of switching tube columns, the switching tube columns are arranged in parallel along the X direction, and the switching tube columns are positioned on one side of the first resistor strip which is electrically connected with the switching tube columns;
the second layer of switching transistors is positioned on one side of the rectangle extending along the X direction;
the first decoder is positioned on one side of a side extending along the Y direction in the rectangle;
the second decoder is positioned on one side of the second layer of switching transistors, which is away from the rectangle.
10. Digital-to-analog converter according to claim 2, characterized in that 2 N The metal resistors comprise a first metal resistor extending along the Y direction, a second metal resistor extending along the X direction and a third metal resistor extending along the Y direction;
the intersection point of the X axis along the X direction and the Y axis along the Y direction is used as an origin, and all the metal resistor distribution areas are rectangular, and the rectangular covers four quadrants;
in each quadrant, the first metal resistor defines a plurality of first resistor bars, and the plurality of first resistor bars are arranged in parallel along the Y direction; the second metal resistor defines a plurality of second resistor strips, the plurality of second resistor strips are arranged along the X direction, the third metal resistor defines two third resistor strips, and the plurality of third resistor strips are arranged along the X direction; the first resistor strips and the second resistor strips are alternately connected;
a first resistor bar positioned in the fourth quadrant is connected with a first resistor bar positioned in the first quadrant through one third resistor bar, and a first resistor bar positioned in the second quadrant is connected with a first resistor bar positioned in the third quadrant through the other third resistor bar.
11. The digital to analog converter of claim 10, wherein said switch module packageDraw together 2 N A plurality of first layer switching transistors, a plurality of second layer switching transistors, and a plurality of third layer switching transistors; the decoding module comprises a first decoder, a second decoder, a third decoder and a fourth decoder;
a first end of the j-th layer of switching transistor is electrically connected with a second end of the j-th layer of metal resistor, and a control end of the first layer of switching transistor is electrically connected with the first decoding; wherein j is an integer, and j is more than or equal to 1 and less than or equal to 2 N ；
In each quadrant, the second end of the first layer of open-transistor electrically connected with the same first resistor strip is electrically connected with the first end of the same second layer of switch transistor; the control end of the second-layer switching transistor which is electrically connected with the metal resistor positioned in the first quadrant and the second quadrant through the first-layer switching transistor is electrically connected with the second decoder; the control end of the second-layer switching transistor which is electrically connected with the metal resistor positioned in the third quadrant and the fourth quadrant through the first-layer switching transistor is electrically connected with the third decoder; a second end of the second layer of switching transistors electrically connected with the metal resistor in the same quadrant through the first layer of switching transistors is electrically connected with a first end of the same third layer of switching transistors;
And the control end of the third-layer switching transistor is electrically connected with the fourth decoder.
12. The digital to analog converter of claim 11, wherein,
the first layer of switching transistors are positioned in the rectangle, and in each quadrant, the first layer of switching transistors define a plurality of switching tube columns which are arranged in parallel along the X direction, and the switching tube columns are positioned on one side of the first resistor strip which is electrically connected with the switching tube columns;
the first decoder is positioned on one side of a side extending along the Y direction in the rectangle;
the second decoder and the second layer switching transistor electrically connected thereto are located at one side of a side of the rectangle extending in the X direction and are close to the first quadrant and the second quadrant;
the third decoder and the second layer switching transistor electrically connected thereto are located at one side of a side of the rectangle extending in the X direction and are close to the third quadrant and the fourth quadrant;
the fourth decoder is positioned on one side of the first decoder facing away from the rectangle.
13. The digital to analog converter according to claim 9 or 12, wherein,
and along the Y direction, every two adjacent first-layer switching transistors form a switching transistor group, the second ends of the two first-layer switching transistors in the same switching transistor group are connected, and the first end of each first-layer switching transistor is flush with the second end of the metal resistor electrically connected with the first end of each first-layer switching transistor.
14. The digital to analog converter of claim 1, wherein the material of the metal resistor comprises aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011486714.XA CN112636753B (en) | 2020-12-16 | 2020-12-16 | Digital-to-analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011486714.XA CN112636753B (en) | 2020-12-16 | 2020-12-16 | Digital-to-analog converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112636753A CN112636753A (en) | 2021-04-09 |
| CN112636753B true CN112636753B (en) | 2024-04-09 |
Family
ID=75313632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011486714.XA Active CN112636753B (en) | 2020-12-16 | 2020-12-16 | Digital-to-analog converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112636753B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471669A (en) * | 2007-12-28 | 2009-07-01 | 上海华虹Nec电子有限公司 | D/A converter and D/A converting method |
| CN110474644A (en) * | 2019-07-25 | 2019-11-19 | 海菲曼（天津）科技有限公司 | A kind of audio digital to analog converter, multimedia digiverter and terminal device |
| CN210839536U (en) * | 2020-01-08 | 2020-06-23 | 海菲曼（天津）科技有限公司 | Voltage-dividing type R2R-structured audio digital-to-analog converter |
| CN111404548A (en) * | 2020-05-12 | 2020-07-10 | 普源精电科技股份有限公司 | Reference voltage circuit and transmission method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8975964B2 (en) * | 2012-02-06 | 2015-03-10 | Texas Instruments Incorporated | BEMF monitor gain calibration stage in hard disk drive servo integrated circuit |
| US9762211B2 (en) * | 2015-11-03 | 2017-09-12 | Samsung Electronics Co., Ltd | System and method for adjusting duty cycle in clock signals |
-
2020
- 2020-12-16 CN CN202011486714.XA patent/CN112636753B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101471669A (en) * | 2007-12-28 | 2009-07-01 | 上海华虹Nec电子有限公司 | D/A converter and D/A converting method |
| CN110474644A (en) * | 2019-07-25 | 2019-11-19 | 海菲曼（天津）科技有限公司 | A kind of audio digital to analog converter, multimedia digiverter and terminal device |
| CN210839536U (en) * | 2020-01-08 | 2020-06-23 | 海菲曼（天津）科技有限公司 | Voltage-dividing type R2R-structured audio digital-to-analog converter |
| CN111404548A (en) * | 2020-05-12 | 2020-07-10 | 普源精电科技股份有限公司 | Reference voltage circuit and transmission method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112636753A (en) | 2021-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0136869B1 (en) | A resistance ladder network | |
| US6194668B1 (en) | Multi-layer circuit board | |
| JP5420485B2 (en) | Analog to digital converter | |
| US20050161725A1 (en) | Semiconductor component comprising an integrated latticed capacitance structure | |
| US6496131B2 (en) | Capacitor-array D/A converter including a thermometer decoder and a capacitor array | |
| JP2010278450A5 (en) | ||
| CN112636753B (en) | Digital-to-analog converter | |
| US5534862A (en) | Resistor string with equal resistance resistors | |
| KR930001724B1 (en) | Resistor and electronic device | |
| JPS58112343A (en) | Semiconductor and manufacture thereof | |
| CN107612549B (en) | Twisted-pair type shared central capacitor array and layout design method thereof | |
| US5014054A (en) | Digital-to-analog converter of the resistor string type | |
| JP4927494B2 (en) | Analog-digital converter and design method of analog-digital converter | |
| US7504980B2 (en) | Semiconductor device | |
| JP2009077370A (en) | Digital-to-analog converter | |
| CN111106832B (en) | DAC circuit structure and resistance voltage-dividing type DAC | |
| JP3028420B2 (en) | Semiconductor integrated device | |
| WO2020036479A1 (en) | Binary weighted capacitor array with split capacitor layout | |
| JPS61156851A (en) | Integrated circuit | |
| US10979063B2 (en) | Electronic circuit with a set of weighted capacitances | |
| US5905427A (en) | Integrated circuit resistor array | |
| TWI283971B (en) | D/A converter | |
| JP2991117B2 (en) | D / A converter | |
| US6911896B2 (en) | Enhanced linearity, low switching perturbation resistor strings | |
| JPS5826809B2 (en) | voltage divider circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |