CN112635436B - Chip packaging structure and preparation method thereof - Google Patents

Chip packaging structure and preparation method thereof Download PDF

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Publication number
CN112635436B
CN112635436B CN202011499407.5A CN202011499407A CN112635436B CN 112635436 B CN112635436 B CN 112635436B CN 202011499407 A CN202011499407 A CN 202011499407A CN 112635436 B CN112635436 B CN 112635436B
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Prior art keywords
chip
semiconductor chip
conductive
arcs
sealing layer
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CN202011499407.5A
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CN112635436A (en
Inventor
陈鹏
钱卫松
曾心如
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202011499407.5A priority Critical patent/CN112635436B/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

Abstract

The present disclosure discloses a chip packaging structure and a method for manufacturing the same, the chip packaging structure comprising: a package substrate having a first surface and a second surface opposite to each other; the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate; a plurality of grounding pads arranged on the first surface of the packaging substrate and at least partially surrounding the semiconductor chip; a plastic layer covering the first surface of the package substrate and covering the semiconductor chip and the plurality of grounding pads; the metal layer covers the top surface and the side surface of the plastic sealing layer; and the plurality of conductive arcs are buried in the plastic sealing layer and are provided with a first end and a second end which are opposite to each other, wherein the first ends of the plurality of conductive arcs are respectively connected with one of the plurality of grounding pads, and the second ends of the plurality of conductive arcs are exposed from the side surface of the plastic sealing layer and are contacted with the metal layer.

Description

Chip packaging structure and preparation method thereof
Technical Field
The present disclosure relates to the field of packaging technologies of integrated circuits, and in particular, to a chip packaging structure and a method for manufacturing the same, which has an electromagnetic interference resistant function.
Background
In the fabrication of integrated circuits, chips are obtained by the steps of wafer fabrication, integrated circuit formation, dicing wafers, and the like. The chip formed by the wafer dicing can be electrically connected to a carrier such as a lead frame or a package substrate, and the chip is packaged by a chip packaging technology to avoid the chip from contacting the outside and preventing the outside from damaging the chip. With the rapid development of photoelectric and micro-electric manufacturing process technologies, electronic products are always developed towards smaller, lighter and cheaper directions, so that the packaging form of chip elements is improved continuously.
With the increasing demands of people for functionality of electronic products, various chips are widely used in various electrical devices. The chips are easily affected by electromagnetic radiation in the operation process, the operation frequency is disturbed, and the working stability of the chips is reduced.
Disclosure of Invention
In order to solve the above technical problems, the present disclosure provides a novel chip package structure and a method for manufacturing the same, which has an anti-electromagnetic interference function.
According to an aspect of the present disclosure, there is provided a chip package structure, including: a package substrate having a first surface and a second surface opposite to each other; the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate; a plurality of grounding pads arranged on the first surface of the packaging substrate and at least partially surrounding the semiconductor chip; a plastic layer covering the first surface of the package substrate and covering the semiconductor chip and the plurality of grounding pads; the metal layer covers the top surface and the side surface of the plastic sealing layer; and the plurality of conductive arcs are buried in the plastic sealing layer and are provided with a first end and a second end which are opposite to each other, wherein the first ends of the plurality of conductive arcs are respectively connected with one of the plurality of grounding pads, and the second ends of the plurality of conductive arcs are exposed from the side surface of the plastic sealing layer and are contacted with the metal layer.
In some embodiments, the chip package structure further includes a plurality of conductive balls disposed on the second surface of the package substrate and electrically connected to the semiconductor chip.
In some embodiments, the second ends of the plurality of conductive arcs are located at 1/4 to 3/4 of the height of the side of the molding layer.
In certain embodiments, the second ends of the plurality of conductive arcs have a pitch of greater than or equal to 50 μm and less than or equal to 500 μm.
In certain embodiments, the plurality of conductive arcs have a wire diameter of greater than or equal to 20 and less than or equal to 30 microns.
In some embodiments, the metal layer is made of the following materials or any combination thereof: aluminum, copper, iron.
In some embodiments, the plurality of conductive arcs are made of gold, silver, aluminum or copper.
In some embodiments, the plurality of ground pads entirely surround the semiconductor chip, and the metal layer and the plurality of conductive arcs form a bottom-shrunk faraday cage.
In some embodiments, the semiconductor chip is electrically connected to the package substrate through wire bonding or flip chip bonding.
In some embodiments, the semiconductor chip operates at a frequency between 0.5GHz and 10GHz.
In some embodiments, the plurality of conductive arcs are 1/4 circular-like arcs.
According to still another aspect of the present disclosure, there is provided a method for manufacturing a chip package structure, including the steps of:
providing a package substrate provided with a semiconductor chip, a plurality of grounding pads, a plurality of leads and a wire on a first surface, wherein the wire is arranged along the periphery of the package substrate and at least partially surrounds the semiconductor chip, the plurality of grounding pads are corresponding to the wire and are arranged closer to the semiconductor chip than the wire, and the plurality of grounding pads partially surround the semiconductor chip and are connected with the wire through the plurality of leads;
forming a plastic layer on the first surface of the packaging substrate, wherein the plastic layer encapsulates the wires, the leads and the grounding pads of the semiconductor chip;
cutting the plastic sealing layer and the packaging substrate along the periphery of the semiconductor chip so as to cut the leads between the grounding pads and the wires to form a plurality of conductive arcs embedded in the plastic sealing layer, wherein the plurality of conductive arcs are provided with a first end respectively connected with one of the grounding pads and a second end exposed out of the side surface of the plastic sealing layer; and
forming a metal layer on the top surface and the side surface of the plastic sealing layer after the cutting treatment, and carrying out second end treatment for contacting a plurality of conductive arcs exposed from the side surface of the plastic sealing layer.
In some embodiments, the plurality of leads are severed from the highest point of the plurality of leads in the step of dicing the plastic layer and package substrate along the periphery of the semiconductor chip.
In certain embodiments, the method of making further comprises the steps of: a plurality of conductive balls are disposed on the second surface of the package substrate, wherein the plurality of conductive balls are electrically connected to the semiconductor chip.
The beneficial effects of the present disclosure are that a novel chip package structure and a method for manufacturing the same are provided, wherein one end of a plurality of arc-shaped wires buried in a plastic sealing layer and exposed out of a side surface of the plastic sealing layer contacts a metal layer covering the top surface and the side surface of the plastic sealing layer, so that a faraday cage with an electromagnetic interference resistance function is provided while a grounding function of the metal layer is realized to shield electromagnetic interference, and further effective operation of a semiconductor chip in the chip package structure at an operating frequency of 0.5GHz-10GHz is ensured. Meanwhile, the metal layer for electromagnetic interference (EMI) shielding is not dependent on the fact that grounding is realized in a narrow area at the bottom of the packaging substrate, so that the grounding structure and the grounding cost are simplified, the preparation method of the chip packaging structure is simple and convenient to implement, the cost is low, and the chip packaging structure is suitable for batch production.
Drawings
In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1-3 are schematic diagrams of a method of fabricating a chip package structure according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure.
Fig. 5 is a schematic view of a bottom-collapsed faraday cage formed by the metal layer 700 of fig. 4 and a plurality of conductive arcs 304'.
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ top ], [ bottom ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., are only referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention. In the drawings, like elements are designated by like reference numerals.
The following is a schematic diagram illustrating a method for manufacturing a chip package structure according to an embodiment of the present disclosure by using fig. 1 to 3.
Referring to fig. 1, a package substrate 100 is provided, which has a first surface a and a second surface B opposite to each other. As shown in fig. 1, two semiconductor chips 200 are separately disposed on the first surface a of the package substrate 100, and the two semiconductor chips 200 are electrically connected to the package substrate 100, respectively. In this embodiment, the two semiconductor chips 200 are electrically connected to the bonding pads 206 disposed on the semiconductor chip 200 and the bonding pads 202 disposed on the package substrate 100 through a wire bonding (wire bonding) process, respectively, by a plurality of wires 204, so as to form electrical connections between the semiconductor chip 200 and the package substrate 100, respectively. In other embodiments, other processes such as flip-chip bonding (flip-chip bonding) may be used to form electrical connections between the semiconductor chip 200 and the package substrate 100.
With continued reference to fig. 1, a conductive line 300 and a plurality of ground pads 302 are further disposed on the first surface a of the package substrate 10. As shown in fig. 1, the conductive lines 300 are disposed along the periphery of the package substrate 10 and at least partially surround the plurality of semiconductor chips 200, and the plurality of ground pads 302 are disposed corresponding to the conductive lines and closer to each semiconductor chip 200 than the conductive lines. The plurality of ground pads 302 are connected to the conductive line 300 through the leads 304, respectively. The plurality of ground pads 302 form electrical connections with the ground lines 120 (shown in fig. 4, but not shown in fig. 1) within the package substrate 10. In this embodiment, the package substrate 100 is, for example, an FR4 copper-clad circuit board or a BT resin-based circuit board, or another package substrate. The semiconductor chip 200 is a semiconductor chip with an operating frequency of 0.5GHz-10GHz, and can be used as an RF radio frequency chip, a GPS positioning chip, a DRAM, a NAND memory chip, a Controller (Controller) chip, a Bluetooth chip, or the like. In this embodiment, the plurality of leads 204 and 304 may each be a semi-circular conductive arc, which may be formed by a lead process.
Referring to fig. 2, a molding layer 400 is formed on the first surface a of the package substrate by a molding process (not shown). The molding layer 400 covers the entire first surface a of the package substrate 100 and encapsulates the semiconductor chip 200, the plurality of pads 206, the wires 300, the plurality of leads 204 and 304, and the plurality of ground pads 302. Then, a plurality of conductive balls 450 (shown in fig. 4, but not in fig. 2) are formed on the surface of the package substrate B at positions corresponding to the semiconductor chip 200. The conductive balls 450 may be arranged in a ring shape or a rectangular shape, and electrically connected to the semiconductor chip 200 through a circuit (not shown) disposed in the package substrate 100.
Referring to fig. 3, the structure shown in fig. 2 is cut along a plurality of directions such as line A-A, line B-B, line C-C, line D-D, and line E-E in fig. 3 by the cutting process 600, so as to obtain two separated chip package structures. In the dicing process, the leads 304 are severed from the highest points of the leads 304 to form a plurality of conductive traces 304' (shown in fig. 4-5, but not in fig. 3) embedded within the plastic layer 400. Here, the conductive arc 304' after cutting is an arc resembling a 1/4 circle (approximately circular). It is understood that the plurality of conductive arcs 304' are buried in the molding layer 400, but still have opposite first ends and second ends, wherein the first ends of the plurality of conductive arcs 304' are respectively connected to one of the plurality of grounding pads 302, and the second ends of the plurality of conductive arcs 304' are exposed ends of the side surface of the molding layer 400. A metal layer 700 (shown in fig. 4-5, but not shown in fig. 3) is then formed on the top and side surfaces of the plastic layer 400 and on the side surfaces of the package substrate 100 in the singulated two chip packages by a sputtering or spraying process. Thus, the ends of the conductive arcs 304' exposed to the side of the molding layer 400 may serve as exposed grounding metal terminals to contact the metal layer 700.
Referring to fig. 4, a schematic diagram of a singulated chip package according to an embodiment of the disclosure is shown. Here, for simplicity of drawing, only the package substrate 100, the semiconductor chip 200, the conductive arcs 304', the plastic layer 400, the metal layer 700, and the conductive balls 450 are shown. As shown in fig. 4, the second ends of the plurality of conductive arcs 304 'may be disposed at a position (having a height H) of 1/4 to 3/4 (e.g., about 1/2) of the height H of the side surface of the molding layer 400, and the second ends of the plurality of conductive arcs 304' may have a pitch P of 50 μm or more and 500 μm or less (e.g., 100 μm, 300 μm) or less. The plurality of conductive arcs 304' may have a wire diameter of greater than or equal to 20 and less than or equal to 30 μm (e.g., 25 μm), and may be gold, silver, aluminum, or copper, or any combination thereof. The metal layer 700 may be made of aluminum, copper or iron, and has a thickness of 1 μm to 20 μm (e.g. 10 μm).
Referring to fig. 5, a schematic diagram of a bottom-collapsed faraday cage formed by the metal layer 700 and the plurality of conductive arcs 304' of fig. 4 is shown. The bottom-contracted faraday cage (also referred to as "faraday-like cage") formed by the metal layer 700 and the plurality of conductive arcs 304' can be used as an electromagnetic wave shield for the semiconductor chip in the molding layer 400 to ensure efficient operation of the semiconductor chip at an operating frequency between 0.5GHz and 10GHz in the chip package structure.
In one embodiment, to form an effective faraday cage structure, the grounding pads 302 may be densely disposed around the semiconductor chip 200 completely around the semiconductor chip 200, and the degree of densely packing the grounding pads 302 may correspond to the degree of packing or adjacent spacing of the conductive arcs 304', which may depend on the noise frequency band (e.g., electromagnetic frequency band) to be suppressed.
It will be appreciated that the method of manufacturing the chip package structure shown in fig. 1-3 only discloses the fabrication of two chip package structures, but is not limited thereto. The method for manufacturing the chip package structure shown in fig. 1-3 is also suitable for processing a chip package structure comprising tens of semiconductor chips, and forming tens of chip package structures shown in fig. 4-5 after dividing. Therefore, the preparation method for forming the chip packaging structure shown in fig. 4-5 is simple and convenient to implement, low in cost and suitable for mass production.
It will be appreciated that the semiconductor chip 200 of the chip package structure in the above embodiment is illustrated with one chip illustration, but it may also represent a plurality of semiconductor chips, for example, the ground pad 302 may surround the semiconductor chip 200 representing a plurality of semiconductor chips.
In the foregoing, the present invention provides a novel chip package structure having an electromagnetic interference resistance function, including: a package substrate having a first surface and a second surface opposite to each other; the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate; a plurality of grounding pads arranged on the first surface of the packaging substrate and at least partially surrounding the semiconductor chip; a plastic layer covering the first surface of the package substrate and covering the semiconductor chip and the plurality of grounding pads; the metal layer covers the top surface and the side surface of the plastic sealing layer; and the plurality of conductive arcs are buried in the plastic sealing layer and are provided with a first end and a second end which are opposite to each other, wherein the first ends of the plurality of conductive arcs are respectively connected with one of the plurality of grounding pads, and the second ends of the plurality of conductive arcs are exposed from the side surface of the plastic sealing layer and are contacted with the metal layer.
The beneficial effects of the disclosed embodiments lie in providing a novel chip packaging structure, through burying in the plastic sealing layer and contacting the metal layer covering the top surface and side surface of the plastic sealing layer for a plurality of arc wires that the side surface of the plastic sealing layer exposes, the faraday cage that provides anti-electromagnetic interference function has been provided in order to shield electromagnetic interference when having realized the metal layer ground connection function, and then ensure the effective operation of semiconductor chip in chip packaging structure at operating frequency between 0.5GHz-10GHz. Meanwhile, the metal layer for electromagnetic interference (EMI) shielding is not dependent on the fact that grounding is realized in a narrow area at the bottom of the packaging substrate, so that the grounding structure and the grounding cost are simplified, the preparation method of the chip packaging structure is simple and convenient to implement, the cost is low, and the chip packaging structure is suitable for batch production.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that the invention is not limited to the particular embodiments described, but can be modified and altered by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (15)

1. A chip packaging structure, characterized in that: the chip packaging structure comprises:
a package substrate having a first surface and a second surface opposite to each other;
the semiconductor chip is arranged on the first surface of the packaging substrate and is electrically connected with the packaging substrate;
a plurality of grounding pads arranged on the first surface of the packaging substrate and at least partially surrounding the semiconductor chip;
a plastic layer covering the first surface of the package substrate and covering the semiconductor chip and the plurality of grounding pads;
the metal layer covers the top surface and the side surface of the plastic sealing layer; and
the plurality of conductive arcs are buried in the plastic sealing layer and are provided with a first end and a second end which are opposite to each other, wherein the first ends of the plurality of conductive arcs are respectively connected with one of the plurality of grounding pads, the second ends of the plurality of conductive arcs are exposed from the side face of the plastic sealing layer and are contacted with the metal layer, and the plurality of conductive arcs and the metal layer form a Faraday cage structure.
2. The chip package structure according to claim 1, wherein: the semiconductor chip is arranged on the first surface of the packaging substrate, and the semiconductor chip is electrically connected with the package substrate.
3. The chip package structure according to claim 1, wherein: the second ends of the plurality of conductive arcs are located at 1/4 to 3/4 of the height of the side face of the plastic sealing layer.
4. The chip package structure according to claim 1, wherein: the second ends of the plurality of conductive arcs have a pitch of greater than or equal to 50 μm and less than or equal to 500 μm.
5. The chip package structure according to claim 1, wherein: the plurality of conductive arcs have a wire diameter of greater than or equal to 20 and less than or equal to 30 microns.
6. The chip package structure according to claim 1, wherein: the material of the metal layer is selected from the following materials or any combination thereof: aluminum, copper, iron.
7. The chip package structure according to claim 1, wherein: the plurality of conductive arcs are made of gold, silver, aluminum or copper.
8. The chip package structure according to claim 1, wherein: the plurality of ground pads entirely surround the semiconductor chip, and the metal layer and the plurality of conductive arcs form a bottom-shrunk faraday cage.
9. The chip package structure according to claim 1, wherein: the semiconductor chip is electrically connected to the package substrate through wire bonding or flip chip bonding.
10. The chip package structure according to claim 1, wherein: the operating frequency of the semiconductor chip is between 0.5GHz and 10GHz.
11. The chip package structure according to claim 1, wherein: the semiconductor chip includes one or more of the following chips: RF radio frequency chip, GPS location chip, DRAM memory chip, NAND memory chip, bluetooth chip, controller chip.
12. The chip package structure according to claim 1, wherein: the plurality of conductive arcs are 1/4 circular-like arcs.
13. A preparation method of a chip packaging structure is characterized by comprising the following steps: the preparation method of the chip packaging structure comprises the following steps:
providing a package substrate provided with a semiconductor chip, a plurality of grounding pads, a plurality of leads and a wire on a first surface, wherein the wire is arranged along the periphery of the package substrate and at least partially surrounds the semiconductor chip, the plurality of grounding pads are corresponding to the wire and are arranged closer to the semiconductor chip than the wire, and the plurality of grounding pads partially surround the semiconductor chip and are connected with the wire through the plurality of leads;
forming a plastic layer on the first surface of the packaging substrate, wherein the plastic layer encapsulates the wires, the leads and the grounding pads of the semiconductor chip;
cutting the plastic sealing layer and the packaging substrate along the periphery of the semiconductor chip so as to cut the leads between the grounding pads and the wires to form a plurality of conductive arcs embedded in the plastic sealing layer, wherein the plurality of conductive arcs are provided with a first end respectively connected with one of the grounding pads and a second end exposed out of the side surface of the plastic sealing layer; and
and forming a metal layer on the top surface and the side surface of the plastic sealing layer subjected to cutting treatment so as to contact with the second ends of the plurality of conductive arcs exposed from the side surface of the plastic sealing layer, wherein the plurality of conductive arcs and the metal layer form a Faraday cage structure.
14. The method for manufacturing a chip package according to claim 13, wherein: in the step of cutting the plastic layer and the package substrate along the periphery of the semiconductor chip, the plurality of leads are cut from the highest points of the plurality of leads.
15. The method for manufacturing a chip package according to claim 13, wherein: the method also comprises the following steps: a plurality of conductive balls are disposed on the second surface of the package substrate, wherein the plurality of conductive balls are electrically connected to the semiconductor chip.
CN202011499407.5A 2020-12-17 2020-12-17 Chip packaging structure and preparation method thereof Active CN112635436B (en)

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CN109494163A (en) * 2018-11-20 2019-03-19 苏州晶方半导体科技股份有限公司 The encapsulating structure and packaging method of chip
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