CN112632885B - Software and hardware combined verification system and method - Google Patents
Software and hardware combined verification system and method Download PDFInfo
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- CN112632885B CN112632885B CN202011573586.2A CN202011573586A CN112632885B CN 112632885 B CN112632885 B CN 112632885B CN 202011573586 A CN202011573586 A CN 202011573586A CN 112632885 B CN112632885 B CN 112632885B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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Abstract
The invention discloses a software and hardware combined verification system and a method. The system comprises: the system comprises driver software, a system mc simulation-based memory and heterogeneous clusters; the driver software is embedded in a system mc framework; the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification requirement; the memory loads and stores the data to be verified; the heterogeneous cluster extracts data to be verified from the memory according to the driving instruction, calculates to obtain output data and sends the output data to driving software; and the driving software performs combined verification of software and hardware according to the output data. Heterogeneous clusters are simulated through a system mc, driving software is embedded into a system mc framework, a model with the same function as that of hardware is provided for the driving software, the control flow of the driving software to the hardware is realized, early development and debugging of the software are assisted, and standard data are provided for the hardware. The problem of among the prior art software and hardware separate in most system development go on, lead to the long technique of development cycle is solved.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a software and hardware combined verification system and a software and hardware combined verification method.
Background
The integrated circuit verification methods widely used in the industry include: simulation verification based on a verification platform, formal verification and software and hardware collaborative verification. Simulation verification and formal verification are typical verification methods which are centered on hardware design. By establishing a reasonably complete test case, checking whether the RTL hardware design (register level design) can generate corresponding response under specific excitation, and completing unit test, integration test, system test and the like from bottom to top.
The design of the artificial intelligence system of the data flow architecture relates to the close cooperation of software and hardware, because the hardware and software are designed separately in most system developments, if the hardware and software are completely developed separately and then verified, the whole development process is tedious and complicated, during which the upper layer software does not know how to control the hardware, and the lower layer hardware can not obtain accurate data for testing and verification. This results in the integration process finding problems and going back to modify the interfaces of both parties or to recalculate, which is more time and cost intensive.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide a software and hardware combined verification system and a method, and aims to solve the technical problem that in the prior art, software and hardware are separately carried out in most system development, so that the development period is long.
In order to achieve the above object, the present invention provides a software and hardware combined verification system, including: the system comprises driving software, a memory based on systemc simulation and a heterogeneous cluster based on the systemc simulation, wherein the driving software is embedded in a systemc framework of the memory corresponding to the heterogeneous cluster;
the driving software is used for sending a driving instruction to the heterogeneous cluster according to a preset verification requirement;
the memory is used for loading data to be verified and storing the data to be verified;
the heterogeneous cluster is used for extracting the data to be verified from the storage according to the driving instruction, calculating to obtain output data according to the data to be verified, and sending the output data to the driving software;
and the driving software is used for performing combined verification of software and hardware according to the output data.
Optionally, the driver software, the memory, and the heterogeneous cluster communicate with a transaction level bus through a socket.
Optionally, the heterogeneous cluster comprises an engine unit comprising a direct memory access and an engine core;
the direct memory access is used for extracting data to be verified from the memory according to the driving instruction and sending the data to be verified to the engine core;
the engine core is used for obtaining output data through calculation according to the data to be verified and sending the output data to the direct memory for access;
the direct memory access is used for sending the output data to the driving software.
Optionally, the engine unit further comprises a processor;
the direct memory access is also used for determining a processor instruction according to the driving instruction and sending the processor instruction to the processor;
and the processor is used for receiving the processor instruction and starting the engine core according to the processor instruction.
Optionally, the engine unit further comprises a status register;
the processor is further configured to send a configuration signal to the status register when receiving the processor instruction;
the state register is used for receiving configuration parameters from the driving software according to the configuration signals and adjusting according to the configuration parameters to obtain static engine parameters;
and the engine core is also used for calculating to obtain output data according to the data to be verified and the static engine parameters and sending the output data to the direct memory for access.
Optionally, the number of the engine units is N, and N is larger than or equal to 1.
Optionally, the data to be verified includes at least one of a correlation coefficient, a bias term, and input data of a preset neural network model.
Optionally, the data to be verified further includes data located at a direct connection layer in the preset neural network model.
Optionally, the heterogeneous cluster is further configured to send the output data to the storage, so that the storage stores the output data.
In addition, in order to achieve the above object, the present invention further provides a software and hardware joint verification method, which is applied to the above software and hardware joint verification system, and the software and hardware joint verification system includes: the system comprises driving software, a memory based on systemc simulation and a heterogeneous cluster based on the systemc simulation, wherein the driving software is embedded in a systemc framework of the memory corresponding to the heterogeneous cluster;
the software and hardware combined verification method comprises the following steps:
the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification requirement;
the memory loads data to be verified and stores the data to be verified;
the heterogeneous cluster extracts the data to be verified from the storage according to the driving instruction, calculates the data to be verified to obtain output data and sends the output data to the driving software;
and the driving software performs combined verification of software and hardware according to the output data.
The software and hardware combined verification system comprises: the system comprises driving software, a memory based on system mc simulation and a heterogeneous cluster based on system mc simulation, wherein the driving software is embedded in a system mc framework corresponding to the heterogeneous cluster in the memory; the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification requirement; the memory loads the data to be verified and stores the data to be verified; the heterogeneous cluster extracts data to be verified from the memory according to the driving instruction, calculates the data to be verified to obtain output data and sends the output data to driving software; and the driving software performs combined verification of software and hardware according to the output data. The heterogeneous cluster is simulated by the system mc, the driving software is embedded into the system mc frame, a model with the same function as the hardware is provided for the software, the control flow of the software to the hardware is realized, and the software and hardware combined verification system provided by the invention can assist the early development and debugging of the software and provide standard data for the hardware. The invention simulates the hardware architecture, completely simulates the control flow and the data flow of the hardware during the operation, and solves the technical problem of long development period caused by the fact that the software and the hardware are separately carried out in most system development in the prior art.
Drawings
FIG. 1 is a block diagram of a first embodiment of a software and hardware combined verification system according to the present invention;
FIG. 2 is a schematic diagram illustrating a comparison of development cycles of an embodiment of a combined software and hardware verification system according to the present invention;
FIG. 3 is a block diagram of a second embodiment of the software and hardware combined verification system according to the present invention;
FIG. 4 is a schematic diagram illustrating engine unit data processing according to an embodiment of the software and hardware joint verification system of the present invention;
FIG. 5 is a block diagram of a software and hardware combined verification system according to a third embodiment of the present invention;
FIG. 6 is a schematic diagram of a neural network computing process according to an embodiment of the software and hardware combined verification system of the present invention;
FIG. 7 is a flowchart illustrating a software and hardware combined verification method according to a first embodiment of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
50 | |
| 20 | |
60 | |
| 30 | |
70 | Processor with a memory having a plurality of |
| 40 | |
80 | Status register |
The implementation, functional features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
An embodiment of the present invention provides a software and hardware combined verification system, and referring to fig. 1, fig. 1 is a structural block diagram of a first embodiment of the software and hardware combined verification system of the present invention.
In this embodiment, the software and hardware combined verification system driver 10, the memory 20 based on systemc simulation, and the heterogeneous cluster 30 based on systemc simulation, where the driver 10 is embedded in a system mc framework corresponding to the memory 20 and the heterogeneous cluster 30;
the driver software 10 is configured to send a driving instruction to the heterogeneous cluster 30 according to a preset verification requirement. In this embodiment, the system mc is a software/hardware co-design language, and the driver software 10 is embedded in the system mc framework as the software that interacts most directly with the hardware, and is used as the initiator of the whole system to access and control the heterogeneous cluster 30. The preset verification requirements may be function verification, performance verification, and matching verification, the software and hardware development processes are different, the preset verification requirements are different, and the preset verification requirements also depend on software codes corresponding to the driver software 10 and a control instruction sent by upper-layer software through the driver software 10, for example, when software development matched with hardware is performed, the semi-finished software sends a start instruction to the heterogeneous cluster 30 through the driver software 10, and whether the simulation hardware of the heterogeneous cluster 30 can be normally started is determined. For another example, in the development and design process, the calculation speed of the hardware is tested, and the calculation time of the hardware is monitored by the driver software 10 to determine the calculation performance of the hardware. The present embodiment does not impose any limitation on the predetermined verification requirement. The driving instruction is a starting instruction or a verification instruction for packaging in advance through a function and is used for simulating an actual software and hardware combined verification scene, and the driving instruction can be compiled through software codes according to an actual hardware test case.
It should be noted that the driver software 10 includes information about hardware devices, in this embodiment, the hardware devices are simulated heterogeneous clusters 30, and the driver software 10 functions to correctly identify, manage, access, and control the heterogeneous clusters 30.
The memory 20 is configured to load data to be verified and store the data to be verified. In this embodiment, the memory 20 adopts a double data rate synchronous dynamic random access memory (DDR) 20, which is used to store data that needs to be used by the heterogeneous cluster 30, and the driver software 10 may send data to be verified to the memory 20.
The heterogeneous cluster 30 is configured to extract the data to be verified from the memory 20 according to the driving instruction, calculate output data according to the data to be verified, and send the output data to the driving software 10. In this embodiment, the heterogeneous cluster 30 may be an engine unit 40, which carries calculation and input/output tasks of a neural network, when receiving a driving instruction, the heterogeneous cluster 30 extracts data to be verified from the memory 20, in a specific implementation, when extracting data, the engine is started to perform calculation while outputting data, so as to achieve an effect of a data stream, when the heterogeneous cluster 30 does not complete calculation, the output data of this stage is transmitted to the memory 20 to be stored, when performing calculation of the next stage, corresponding input data is extracted from the memory 20 again, the input data is calculated until final output data is obtained, and the final output data is sent to the driving software 10.
The driver software 10 is configured to perform joint verification of software and hardware according to the output data. In this embodiment, the driver software 10 completes the joint verification between the software and the hardware according to the output data and the operating state data calculated by the heterogeneous cluster 30, so as to assist the early-stage development of the driver software 10. The driver software 10 manages the heterogeneous cluster 30, the operation result of the heterogeneous cluster 30 is kept consistent with the actual hardware, standard data is provided for the hardware according to the operation result,
referring to fig. 2, fig. 2 is a schematic diagram comparing a development cycle of an embodiment of the software and hardware combined verification system of the present invention, where the model development in fig. 2 is the development of the software and hardware combined verification system provided in this embodiment, and it can be seen from the diagram that software and hardware cannot be well paralleled in a traditional software and hardware development process, and software can only perform corresponding hardware-related development after hardware design is completed, and driver-class software is particularly preferred. In the development process of the virtual prototype, the addition of the model (model) makes the whole development process more compact and efficient. The system mc model provided by the embodiment is used as a model with a high abstraction level, so that the development of the driver software follows the steps of the hardware, and the hardware can be subjected to integration test (or system test) almost without waiting for the software after the development. The software and hardware combined verification system is established at the early development stage of a system on chip (soc), at the moment, the CPU type is undetermined, the IP core type is undetermined, and a bottom operating system is also undetermined.
Further, the driver software 10, the memory 20, and the heterogeneous cluster 30 communicate with a transaction level bus through a socket. In this embodiment, the driver software 10, the memory 20, and the heterogeneous cluster 30 communicate via a transaction-level bus, are connected to the transaction-level bus via a socket, and complete the simulation of software and hardware interfaces using a transaction-level bus (TLM bus) and a socket. This interface abstracts away the various protocols of the bus and the communication between the modules is implemented using methods called by functions. Therefore, the module does not need to pay attention to port definition and port time sequence, the modeling speed is improved, and the final model operation speed is optimized.
The software and hardware combined verification system comprises: the system comprises driving software, a memory based on systemc simulation and a heterogeneous cluster based on the systemc simulation, wherein the driving software is embedded in a systemc framework of the memory corresponding to the heterogeneous cluster; the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification requirement; the memory loads the data to be verified and stores the data to be verified; the heterogeneous cluster extracts data to be verified from the memory according to the driving instruction, calculates to obtain output data according to the data to be verified, and sends the output data to the driving software; and the driving software performs combined verification of software and hardware according to the output data. The heterogeneous cluster is simulated by the system mc, the driving software is embedded into the system mc frame, a model with the same function as the hardware is provided for the software, the control flow of the software to the hardware is realized, and the software and hardware combined verification system provided by the invention can assist the early development and debugging of the software and provide standard data for the hardware. The invention simulates the hardware architecture, completely simulates the control flow and the data flow of the hardware during the operation, and solves the technical problem of long development period caused by the fact that the software and the hardware are separately carried out in most system development in the prior art.
Based on the first embodiment of the software and hardware joint verification system, a second embodiment is provided, and referring to fig. 3, fig. 3 is a structural block diagram of the second embodiment of the software and hardware joint verification system of the present invention.
As shown in fig. 3, in the software and hardware joint verification system according to the embodiment of the present invention, the heterogeneous cluster 30 includes an engine unit 40, where the engine unit 40 includes a direct memory access 50 and an engine core 60;
the direct memory access 50 is configured to extract data to be verified from the memory 20 according to the driving instruction, and send the data to be verified to the engine core 60. In this embodiment, the Direct Memory Access (DMA) 50 is a unique module for transferring data inside the system, and the DMA module is responsible for carrying data from the Memory 20DDR to the inside of the engine unit 40, or transferring data inside the engine unit 40 to the DDR or the driver software 10.
The engine core 60 is configured to calculate output data according to the data to be verified, and send the output data to the direct memory access 50. In this embodiment, the engine core 60 is responsible for processing operators of the neural network.
The direct memory access 50 is used to send the output data to the driver software 10.
The engine unit 40 further comprises a processor 70;
the direct memory access 50 is further configured to determine a processor 70 instruction according to the driving instruction, and send the processor 70 instruction to the processor 70. In this embodiment, the driver software 10 determines the instruction of the processor 70 through DMA, and the instruction is compiled off-line and then transferred to the processor 70 through DMA, so that the processor 70 monitors and directly controls the start and stop of the engine unit 40.
The processor 70 is configured to receive the processor 70 instruction, and start the engine core 60 according to the processor 70 instruction. In this embodiment, the processor 70 (uc) may adopt an arm core series processor 70, which is used to take over the functions of the upper layer software, and to allocate and control the start and stop of the engine.
The engine unit 40 further comprises a status register 80;
the processor 70 is further configured to send a configuration signal to the status register 80 when receiving the instruction of the processor 70. In this embodiment, the processor 70 starts to configure the registers after being started by the driver software 10.
The status register 80 is configured to receive the configuration parameters from the driver software 10 according to the configuration signals, and adjust according to the configuration parameters to obtain static engine parameters. In this embodiment, the status register 80 is used for receiving the configuration of the driver software 10, and stores the engine static parameters, which will remain unchanged during the calculation of each layer of neural network. During the development and design process, different calculation contents are realized by putting different programs and parameters into the state register 80.
The engine core 60 is further configured to calculate output data according to the data to be verified and the static engine parameters, and send the output data to the direct memory access 50. In this embodiment, the DMA extraction data, the calculation of the engine core 60, and the DMA output data may be performed synchronously, so as to achieve an effect of data streaming, the DMA extracts parameters required by calculation of two neural networks, namely a correlation Coefficient (Coefficient) and a bias term (bias), from the DDR, and the data of a direct connection layer is also extracted when a direct connection layer (short) is preset in the neural network. The input data is then extracted for calculation. Finally, the output data is transferred back to the DDR through DMA or is handed to the driver software 10 for processing. The engine core 60 extracts relevant engine static parameters from the status register 80, and distributes parameters such as a correlation coefficient corresponding to the neural network to each component for calculation.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating data processing performed by the Engine unit 40 according to an embodiment of the software and hardware combined verification system of the present invention, in fig. 4, software represents an operation of the driver software 10, uc _ read represents a read operation of the processor 70, DMA _ read represents a read operation of the memory 20, uc _ write represents a write operation of the processor 70, DMA _ write represents a write operation of the memory 20, engine represents an operation of the Engine core 60, inst represents an instruction, coef represents a correlation Coefficient (Coefficient), bias represents a bias term (bias), sc represents a direct link layer data (shortcut), data represents input data, calc represents a calculation process, and result represents an output result. As can be seen from fig. 4, the software obtains the instruction corresponding to the processor 70 through the DMA according to the packaged function, and the instruction of the processor 70 is compiled offline and then sent to the processor 70 through the DMA, so as to start the processor 70, obtain the correlation coefficient, the offset item, the direct connection layer data and the input data through the DMA, respectively, and transmit the obtained data to the engine core 60 for calculation, and feed the result back to the software through the DMA, in this process, the processor 70 always reads various parameters, and implements the allocation and control of the parameters in the engine unit 40. Figure 4 illustrates one of the most basic and classical cases. The data processing process of the engine unit 40 may also be performed without starting the processor 70, which is not limited by the embodiment.
The heterogeneous cluster in the software and hardware combined verification system of the embodiment comprises an engine unit, wherein the engine unit comprises a direct memory access and an engine core; the direct memory access extracts data to be verified from the memory according to the driving instruction, and sends the data to be verified to the engine core; the engine core calculates to obtain output data according to the data to be verified and sends the output data to the direct memory for access; the direct memory access sends the output data to the driving software; and the driving software carries out verification according to the output data. The real modules of the hardware are simulated through a systemc model, the functions of the hardware are equal to those of the hardware, the whole heterogeneous cluster is simulated, register level accuracy is achieved, and the software and hardware combined verification system based on the embodiment can assist development and debugging in the early stage of software and provide standard data for the hardware. The hardware architecture is simulated by the embodiment, the control flow and the data flow of the hardware are completely simulated during operation, and the technical problem that in the prior art, software and hardware are separately carried out in most system development, so that the development period is long is solved.
Based on the first embodiment and the second embodiment of the software and hardware joint verification system, referring to fig. 5, fig. 5 is a structural block diagram of a third embodiment of the software and hardware joint verification system according to the present invention.
In this embodiment, the number of the engine units 40 is N, where N is greater than or equal to 1. In this embodiment, referring to fig. 5, 2 engine units 40 in fig. 5 may be adopted, and in a specific implementation, other numbers may be adopted, which is not limited in this embodiment.
It can be understood that, the CAISA engine and the PP (precision Processing) engine are adopted as the engine unit 40 of this embodiment, which bear the calculation and input/output tasks of the neural network, and the CAISA engine and the PP engine belong to the same data stream architecture, and the requirements to be met are not consistent, the CAISA engine is a neural network calculation engine based on int8 or int16, which mainly processes the mainstream neural network operator, the CAISA performance is high, and the PP engine is based on fp (floating point) operation, which processes some operators that must use fp, and the performance is inferior to the CAISA. Both engines have a pool of supported operators that includes both the same operators that are supported, as well as operators that are supported only within one engine. When in use, the driver software 10 distributes operators to the CAISA engine or the PP engine according to the preset verification requirements, and each engine needs to be correctly set before starting.
The data to be verified comprises at least one of a correlation coefficient, a bias item and input data of a preset neural network model. In this embodiment, the preset neural network model is a pre-configured neural network computational model, and the data to be verified includes correlation coefficients, bias terms, and input data corresponding to each layer of the network layer required for computing the neural network. Referring to fig. 6, fig. 6 is a schematic diagram illustrating a neural network computing process according to an embodiment of the software and hardware combined verification system of the present invention, fig. 6 is only used as an example, the corresponding process does not represent a separate time, and some processes and operations may be performed in parallel in an actual process, for example, data is extracted from storage, an engine is started to perform computation, and data is output, so as to achieve the effect of data flow.
The data to be verified also comprises data located in a direct connection layer in the preset neural network model. In this embodiment, when the driver software 10 detects that the direct connection layer data is included in the preset neural network model, the direct connection layer data is transmitted to the memory 20 to be stored, and when the engine unit 40 performs neural network calculation, the direct connection layer data is extracted from the memory 20 to be calculated.
The heterogeneous cluster 30 is further configured to send the output data to the storage 20, so that the storage 20 stores the output data. In this embodiment, the heterogeneous cluster 30 may send the output data to the memory 20 for storage, for example, after a layer of data is calculated on the preset neural network model, the output data of the layer is sent to the memory 20 for storage, so that when the next layer of data is calculated, the output data is taken as input data for extraction, and calculation is performed again according to the input data.
In the software and hardware combined verification system of the embodiment, the number of the engine units is N, N is greater than or equal to 1, and at least one of a correlation coefficient, a bias term and input data of a preset neural network model is extracted from a memory according to an operator pool supported by the plurality of engine units, so that neural network calculation is realized. The real modules of the hardware are simulated through a systemc model, the functions of the hardware are equal to those of the hardware, and based on the software and hardware combined verification system provided by the embodiment, early architecture exploration and algorithm realization can be provided for the realization of the hardware on a neural network. The hardware architecture is simulated by the embodiment, the control flow and the data flow of the hardware are completely simulated during operation, and the technical problem that in the prior art, software and hardware are separately carried out in most system development, so that the development period is long is solved.
An embodiment of the present invention provides a software and hardware joint verification method, and referring to fig. 7, fig. 7 is a flowchart illustrating a first embodiment of the software and hardware joint verification method according to the present invention.
The software and hardware joint verification method is applied to the software and hardware joint verification system as described above, and the software and hardware joint verification system comprises: the system comprises driving software, a memory based on systemc simulation and a heterogeneous cluster based on the systemc simulation, wherein the driving software is embedded in a systemc framework of the memory corresponding to the heterogeneous cluster;
the software and hardware combined verification method comprises the following steps:
step S10: and the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification requirement.
It is understood that systemc is a software/hardware co-design language, and driver software is embedded in the system mc framework as the most direct software to interact with hardware, and as the initiator of the whole system, accesses and controls heterogeneous clusters. The preset verification requirements can be function verification, performance verification and matching verification, the software and hardware development processes are different, the preset verification requirements also depend on software codes corresponding to the driver software and control instructions sent by upper-layer software through the driver software, for example, when software development matched with hardware is performed, the semi-finished software sends a starting instruction to the heterogeneous cluster through the driver software, and whether the simulation hardware of the heterogeneous cluster can be normally started is judged. For another example, in the development and design process, the calculation speed of the hardware is tested, and the calculation time of the hardware is monitored by the driving software to judge the calculation performance of the hardware. The present embodiment does not impose any limitation on the predetermined verification requirement. The driving instruction is a starting instruction or a verification instruction for packaging in advance through a function and is used for simulating an actual software and hardware combined verification scene, and the driving instruction can be compiled through software codes according to an actual hardware test case.
It should be noted that the driver software includes information about the hardware device, and in this embodiment, the related hardware device is an emulated heterogeneous cluster, and the driver software is used to correctly identify, manage, access, and control the heterogeneous cluster.
Step S20: and the memory loads data to be verified and stores the data to be verified.
It can be understood that the memory adopts a double data rate synchronous dynamic random access memory (DDR) for storing data required to be used by the heterogeneous cluster, and the data to be verified can be sent to the memory by the driver software.
Step S30: and the heterogeneous cluster extracts data to be verified from the memory according to the driving instruction, calculates the data to be verified to obtain output data and sends the output data to the driving software.
It should be noted that the heterogeneous cluster may be an engine unit, and carries calculation and input/output tasks of the neural network, when receiving a driving instruction, the heterogeneous cluster extracts data to be verified from the memory, in a specific implementation, when extracting data, the engine is started to perform calculation while outputting data, so as to achieve an effect of a data stream, when the heterogeneous cluster does not complete calculation, the heterogeneous cluster transmits the output data of this stage to the memory to be stored, and when performing calculation of the next stage, corresponding input data is extracted from the memory again, and the input data is calculated until final output data is obtained and sent to the driving software.
Step S40: and the driving software performs combined verification of software and hardware according to the output data.
It can be understood that the driver software completes the joint verification between the software and the hardware according to the output data obtained by the heterogeneous cluster calculation and the running state data, so as to assist the early development of the driver software. The driving software manages the heterogeneous cluster, the operation result of the heterogeneous cluster is kept consistent with the actual hardware, standard data is provided for the hardware according to the operation result,
referring to fig. 2, fig. 2 is a schematic diagram comparing a development cycle of an embodiment of the software and hardware combined verification system of the present invention, where the model development in fig. 2 is the development of the software and hardware combined verification system provided in this embodiment, and it can be seen from the diagram that software and hardware cannot be well paralleled in a traditional software and hardware development process, and software can only perform corresponding hardware-related development after hardware design is completed, and driver-class software is particularly preferred. In the development process of the virtual prototype, the addition of the model (model) makes the whole development process more compact and efficient. The system mc model provided by the embodiment is used as a model with a high abstraction level, so that the development of the driver software follows the steps of the hardware, and the hardware can perform integration test (or system test) almost without waiting for the software after the development. The software and hardware combined verification system is established at the early development stage of a system on chip (soc), at the moment, the CPU type is undetermined, the IP core type is undetermined, and a bottom operating system is also undetermined.
Further, the driver software, the memory, and the heterogeneous cluster communicate with a transaction level bus through a socket. In this embodiment, the driver software, the memory, and the heterogeneous cluster communicate with each other through a transaction-level bus, are connected to the transaction-level bus through a socket, and complete the simulation of software and hardware interfaces by using a transaction-level bus (TLM bus) and a socket. This interface abstracts away the various protocols of the bus and the communication between the modules is implemented using methods called by functions. Therefore, the module does not need to pay attention to port definition and port time sequence, the modeling speed is improved, and the final model operation speed is optimized.
The software and hardware combined verification system comprises: the system comprises driving software, a memory based on system mc simulation and a heterogeneous cluster based on system mc simulation, wherein the driving software is embedded in a system mc framework corresponding to the heterogeneous cluster in the memory; the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification requirement; the memory loads the data to be verified and stores the data to be verified; the heterogeneous cluster extracts data to be verified from the memory according to the driving instruction, calculates to obtain output data according to the data to be verified, and sends the output data to the driving software; and the driving software performs combined verification of software and hardware according to the output data. The heterogeneous cluster is simulated by the system mc, the driving software is embedded into the system mc frame, a model with the same function as the hardware is provided for the software, the control flow of the software to the hardware is realized, and the software and hardware combined verification system provided by the invention can assist the early development and debugging of the software and provide standard data for the hardware. The invention simulates hardware architecture, completely simulates control flow and data flow of hardware during operation, and solves the technical problem of long development period caused by the separation of software and hardware in most system development in the prior art.
In an embodiment, the heterogeneous cluster includes an engine unit including a direct memory access and an engine core;
step S30, including:
the direct memory access extracts data to be verified from the memory according to the driving instruction and sends the data to be verified to the engine core;
the engine core calculates to obtain output data according to the data to be verified and sends the output data to the direct memory for access;
the direct memory access sends the output data to the driver software.
In an embodiment, the engine unit further comprises a processor;
after the direct memory access extracts data to be verified from the memory according to the driving instruction and sends the data to be verified to the engine core, the method further comprises:
the direct memory access determines a processor instruction according to the driving instruction, and sends the processor instruction to the processor;
and the processor receives the processor instruction and starts the engine core according to the processor instruction.
In an embodiment, the engine unit further comprises a status register;
the direct memory access determines a processor instruction according to the driving instruction, and after sending the processor instruction to the processor, the method further comprises:
the processor sends a configuration signal to the status register when receiving the processor instruction;
the state register receives configuration parameters from the driving software according to the configuration signals, and adjusts the configuration parameters to obtain static parameters of the engine;
correspondingly, the engine core calculates to obtain output data according to the data to be verified, and sends the output data to the direct memory access, including:
and the engine core calculates to obtain output data according to the data to be verified and the static engine parameters, and sends the output data to the direct memory for access.
In one embodiment, the number of the engine units is N, and N is larger than or equal to 1.
In an embodiment, the data to be verified includes at least one of a correlation coefficient, a bias term and input data of a preset neural network model.
In an embodiment, the data to be verified further includes data located at a direct connection layer in the preset neural network model.
In an embodiment, after step S40, the method further includes: and the heterogeneous cluster sends the output data to the memory so that the memory stores the output data.
Further, it is to be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or system comprising the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention or portions thereof that contribute to the prior art may be embodied in the form of a software product, where the computer software product is stored in a storage medium (e.g. a Read Only Memory (ROM)/RAM, a magnetic disk, and an optical disk), and includes several instructions for enabling a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
Claims (9)
1. A combined software and hardware validation system, comprising: the system comprises driving software, a memory based on system mc simulation and a heterogeneous cluster based on system mc simulation, wherein the driving software is embedded in a system mc framework of the memory corresponding to the heterogeneous cluster;
the driving software is used for sending a driving instruction to the heterogeneous cluster according to a preset verification requirement;
the memory is used for loading data to be verified and storing the data to be verified;
the heterogeneous cluster is used for extracting the data to be verified from the storage according to the driving instruction, calculating to obtain output data according to the data to be verified, and sending the output data to the driving software;
the driving software is used for performing combined verification of software and hardware according to the output data;
wherein the heterogeneous cluster comprises an engine unit comprising a direct memory access and an engine core;
the direct memory access is used for extracting data to be verified from the memory according to the driving instruction and sending the data to be verified to the engine core;
the engine core is used for obtaining output data through calculation according to the data to be verified and sending the output data to the direct memory for access;
the direct memory access is used for sending the output data to the driving software.
2. The software and hardware joint validation system of claim 1, wherein the driver software, the memory, and the heterogeneous cluster communicate with a transaction level bus through a socket.
3. The combined software and hardware validation system of claim 1, wherein the engine unit further comprises a processor;
the direct memory access is also used for determining a processor instruction according to the driving instruction and sending the processor instruction to the processor;
and the processor is used for receiving the processor instruction and starting the engine core according to the processor instruction.
4. The combined software and hardware validation system of claim 3, wherein the engine unit further comprises a status register;
the processor is further configured to send a configuration signal to the status register when receiving the processor instruction;
the state register is used for receiving configuration parameters from the driving software according to the configuration signals and adjusting according to the configuration parameters to obtain static engine parameters;
and the engine core is also used for calculating to obtain output data according to the data to be verified and the static engine parameters and sending the output data to the direct memory for access.
5. The combined hardware and software verification system of claim 1, wherein the number of engine units is N, and N ≧ 1.
6. The software and hardware combined verification system according to any one of claims 1 to 5, wherein the data to be verified comprises at least one of correlation coefficients, bias terms and input data of a preset neural network model.
7. The system of claim 6, wherein the data to be verified further comprises data in a direct connection layer in the predetermined neural network model.
8. The combined software and hardware validation system of any of claims 1-5, wherein the heterogeneous cluster is further configured to send the output data to the memory so that the memory saves the output data.
9. A software and hardware joint verification method, which is applied to the software and hardware joint verification system according to any one of claims 1 to 8, and which comprises: the system comprises driving software, a memory based on systemc simulation and a heterogeneous cluster based on the systemc simulation, wherein the driving software is embedded in a systemc framework of the memory corresponding to the heterogeneous cluster;
the software and hardware combined verification method comprises the following steps:
the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification requirement;
the memory loads data to be verified and stores the data to be verified;
the heterogeneous cluster extracts the data to be verified from the storage according to the driving instruction, calculates to obtain output data according to the data to be verified, and sends the output data to the driving software;
the driving software carries out combined verification of software and hardware according to the output data;
wherein the heterogeneous cluster comprises an engine unit comprising a direct memory access and an engine core;
the heterogeneous cluster extracts the data to be verified from the storage according to the driving instruction, calculates to obtain output data according to the data to be verified, and sends the output data to the driving software, and the method comprises the following steps:
the direct memory access extracts data to be verified from the memory according to the driving instruction and sends the data to be verified to the engine core;
the engine core calculates to obtain output data according to the data to be verified and sends the output data to the direct memory for access;
the direct memory access sends the output data to the driver software.
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