CN112631723A - Byte code simplified instruction set and resource limited device of micro-operation system - Google Patents
Byte code simplified instruction set and resource limited device of micro-operation system Download PDFInfo
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Abstract
The invention discloses a simplified instruction set and resource-limited device of a micro-operation system bytecode, wherein the simplified instruction set comprises: the first instruction consists of an operation code, and the operation code contains parameter information of the first instruction in a hidden way; the second instruction is a high-frequency instruction with multiple instruction formats; a third instruction, wherein the third instruction comprises instructions with different instruction formats based on different parameter numbers; the fourth instruction comprises an instruction of a common data type and an instruction of an uncommon data type, wherein the instruction of the common data type has a plurality of instruction formats, and the instruction of the uncommon data type has one instruction format; a fifth instruction, the fifth instruction being an instruction having a single-byte constant pool index; and the sixth instruction is a macro instruction. The instruction set of the invention reduces the size of the byte code as much as possible, thereby not only reducing the requirement of persistent storage of the chip, but also improving the execution efficiency of the code.
Description
Technical Field
The invention relates to the technical field of virtual machine instruction sets, in particular to a byte code simplified instruction set and a resource limited device of a micro-operating system.
Background
The Java programming language is object-oriented, and "classes" describe a collection of data (described by fields), and the various methods used to operate on the data, the fields and methods of the classes describe the state and behavior of an object. Because of resource limitation, the security chips of the smart SE (Secure Element) and the MCU (Micro Controller Unit) often use a Java Card virtual machine at present, and can run an application program written in Java language. The application program written by Java language needs to generate a Class file through a Java compiler, then the Class file is converted into a CAP file through a conversion tool provided by a Java Card, and the CAP file is downloaded into a chip and executed by a Java Card virtual machine. The Java Card instruction set is based on an operand stack, which has a problem of poor execution performance compared to the bytecode of the register-based instruction set.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a byte code simplified instruction set and resource limited device of a micro-operating system, which is used for resource limited devices such as intelligent SE (application sequence) chips and safety MCU (microprogrammed control Unit) chips and various object-oriented programs neutral in an architecture, reduces the size of byte codes as much as possible, can reduce the requirement of persistent storage of the chips and can improve the execution efficiency of the codes.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a reduced instruction set of micro-operating system bytecodes, the reduced instruction set comprising:
the first instruction consists of an operation code, and the operation code implicitly contains parameter information of the first instruction;
a second instruction, which is a high-frequency instruction with multiple instruction formats;
a third instruction, the third instruction comprising instructions based on different numbers of parameters and having different instruction formats;
a fourth instruction, including an instruction of a common data type and an instruction of an uncommon data type, the instruction of the common data type having multiple instruction formats, and the instruction of the uncommon data type having one instruction format;
a fifth instruction, the fifth instruction being an instruction having a single-byte constant pool index;
a sixth instruction, the sixth instruction being a macro instruction.
Further, as described above for the reduced instruction set, the first instruction comprises:
instructions that imply both operands and register numbers into the opcode;
instructions that imply register numbers into the opcodes;
instructions to imply constant operands into opcodes;
an array member access instruction for hiding the member type of the array member into the operation code;
the type and parameters of the method call are implicit to the instruction in the opcode.
Further, as described above for the reduced instruction set, the second instructions include:
common arithmetic operation instructions having a plurality of operation formats;
an array member access instruction in a 4-bit register format is adopted;
an array creating instruction for hiding the member type of the array member into the operation code;
based on the equal and unequal comparison results, branch instructions having multiple instruction formats.
Further, as described above for the reduced instruction set, the third instruction includes:
based on different parameter numbers, static method call instructions with different instruction formats;
virtual method call instructions with different instruction formats based on different parameter numbers;
based on the number of different parameters, private instance method call instructions with different instruction formats.
Further, as in the reduced instruction set described above, the fourth instruction comprises:
the instructions of common data types include instructions of short data types;
instructions of the infrequent data type include instructions of the int data type.
Further, as in the reduced instruction set described above, the fifth instruction includes:
a static method call instruction with a single-byte constant pool index;
a virtual method call instruction with a single-byte constant pool index;
a static domain access instruction with a single-byte constant pool index;
example Domain Access instructions with a one-byte constant pool index.
Further, as in the reduced instruction set described above, the sixth instruction comprises:
replacing the formed macroinstruction based on the static method call instruction;
and merging the formed macroinstructions based on the adjacent instructions.
A resource-constrained device on which is run a virtual machine for executing the reduced instruction set of any one of claims 1-7.
The invention has the beneficial effects that: the invention designs a register-based virtual machine instruction set which is used for resource-limited devices such as intelligent SE (secure element) chips and safe MCU (microprogrammed control unit) chips, is object-oriented and various programs neutral in a system structure, reduces the size of byte codes as much as possible, can reduce the requirement of persistent storage of the chips and can improve the execution efficiency of the codes.
Drawings
FIG. 1 is a block diagram of a reduced instruction set for micro operating system bytecode according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
An instruction consists of a one byte length opcode that specifies the operation to be performed, followed by zero or more operands that represent the values to be operated on. Each element in the instruction format description represents a byte. The registers in the instruction are 16 bits and can represent bootean, byte, short, reference type and return Address, and int type requires two consecutive numbered register pair representations. null refers to a value of short type 0, i.e., (object) null ═ 0. The last registers in the stack frame of the method call are used to pass the method parameters. The invention provides a register-based TGoMOS virtual machine instruction set (hereinafter, a simplified instruction set), which is used for resource-limited devices such as intelligent SE (programmable element array) chips and safety MCU (microprogrammed control Unit) chips, is oriented to various programs with neutral system structures, is specially designed for virtual machines of the resource-limited devices such as the intelligent SE chips and the safety MCU chips, reduces the size of byte codes as much as possible, can reduce the requirement of persistent storage of the chips and can improve the execution efficiency of the codes.
As shown in fig. 1, an embodiment of the present invention provides a reduced instruction set of a micro operating system bytecode, where the reduced instruction set includes: the instruction processing device comprises a first instruction, a second instruction, a third instruction, a fourth instruction, a fifth instruction and a sixth instruction.
The first instruction consists of an operation code, and the operation code contains parameter information of the first instruction in a hidden mode. The first instructions include:
a. instructions that imply both operands and register numbers into the opcode, such as the constant assignment instructions of Table 1 below.
TABLE 1
As can be seen from table 1, constant assignment is a very frequent operation, and the length of the bytecode of the method can be significantly reduced by using the above coding.
b. Instructions that imply register numbers into the opcodes, such as the constant assignment instruction of table 2, the static domain access instruction of table 3, the return method call non-object result instruction of table 4, the return method call object reference result instruction of table 5, and the array member access instruction of table 6.
TABLE 2
TABLE 3
TABLE 4
TABLE 5
TABLE 6
c. Instructions to imply constant operands into opcodes;
d. an array member access instruction for hiding the member type of the array member into the operation code;
e. the type and parameters of the method call are implicit to the instruction in the opcode.
The reduced instruction set of the present invention also includes a second instruction that is a high frequency instruction having a plurality of instruction formats. The second instructions include:
a. common arithmetic operation instructions having a variety of operation formats, such as the add operation instruction of Table 7 and the AND operation instruction of Table 8.
TABLE 7
| Instruction format | Mnemonic symbol | Description of the invention |
| op A|B | add/2r rA rB | rA＝rA+rB |
| op A|B | add-c4/1r rA B | rA＝rA+B |
| op A|B CC | add-c8 rA rB CC | rA＝rB+CC |
| op AA B|C | add/R44 rAA rB rC | rAA＝rB+rC |
| op AA BB CC | add rAA rBB rCC | rAA＝rBB+rCC |
| op A|B | iadd/2r rA rB | rA＝rA+rB |
| op A|B CC | iadd-c8 rA rB CC | rA＝rB+CC |
| op A|B CCh CCl | iadd-c16 rA rB CCCC | rA＝rB+CCCC |
| op AA BB CC | iadd rAA rBB rCC | rAA＝rBB+rCC |
Since the add operation is more common, providing multiple operation formats can reduce the size of the bytecode. Using other instructions may reduce the instruction length by 1 or 2 bytes compared to 4 bytes for add rAA rBB/iadd rAA rBB.
TABLE 8
| Instruction format | Mnemonic symbol | Description of the invention |
| op A|B | and/2r rA rB | rA＝rA&rB |
| op A|B | and-c4rA，B | rA＝rA&B |
| op A|B | s2b2s rA rB | rA＝rB&0x00FF |
| op A|B CC | and-c8 rA，rB，CC | rA＝rB&CC |
| op AA B|C | and/R44 rAA rB rC | rAA＝rB&rC |
| op A|B CCh CCl | and-c16 rA rB CCCC | rA＝rB&CCCC |
| op AA BB CC | and rAA rBB rCC | rAA＝rBB&rCC |
| op A|B | iand/2r rA rB | rA＝rA&rB |
| op A|B CC | iand-c8 rA，rB，CC | rA＝rB&CC |
| op A|B CCh CCl | iand-c16 rA rB CCCC | rA＝rB&CCCC |
| op AA BB CC | iand rAA rBB rCC | rAA＝rBB&rCC |
Providing multiple operation formats may reduce the size of the bytecode, since it is more common than the operation. Using other instructions may reduce the instruction length by 1 or 2 bytes compared to 4 bytes for the and rAA rBB/iand rAA rBB. For example, the third row s2b2s rA rB instruction implicates the operand 0xFF into the opcode, reducing instruction length.
b. The array member access instruction in a 4-bit register format is shown in Table 9.
TABLE 9
As can be seen from table 9, the instruction using the 4-bit register format is reduced by one byte compared to the instruction using the 8-bit register, and the length of the bytecode can be significantly reduced by using the 4-bit register for the frequently-occurring instruction (such as getarray-o).
c. The create array instruction, which implies the member type of the array member into the opcode, is shown in Table 10.
Watch 10
As can be seen from Table 10, the first row of the malware-b rA rB instruction is more common, and the member type (byte) of the array member is implicit in the opcode, which can be reduced by 1 or 2 bytes compared to the other two instructions.
d. Based on the equal and unequal comparison results, branch instructions having a variety of instruction formats, including a branch instruction with a value of 0 for comparison, such as Table 11, and a branch instruction with two operands for comparison, such as Table 12.
TABLE 11
TABLE 12
In table 12 above, instructions that use an 8-bit offset can be reduced by one byte length.
The reduced instruction set of the present invention further includes a third instruction, the third instruction including instructions having different instruction formats based on different numbers of parameters. The third instructions include:
a. static method call instructions with different instruction formats based on different numbers of parameters, as in table 13.
b. Virtual method call instructions having different instruction formats based on different numbers of parameters, as in table 14.
c. Based on the number of different parameters, private instance method call instructions with different instruction formats.
Watch 13
TABLE 14
As can be seen from tables 13-14, for method calls with no or few parameters, the above encoding instruction is relatively short, and especially such calls are relatively common, so that the size of the bytecode of the method can be significantly reduced.
The reduced instruction set of the present invention further includes a fourth instruction, the fourth instruction including an instruction of a common data type and an instruction of an uncommon data type, the instruction of the common data type having a plurality of instruction formats, the instruction of the uncommon data type having an instruction format, the instruction of the common data type including an instruction of a short data type, and the instruction of the uncommon data type including an instruction of an int data type.
The reduced instruction set of the present invention also includes a fifth instruction that is an instruction having a single-byte constant pool index. The fifth instructions include:
a. static method call instructions with a one-byte constant pool index, such as table 15.
b. A virtual method call instruction with a single-byte constant pool index, as in Table 16.
c. Static domain access instructions with a single-byte constant pool index, such as table 17.
d. Example Domain Access instructions with a one-byte constant pool index, such as Table 18.
Watch 15
TABLE 16
TABLE 17
Watch 18
From tables 15-18, it can be seen that the length of the bytecode can be significantly reduced if a single-byte constant pool index can be employed.
The reduced instruction set of the present invention also includes a sixth instruction, the sixth instruction being a macro instruction. The sixth instruction includes replacing the formed macroinstruction based on a static method call instruction, and merging the formed macroinstruction based on adjacent instructions, as in table 19.
As can be seen from table 19, the macro instruction replacing the static method does not need to provide a constant pool index, and since the frequency of such static method calls is relatively high, replacing the macro instruction can significantly reduce the size of the bytecode.
The following table 20 is a summary table of the bytecode instruction set of the TGoMOS virtual machine instruction set of the present invention (the reduced instruction set of the present invention).
Watch 20
The embodiment of the invention also provides a resource-limited device, wherein a virtual machine is operated on the resource-limited device, and the virtual machine is used for executing the reduced instruction set.
The register-based virtual machine instruction set designed by the invention is used for resource-limited devices such as intelligent SE (secure element) chips and safe MCU (microprogrammed control Unit) chips, is object-oriented and architecture-neutral programs, reduces the size of byte codes as much as possible, can reduce the requirement on persistent storage of the chips and can improve the execution efficiency of the codes.
In order to verify the beneficial effects of the simplified instruction set of the present invention, a Java Card instruction set and a TGoMOS instruction set (the simplified instruction set of the present invention) are compared, other codes are basically consistent except for a bytecode interpreter code in a virtual machine system implemented on the same chip, a cryptographic algorithm and Flash write operation which take time in a command are closed, and average time of 10 execution results is counted and compared to obtain a comparison result. The results of comparing the sizes of converted bytecodes of the Java Card instruction set and the TGoMOS instruction set are shown in table 21. The results of the performance comparison of the application of the EDEP wallet to Java Card and TGoMOS platforms are shown in Table 22.
TABLE 21
TABLE 22
| Type of operation | TGoMOS | Java Card | The performance is improved% |
| Selecting applications | 2898 | 3078 | 5.85 |
| Load initialization | 5958 | 6826 | 12.72 |
| Earmark | 3118 | 3232 | 3.53 |
| Small counter | 14188 | 15690 | 9.57 |
| Selecting applications | 2904 | 3079 | 5.68 |
| Consumption initialization | 5646 | 6438 | 12.30 |
| Consumption of | 4192 | 4378 | 4.25 |
| Obtaining a balance | 2214 | 2554 | 13.31 |
| Small counter | 14956 | 16449 | 9.08 |
| Selecting applications | 2906 | 3080 | 5.65 |
| Composite consumption initialization | 5542 | 6439 | 13.93 |
| Updating File-1A | 2501 | 2579 | 3.02 |
| Updating File-1E | 2675 | 2756 | 2.94 |
| Composite consumption | 4164 | 4356 | 4.41 |
| Obtaining a balance | 2214 | 2554 | 13.31 |
| Small counter | 20002 | 21764 | 8.10 |
From table 21, the bytecode size of the TGoMOS instruction set (the reduced instruction set of the present invention) is close to the Java Card instruction set compared to the Java Card instruction set, and from table 22, the performance of running the EDEP wallet application on the TGoMOS virtual machine instruction set platform is better.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (8)
1. A reduced instruction set of micro-operating system bytecodes, the reduced instruction set comprising:
the first instruction consists of an operation code, and the operation code implicitly contains parameter information of the first instruction;
a second instruction, which is a high-frequency instruction with multiple instruction formats;
a third instruction, the third instruction comprising instructions based on different numbers of parameters and having different instruction formats;
a fourth instruction, including an instruction of a common data type and an instruction of an uncommon data type, the instruction of the common data type having multiple instruction formats, and the instruction of the uncommon data type having one instruction format;
a fifth instruction, the fifth instruction being an instruction having a single-byte constant pool index;
a sixth instruction, the sixth instruction being a macro instruction.
2. The reduced instruction set of claim 1 wherein the first instruction comprises:
instructions that imply both operands and register numbers into the opcode;
instructions that imply register numbers into the opcodes;
instructions to imply constant operands into opcodes;
an array member access instruction for hiding the member type of the array member into the operation code;
the type and parameters of the method call are implicit to the instruction in the opcode.
3. The reduced instruction set of claim 1 wherein the second instructions comprise:
common arithmetic operation instructions having a plurality of operation formats;
an array member access instruction in a 4-bit register format is adopted;
an array creating instruction for hiding the member type of the array member into the operation code;
based on the equal and unequal comparison results, branch instructions having multiple instruction formats.
4. The reduced instruction set of claim 1 wherein the third instruction comprises:
based on different parameter numbers, static method call instructions with different instruction formats;
virtual method call instructions with different instruction formats based on different parameter numbers;
based on the number of different parameters, private instance method call instructions with different instruction formats.
5. The reduced instruction set of claim 1 wherein the fourth instruction comprises:
the instructions of common data types include instructions of short data types;
instructions of the infrequent data type include instructions of the int data type.
6. The reduced instruction set of claim 1 wherein the fifth instruction comprises:
a static method call instruction with a single-byte constant pool index;
a virtual method call instruction with a single-byte constant pool index;
a static domain access instruction with a single-byte constant pool index;
example Domain Access instructions with a one-byte constant pool index.
7. The reduced instruction set of claim 1 wherein the sixth instruction comprises:
replacing the formed macroinstruction based on the static method call instruction;
and merging the formed macroinstructions based on the adjacent instructions.
8. A resource-constrained apparatus on which a virtual machine runs, the virtual machine being configured to execute the reduced instruction set of any one of claims 1 to 7.
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| CN202011553141.8A CN112631723A (en) | 2020-12-24 | 2020-12-24 | Byte code simplified instruction set and resource limited device of micro-operation system |
| PCT/CN2021/104738 WO2022134538A1 (en) | 2020-12-24 | 2021-07-06 | Micro-operating system bytecode reduced instruction set and resource restriction apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022134538A1 (en) * | 2020-12-24 | 2022-06-30 | 北京握奇数据股份有限公司 | Micro-operating system bytecode reduced instruction set and resource restriction apparatus |
| CN117130722A (en) * | 2023-08-04 | 2023-11-28 | 北京中电华大电子设计有限责任公司 | Optimization method and device for WebAsssembly instruction set |
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| US11307873B2 (en) * | 2018-04-03 | 2022-04-19 | Intel Corporation | Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging |
| US10853073B2 (en) * | 2018-06-30 | 2020-12-01 | Intel Corporation | Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator |
| US10866786B2 (en) * | 2018-09-27 | 2020-12-15 | Intel Corporation | Systems and methods for performing instructions to transpose rectangular tiles |
| US11200063B2 (en) * | 2018-09-27 | 2021-12-14 | Intel Corporation | Graphics engine reset and recovery in a multiple graphics context execution environment |
| CN112631722A (en) * | 2020-12-24 | 2021-04-09 | 北京握奇数据股份有限公司 | Byte code instruction set simplifying method and system |
| CN112631724A (en) * | 2020-12-24 | 2021-04-09 | 北京握奇数据股份有限公司 | Byte code instruction set simplifying method and system |
| CN112631723A (en) * | 2020-12-24 | 2021-04-09 | 北京握奇数据股份有限公司 | Byte code simplified instruction set and resource limited device of micro-operation system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022134538A1 (en) * | 2020-12-24 | 2022-06-30 | 北京握奇数据股份有限公司 | Micro-operating system bytecode reduced instruction set and resource restriction apparatus |
| CN117130722A (en) * | 2023-08-04 | 2023-11-28 | 北京中电华大电子设计有限责任公司 | Optimization method and device for WebAsssembly instruction set |
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