CN112612429A - iscsi target tgt architecture optimization method and system - Google Patents
iscsi target tgt architecture optimization method and system Download PDFInfo
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- CN112612429A CN112612429A CN202110014816.XA CN202110014816A CN112612429A CN 112612429 A CN112612429 A CN 112612429A CN 202110014816 A CN202110014816 A CN 202110014816A CN 112612429 A CN112612429 A CN 112612429A
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- 238000005457 optimization Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000003999 initiator Substances 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000872 buffer Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
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- 238000013507 mapping Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0608—Saving storage space on storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
- H04L41/0823—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability
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Abstract
The invention provides an iscsi target tgt architecture optimization method and system. The method comprises the following steps: when loading an iscsi driver, establishing a memory pool in a memory space applied on an iscsi target; and finishing physical IO to the memory on the iscsi target based on the established memory pool. The iscsi target tgt architecture optimization method and system provided by the invention can improve the IO read-write stability and performance.
Description
Technical Field
The invention relates to the technical field of bank open systems, in particular to an iscsi target tgt architecture optimization method and system.
Background
iscsi: the Internet Small Computer System Interface is an Ethernet-based storage protocol developed by IBM and is a SCSI instruction set that can run on top of the IP protocol. iscsi is a storage device remote mapping technique that maps storage devices on a remote server to local and appears as a block device.
The iscsi architecture mainly divides the storage device and the used host into two parts, which are: iscsi target: namely, the storage equipment end is used for storing the disk or RAID equipment, and the storage equipment end is made into a server end capable of providing the disk through an iscsi target function mainly through a TCP/IP technology; iscsi initiator: is the client that can use the target. It is true that a server that wants to connect to an iscsi target must also have the associated function of the iscsi initiator installed before the disk provided by the iscsi target can be used.
tgt is a common way to realize iscsi target, and the technology makes corresponding optimization according to the type of the back-end storage device and the condition of the device resource, so as to improve the IO performance.
The iscsi target tgt is the iscsi server implemented in tgt mode.
The prior art scheme is that a read-write IO of an iscsi initiator end applies for a memory to a system after reaching an iscsi target through a network, starts to receive data, writes the data into a back-end storage device after the data is received, and in the writing process, the data needs to be converted into a data format required by the back-end storage read-write, and then is transmitted after the conversion, and the memory is released after the read-write is completed. The existing flow refers to the flow chart 1.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an iscsi target tgt architecture optimization method and system, which can improve IO read-write stability and performance.
In order to solve the technical problem, the invention provides an iscsi target tgt architecture optimization method, which comprises the following steps: when loading an iscsi driver, establishing a memory pool in a memory space applied on an iscsi target; and finishing physical IO to the memory on the iscsi target based on the established memory pool.
In some embodiments, further comprising: after a memory pool is established in the memory space applied by the iscsi target, the memory space in the memory pool is managed by utilizing the tgt process.
In some embodiments, the physical IO comprises: physical IO originating from iscsi initiator.
In some embodiments, completing physical IO of memory on an iscsi target based on an already established memory pool, comprising: and finishing physical IO to the memory on the iscsi target based on a storage format compatible with the back end.
In some embodiments, further comprising: and releasing the memory pool established in the memory space when the iscsi drive is unloaded.
In addition, the invention also provides an iscsi target tgt architecture optimization system, which comprises: one or more processors; a storage device for storing one or more programs that, when executed by the one or more processors, cause the one or more processors to implement the iscsi target tgt architecture optimization method as described above.
After adopting such design, the invention has at least the following advantages:
1. read-write fluctuation caused by insufficient system memory when the equipment is busy is avoided;
2. reducing the memory application and release times;
3. unnecessary memory copying is avoided.
Drawings
The foregoing is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and the detailed description.
FIG. 1 is a flow chart of iscsi IO read and write provided by the prior art;
FIG. 2 is a flow chart of iscsi IO read-write provided by an embodiment of the present invention;
fig. 3 is a system structure diagram of an iscsi target tgt architecture optimization system according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
The new technical scheme is that a large block of memory is applied to be used as a memory pool when the iscsi driver loads, and the application and release of the memory interact with the memory pool later, so that the reading and writing stability of the iscsi target cannot be influenced by the amount of the available memory of equipment.
The read-write IO of the iscsi initiator end applies for the memory to the memory pool after reaching the iscsi target through the network, starts to receive data, receives the data and directly stores the data according to the format required by the back-end storage, and directly issues the data when the data is written into the back-end storage without conversion again, so that each IO reduces one time of memory copy and one time of application and release of the memory. The flow of the new technical scheme refers to a flow chart 2.
The technical scheme provided by the embodiment of the invention has the following key points:
1. when the driver loads, the memory pool is applied, the tgt process manages the memory by itself, and the application and the release of the memory do not interact with the system memory later.
2. The data is received and stored in a format stored and issued by the back end, so that the copying and application releasing times of the memory are reduced.
Because the memory for receiving data by the tgt process is managed by the memory pool and does not interact with the system memory, the stability is greatly improved, and the received data is stored based on a format compatible with the back end, the back end storage is prevented from applying for memory copy and conversion again, and the processing efficiency of the back end storage is greatly improved.
FIG. 3 shows the structure of an iscsi target tgt architecture optimization system. Referring to fig. 3, for example, the iscsi target tgt architecture optimization system 300 may be used to act as a storage optimization system in an iscsi system. As described herein, the iscsi target tgt architecture optimization system 300 may be used to implement optimized storage functionality for data in an iscsi system. The iscsi target tgt architecture optimization system 300 may be implemented in a single node, or the functions of the iscsi target tgt architecture optimization system 300 may be implemented in multiple nodes in a network. Those skilled in the art will appreciate that the term iscsi target tgt architecture optimization system includes devices in a broad sense, and the iscsi target tgt architecture optimization system 300 shown in fig. 3 is but one example. The iscsi target tgt architecture optimization system 300 is included for clarity and is not intended to limit the application of the present invention to a particular iscsi target tgt architecture optimization system embodiment or a class of iscsi target tgt architecture optimization system embodiments. At least some of the features/methods described herein may be implemented in a network device or component, such as the iscsi target tgt architecture optimization system 300. For example, the features/methods of the present invention may be implemented in hardware, firmware, and/or software running installed on hardware. The iscsi target tgt architecture optimization system 300 may be any device that processes, stores, and/or forwards data frames over a network, such as a server, a client, a data source, and the like. As shown in fig. 3, the iscsi target tgt architecture optimization system 300 may include a transceiver (Tx/Rx)310, which may be a transmitter, a receiver, or a combination thereof. Tx/Rx 310 may be coupled to a plurality of ports 350 (e.g., an uplink interface and/or a downlink interface) for transmitting and/or receiving frames from other nodes. Processor 330 may be coupled to Tx/Rx 310 to process frames and/or determine to which nodes to send frames. The processor 330 may include one or more multi-core processors and/or memory devices 332, which may serve as data stores, buffers, and the like. The processor 330 may be implemented as a general-purpose processor, or may be part of one or more Application Specific Integrated Circuits (ASICs) and/or Digital Signal Processors (DSPs).
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention in any way, and it will be apparent to those skilled in the art that the above description of the present invention can be applied to various modifications, equivalent variations or modifications without departing from the spirit and scope of the present invention.
Claims (6)
1. An iscsi target tgt architecture optimization method is characterized by comprising the following steps:
when loading an iscsi driver, establishing a memory pool in a memory space applied on an iscsi target;
and finishing physical IO to the memory on the iscsi target based on the established memory pool.
2. The iscsi target tgt architecture optimization method according to claim 1, further comprising:
after a memory pool is established in the memory space applied by the iscsi target, the memory space in the memory pool is managed by utilizing the tgt process.
3. The iscsi target tgt architecture optimization method according to claim 1, wherein the physical IO comprises: physical IO originating from iscsi initiator.
4. The iscsi target tgt architecture optimization method of claim 3, wherein completing physical IO of the memory on the iscsi target based on the established memory pool, comprises:
and finishing physical IO to the memory on the iscsi target based on a storage format compatible with the back end.
5. The iscsi target tgt architecture optimization method according to claim 1, further comprising:
and releasing the memory pool established in the memory space when the iscsi drive is unloaded.
6. An iscsi target tgt architecture optimization system, comprising:
one or more processors;
a storage device for storing one or more programs,
when executed by said one or more processors, cause said one or more processors to implement the iscsi target tgt architecture optimization method according to any of claims 1 to 5.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1972215A (en) * | 2006-12-06 | 2007-05-30 | 中国科学院计算技术研究所 | A remote internal memory sharing system and its implementation method |
| CN106886368A (en) * | 2016-12-30 | 2017-06-23 | 北京同有飞骥科技股份有限公司 | A kind of block device writes IO shapings and multi-controller synchronization system and synchronous method |
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2021
- 2021-01-06 CN CN202110014816.XA patent/CN112612429A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1972215A (en) * | 2006-12-06 | 2007-05-30 | 中国科学院计算技术研究所 | A remote internal memory sharing system and its implementation method |
| CN106886368A (en) * | 2016-12-30 | 2017-06-23 | 北京同有飞骥科技股份有限公司 | A kind of block device writes IO shapings and multi-controller synchronization system and synchronous method |
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Application publication date: 20210406 |