CN112597729B - DDR SDRAM channel optimization method and device and memory chip - Google Patents

DDR SDRAM channel optimization method and device and memory chip Download PDF

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CN112597729B
CN112597729B CN202110237448.5A CN202110237448A CN112597729B CN 112597729 B CN112597729 B CN 112597729B CN 202110237448 A CN202110237448 A CN 202110237448A CN 112597729 B CN112597729 B CN 112597729B
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姜攀
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New H3C Semiconductor Technology Co Ltd
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Abstract

The application provides a method and a device for optimizing a DDR SDRAM channel and a memory chip, wherein the method comprises the following steps: obtaining a DDR SDRAM design file; obtaining a passive channel description model for describing a DDR SDRAM channel in a design file; calculating a channel margin COM of the current DDR SDRAM channel according to the passive channel description model; if the current DDR SDRAM channel is determined to not meet the electrical performance optimization output condition based on the channel margin COM, performing optimization processing on the DDR SDRAM channel in the design file; and continuing to execute the step of obtaining the passive channel description model for describing the DDR SDRAM channel in the design file until the optimized DDR SDRAM channel meets the electrical performance optimization output condition. Therefore, the optimization processing speed of the DDR SDRAM channel is greatly improved.

Description

DDR SDRAM channel optimization method and device and memory chip
Technical Field
The application relates to the technical field of integrated circuits, in particular to a method and a device for optimizing a double-rate synchronous dynamic random access memory DDR SDRAM channel and a memory chip.
Background
With the rapid development of new applications such as artificial intelligence, automatic driving, high-performance computing and embedded vision, higher requirements are put forward on the bandwidth of a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM, abbreviated as DDR). Fig. 1a shows a relationship between time (in years) and data transmission rate (Gbps/pin) of various memories (such as GDDR, LPDDR, HBM, etc.), which shows geometric growth in recent years, and puts higher requirements on the electrical performance design of the DDR, and accordingly, after the DDR design is completed, verification and optimization of the DDR are also very important.
The optimization scheme of the current DDR design is implemented by using a passive channel, that is, performing passive channel modeling on an initial DDR file, then performing active time domain eye diagram simulation on a modeling output result, if the simulation result does not reach the expectation, performing optimization processing on the DDR file, then performing modeling and time domain eye diagram simulation again on the result after the optimization processing, then judging whether the simulation result reaches the expectation, if the simulation result still does not reach the expectation, performing the above-mentioned process iteratively, as shown in fig. 1 b. However, the method needs a long time for completing one iteration, and designers generally cannot directly find the quality of the DRR design from the passive channel parameters directly, and the DRR design can be judged only by completing time-domain eye diagram simulation. Moreover, time-domain eye diagram simulation must rely on active models, such as HSPICE, IBIS or IBIS-AMI models, which are difficult to acquire in the early design stage of DRR design and cannot complete early iterations of system design.
Therefore, how to realize the fast optimization of the DRR SDRAM design file is one of the considerable technical problems.
Disclosure of Invention
In view of this, the present application provides an optimization method and apparatus for DDR SDRAM channels of a double data rate synchronous dynamic random access memory, and a memory chip, so as to implement a fast optimization design of DRR SDRAM design files.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the present application, there is provided a method for optimizing a DDR SDRAM channel, the method comprising:
obtaining a DDR SDRAM design file;
obtaining a passive channel description model for describing a DDR SDRAM channel in the design file;
calculating a channel margin COM of the current DDR SDRAM channel according to the passive channel description model;
if the current DDR SDRAM channel does not meet the electrical performance optimization output condition based on the channel margin COM, performing optimization processing on the DDR SDRAM channel in the design file; and continuing to execute the step of obtaining the passive channel description model for describing the DDR SDRAM channel in the design file until the optimized DDR SDRAM channel meets the electrical performance optimization output condition.
According to a second aspect of the present application, there is provided an apparatus for optimizing a DDR SDRAM channel, the apparatus comprising:
the file acquisition module is used for acquiring a DDR SDRAM design file;
the model obtaining module is used for obtaining a passive channel description model for describing the DDR SDRAM channel in the design file;
the calculation module is used for calculating the channel margin COM of the current DDR SDRAM channel according to the passive channel description model;
the judging module is used for judging whether the current DDR SDRAM channel meets the electrical performance optimization output condition or not based on the channel margin COM;
the optimization processing module is used for optimizing the DDR SDRAM channel in the design file if the judgment result of the judgment module is negative; and continuing to execute the step of obtaining the passive channel description model for describing the DDR SDRAM channel in the design file until the optimized DDR SDRAM channel meets the electrical performance optimization output condition.
According to a third aspect of the present application, a memory chip is provided, which includes a double-rate synchronous dynamic random access memory DDR SDRAM memory, where the DDR SDRAM memory includes a DDR SDRAM channel optimized based on the method provided in the first aspect of the embodiments of the present application.
According to a fourth aspect of the present application, there is provided an electronic device comprising a processor and a machine-readable storage medium, the machine-readable storage medium storing a computer program executable by the processor, the processor being caused by the computer program to perform the method provided by the first aspect of the embodiments of the present application.
According to a fifth aspect of the present application, there is provided a machine-readable storage medium storing a computer program which, when invoked and executed by a processor, causes the processor to perform the method provided by the first aspect of the embodiments of the present application.
The beneficial effects of the embodiment of the application are as follows:
the method, the device and the memory chip for optimizing the DDR SDRAM channel provided by the embodiment of the application obtain a passive channel description model for describing the DDR SDRAM channel after obtaining a DDR SDRAM design file comprising the DDR SDRAM channel, then calculate the channel margin COM of the DDR SDRAM channel based on the obtained passive channel description model, optimize the DDR SDRAM channel when the DDR SDRAM channel which is currently designed is confirmed to not meet the electrical performance optimization output condition based on the channel margin COM, then repeatedly execute the process until the DDR SDRAM channel after the optimization process meets the electrical performance optimization output condition, so that the DDR SDRAM channel is not required to be optimized by an active time domain eye diagram simulation model in the prior art, and the active time domain eye diagram simulation model is difficult to obtain and consumes time, therefore, the optimization time of the DDR SDRAM channel can be greatly saved by adopting the method provided by the application, and the accuracy is high.
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FIG. 1a is a prior art data transfer rate for DDR in recent years;
FIG. 1b is a flowchart of DDR optimization provided by the prior art;
FIG. 2 is a flowchart of a method for optimizing a DDR SDRAM channel according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of another DDR SDRAM channel optimization method provided by the embodiments of the present application;
fig. 4 is a schematic diagram of far-end crosstalk channels and near-end crosstalk channels provided by an embodiment of the present application;
FIG. 5 is a block diagram of an apparatus for optimizing a DDR SDRAM channel according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a hardware structure of an electronic device implementing the method for optimizing the DDR SDRAM channel according to the embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the corresponding listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for optimizing a DDR SDRAM channel according to the present application, where the method includes the following steps:
and S21, obtaining a DDR SDRAM design file.
Specifically, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), abbreviated as DDR, can perform Data transmission on both the rising edge and the falling edge of the system clock, so the Data transmission speed is twice the frequency of the system clock.
And S22, obtaining a passive channel description model for describing the DDR SDRAM channel in the design file.
Specifically, after the DDR SDRAM design file is obtained, parameters simulating a passive channel of the DDR SDRAM channel may be extracted from the design file, and then the extracted parameters are configured in the corresponding passive channel description model, so as to obtain the passive channel description model for describing the DDR SDRAM channel in the design file. Optionally, the passive channel description models corresponding to different DDR SDRAM designs are different, and after the DDR SDRAM channel is optimized, the passive channel description models corresponding to the DDR SDRAM design file before and after the optimization are also different.
And S23, calculating a channel margin COM of the current DDR SDRAM channel according to the passive channel description model.
Specifically, because the data and address buses in the DDR SDRAM design are single-ended transmission, the single-ended transmission refers to single-wire communication from the local terminal to the opposite terminal, that is, the local terminal transmits data to the port of the opposite terminal through the port of the local terminal. Therefore, the passive channel description model obtained in the present application is a single-ended passive channel description model, which can be denoted as S2P.
In this step, a Channel Margin (COM) algorithm may be used to calculate a COM of the current DDR SDRAM Channel, and since a single-ended passive Channel description model is obtained, correspondingly, the COM algorithm of the Channel Margin in this application is also adaptively adjusted, so that the improved COM algorithm of the Channel Margin can adapt to the single-ended passive Channel description model. Specifically, the channel margin COM algorithm is operated by a matrix, so for a description matrix of a single-ended passive channel description model, the operation matrix related to the channel margin COM algorithm needs to be adjusted to a dimension required for processing the description matrix. For example, the description matrix of the single-ended passive channel description model is 2 rows and 2 columns, and the operation matrix involved in the channel margin COM algorithm needs to be adjusted to the dimension required for processing the 2 rows and 2 columns description matrix.
S24, judging whether the current DDR SDRAM channel meets the electrical performance optimization output condition or not based on the channel margin COM; if not, go to step S25; if yes, the process ends.
In this step, the channel margin COM value can measure the channel quality of the passive channel, so the channel quality of the currently designed DDR SDRAM channel can be determined based on the channel margin COM value, and if the channel quality reaches the electrical property optimized output condition, the currently designed DRR SDRAM channel is represented to meet the requirement and can be used; otherwise, it indicates that the currently designed DRR SDRAM channel needs to be optimized.
Specifically, step S24 may be performed according to the following procedure: judging whether the calculated channel margin COM value is larger than a set threshold value, if so, indicating that the currently designed DDR SDRAM channel meets the electrical performance optimization output condition; and if the output voltage is not larger than the preset value, the DDR SDRAM channel does not meet the electrical performance optimization output condition. The set threshold in the present application may be determined according to actual conditions, or may be obtained through a large number of simulation verifications.
S25, optimizing the DDR SDRAM channel in the design file, and executing the step S22 again.
In this step, when it is determined in step S24 that the currently designed DDR SDRAM does not satisfy the electrical performance optimization output condition, in a possible embodiment, at least one optimization method may be selected according to a plurality of preset possible optimization methods to perform optimization design on the DDR SDRAM channel in the design file, so as to obtain an optimized DDR SDRAM design file, or a correspondence between index values and optimization methods is preset, when it is determined that the current DDR SDRAM channel does not satisfy the requirement based on the channel margin COM value, the index values of the relevant indexes of the current DDR SDRAM may be determined, and then according to the requirement of each index value, the optimization method corresponding to the index values that do not satisfy the requirement is selected to optimize the DDR SDRAM channel, so as to obtain an optimized DDR SDRAM design file; and then executing the passive channel description model of the DDR SDRAM channel after the optimization processing again, namely executing the steps S22-S25 again until the DDR SDRAM channel after the optimization processing meets the electrical performance optimization output condition. In another possible embodiment, when the current DDR SDRAM channel is determined to not meet the requirement based on the channel margin COM value, the result can be output, so that a designer can perform optimization processing on the DDR SDRAM channel in the design file; or further determining an index value of a relevant index of the current DDR SDRAM, and then outputting the index value to a designer so that the designer can optimize the DDR SDRAM channel in the design file according to the output index value; then, the steps S22 to S25 are executed again. Therefore, the problem that the DDR SDRAM can be optimally designed only based on a time domain eye diagram simulation result, which is provided by the existing method, is consumed for a long time is not needed, the DDR SDRAM channel is optimized by adopting a method for calculating a channel margin COM value, the participation of an active model is not needed, and the optimization time of the DDR SDRAM channel is obviously saved.
By implementing the flow shown in fig. 2, after a DDR SDRAM design file including a DDR SDRAM channel is obtained, a passive channel description model for describing the DDR SDRAM channel is obtained, then a channel margin COM value of the DDR SDRAM channel is calculated based on the obtained passive channel description model, when the currently designed DDR SDRAM channel is confirmed to not meet an electrical performance optimization output condition based on the channel margin COM value, the DDR SDRAM channel is optimized, and then the flow is repeatedly executed until the optimized DDR SDRAM channel meets the electrical performance optimization output condition, so that the DDR SDRAM channel is not required to be optimized by using an active time domain eye pattern simulation model in the prior art, and because the active time domain eye pattern simulation model is difficult to obtain and consumes time, the optimization time of the DDR SDRAM channel can be greatly saved by adopting the method provided by the application, and the accuracy is high.
Optionally, after implementing the flow of fig. 2, the method for optimizing the DDR SDRAM channel provided in the embodiment of the present application may further include the following steps:
performing time domain eye diagram simulation processing on the DDR SDRAM channel meeting the electrical property optimization output condition;
and if the time domain eye pattern simulation result is successful, confirming that the DDR SDRAM channel meeting the electrical property optimization output condition meets the requirement.
Specifically, in a general case, when the set threshold value of the channel margin COM is set accurately, and the channel margin COM value of the optimized DDR SDRAM channel is greater than the set threshold value, it indicates that the optimized DDR SDRAM channel has satisfied the requirement. However, in order to prevent the influence of other factors, the designed DDR SDRAM channel may be further verified, and then the application proposes that the DDR SDRAM channel satisfying the electrical performance optimization output condition is subjected to time domain eye diagram simulation processing to obtain a time domain eye diagram simulation result, and if the time domain eye diagram simulation verification result is successful, it is indicated that the DDR SDRAM channel satisfying the electrical performance optimization output condition satisfies the design requirement. Specifically, the simulation result of the time domain eye pattern of the DDR SDRAM channel satisfying the electrical performance optimization output condition is generally successful, and the time domain eye pattern simulation does not need to be frequently performed to a certain extent; in addition, if the time domain eye pattern simulation result is unsuccessful, the DDR SDRAM channel may be optimally designed, then the process shown in fig. 2 is executed again, and then the DDR SDRAM meeting the electrical performance optimization output condition executes the time domain eye pattern simulation again.
Optionally, the passive channel in this application may include, but is not limited to, a victim line channel, a far-end crosstalk channel, and a near-end crosstalk channel, and accordingly, the passive channel description model in this embodiment includes a victim line channel description model, a far-end crosstalk channel description model, and a near-end crosstalk channel description model, on this basis, step S23 may be implemented according to the flow shown in fig. 3, and includes the following steps:
and S31, performing channel filtering processing on the victim line channel represented by the victim line channel description model.
Specifically, the channel filtering function may be used to perform channel filtering processing on the victim line channel represented by the victim line channel description model, for example, the channel filtering function may be, but is not limited to, a Hintr () function, and the like.
S32, judging whether the victim line channel needs equalization processing according to the DDR SDRM design file, and if so, executing a step S33; if the determination result is negative, step S319 is executed.
Specifically, the DDR SDRAM design file includes indication information for indicating whether the victim line channel needs equalization processing, and whether the victim line channel needs equalization processing is determined according to a value of the indication information.
Optionally, the indication information of the victim line channel included in the DDR SDRAM design file in the present application may be the number of zeros and poles. When the number is 0, it indicates that the victim line channel does not need to be equalized, and when the number is not 0, it indicates that the victim line channel needs to be equalized.
And S33, performing required equalization processing on the channel-filtered victim line channel by using an equalizer.
This step is performed when equalization is required. Alternatively, the equalization process in the present application may include, but is not limited to, Continuous Time Linear Equalizer (CTLE), Feed Forward Equalizer (FFE), and Decision Feedback Equalizer (DFE), respectively. The equalization process that needs to be performed by the victim line channel may be at least one of the three equalization processes described above.
Specifically, when the equalizer is used to perform the equalization processing on the victim line channel, the essence of the present application is to use the equalization function to operate the matrix for representing the victim line channel, and take the FFE and CTLE equalization processing as an example for explanation, then the required equalization functions are Hffe () and Hctel (). And combining the channel filter function, the product of the three functions is Hintr () ' Hffe () ' Hctel () ' when in operation, wherein the matrix for representing the channel of the victim line is in the parenthesis and participates in the operation. Specifically, the equalization function is constructed according to indication information about a victim line channel in a DDR SDRAM design file, and taking the example that the indication information includes 2 zeros and 2 poles, the equalization function including 2 zeros and 2 poles is constructed. And then carrying out equalization processing on the victim line channel by using the constructed equalization function.
And S34, converting the equalized victim line channel from a frequency domain to a time domain, and determining the signal amplitude of the signal of the victim line channel when the converted victim line channel has the optimal figure of merit FOM.
Specifically, since the channel filtering and the equalization processing are both operations in the frequency domain, and the signal amplitude needs to be calculated when the channel margin COM value is calculated, the victim line channel after the equalization processing needs to be converted from the frequency domain to the time domain, that is, the victim line channel signal on the victim line channel needs to be subjected to inverse fourier transform to obtain a time domain victim line channel signal, which may be a single pulse response waveform. Then determining a Figure of merit (Figure of merit, FOM) of the victim line channel after the conversion, if the Figure of merit does not reach the optimum, adjusting parameters in the equalizer (when the equalizer is an equalization function, it is substantial to adjust values of zero and pole in the equalization function), then performing equalization processing again on the victim line channel after the channel filtering by using the adjusted equalizer, then performing frequency domain to time domain conversion on the victim line channel after the equalization processing in step S34, then confirming the FOM of the victim line channel after the conversion again, judging whether the Figure of merit FOM determined this time is optimum again, if not, performing the above process again until the optimum FOM is determined and marked as the optimum Figure of merit, then performing equalization processing on the victim line channel by using the equalizer corresponding to the optimum Figure of merit FOM, then performing frequency domain to time domain conversion on the victim line channel after the equalization processing, the signal amplitude As of the victim line channel signal on the victim line channel is obtained. Or, when the optimal figure of merit FOM does not exist, determining whether the number of times of determination reaches the set number of times, when the set number of times of determination reaches, selecting the largest figure of merit FOM value from the historically calculated figure of merit FOM As the optimal figure of merit FOM, then performing equalization processing on the victim line channel by using the equalizer corresponding to the largest figure of merit FOM value, and then performing frequency domain to time domain conversion on the equalized victim line channel to obtain the signal amplitude As of the signal of the victim line channel on the victim line channel.
And S35, aiming at the far-end crosstalk channel description model, carrying out channel filtering processing on the far-end crosstalk channel represented by the far-end crosstalk channel description model.
In this step, reference may be made to the processing procedure of the victim line channel in step S31 for processing the far-end crosstalk channel in this application, and repeated details are not described again.
Alternatively, the Far End Crosstalk (FEXT) channel in the present application may include a plurality of channels, and as shown with reference to fig. 4, the FEXT channel includes a plurality of aggressor and victim line driving ends. Referring to fig. 4, in fig. 4, the left side is a far-end crosstalk channel, the middle is a victim channel, and the right side is a near-end crosstalk channel, taking the first aggressor line of the far-end crosstalk channel as an example to explain, a port of the aggressor line and a port of the victim line form a single-ended channel.
S36, judging whether the far-end crosstalk channel needs equalization processing according to the DDR SDRM design file, and if so, executing a step S37; if not, step S39 is executed.
Specifically, the DDR SDRAM design file also includes indication information indicating whether the far-end crosstalk channel needs to perform the equalization processing, and when the indication information indicates that the equalization processing needs to be performed on the far-end crosstalk channel, step S37 is executed. If the equalization process is not required, step S39, described in detail below, may be performed.
And S37, carrying out equalization processing on the far-end crosstalk channel after channel filtering.
Specifically, in the implementation process of equalizing the far-end crosstalk channel in this step, reference may be made to the processing process of step S33 on the victim channel. Namely, the optimal figure of merit FOM of the victim line channel signal on the victim line channel after equalization processing and frequency-time domain conversion is confirmed, and the equalizer corresponding to the optimal figure of merit FOM performs equalization processing on the far-end crosstalk channel after channel filtering. Specifically, when the equalization function corresponding to the far-end crosstalk channel is constructed, the equalization function may be constructed based on the indication information used in step S36 to indicate whether the far-end crosstalk channel needs to perform the equalization processing.
Alternatively, when step S37 is implemented, the following process may be implemented: acquiring the equalization parameters of the equalizer of the equalized victim line channel under the optimal figure of merit (FOM); and configuring an equalizer required by the far-end crosstalk channel by using the equalization parameter, and performing equalization processing on the far-end crosstalk channel after channel filtering processing by using the configured equalizer.
Specifically, in order to optimize the DDR SDRAM channel more quickly and evaluate the DDR SDRAM channel more accurately, when the far-end crosstalk channel is equalized, the equalization parameters of the equalizer of the victim line channel at the optimal figure of merit FOM may be retained, the equalizer of the far-end crosstalk channel is configured by using the equalization parameters of the equalizer of the victim line channel at the optimal figure of merit FOM, and then the far-end crosstalk channel filtered by the channel is equalized by using the configured equalizer.
And S38, converting the equalized far-end crosstalk channel from a frequency domain to a time domain.
Specifically, the far-end crosstalk signal on the equalized far-end crosstalk channel may be subjected to a frequency-domain to time-domain conversion process by using an inverse fourier transform, and then step S310 is performed.
S39, converting the channel-filtered far-end crosstalk channel from frequency domain to time domain, and performing step S310.
Specifically, when the far-end crosstalk channel does not need to perform the equalization processing, the far-end crosstalk signal on the far-end crosstalk channel filtered by the channel in step S35 may be directly subjected to the frequency-domain-to-time-domain conversion processing.
And S310, adding interference noise to the converted far-end crosstalk channel, and determining the channel noise of the far-end crosstalk channel added with the interference noise.
Specifically, the interference noise in the present application may include, but is not limited to, deterministic jitter noise, random jitter noise, and the like. After adding the interference noise, the channel noise of the far-end crosstalk channel after adding the interference noise in the time domain can be determined.
S311, aiming at the near-end crosstalk channel description model, carrying out channel filtering processing on the near-end crosstalk channel represented by the near-end crosstalk channel description model.
The Near End Crosstalk channel (NEXT) in the present application may include a plurality of channels, and as also shown with reference to fig. 4, the NEXT channel includes a plurality of aggressor and victim line driving ends.
S312, judging whether the near-end crosstalk channel needs equalization processing or not according to the DDR SDRM file, and if so, executing the step S313; if not, go to step S315.
Specifically, the DDR SDRAM design file also includes indication information indicating whether the near-end crosstalk channel needs to perform the equalization processing, and when the indication information indicates that the equalization processing needs to be performed on the near-end crosstalk channel, step S313 is executed. If the equalization process is not required, step S315, which will be described in detail later, may be performed.
And S313, carrying out equalization processing on the near-end crosstalk channel after channel filtering.
Specifically, in the implementation process of equalizing the near-end crosstalk channel in this step, reference may be made to the processing process of step S33 on the victim channel. Namely, the optimal figure of merit FOM of the victim line channel signal on the victim line channel after equalization processing and frequency-time domain conversion is confirmed, and the equalizer corresponding to the optimal figure of merit FOM performs equalization processing on the near-end crosstalk channel after channel filtering. Specifically, when the equalization function corresponding to the near-end crosstalk channel is constructed, the equalization function may be constructed based on the indication information used in step S36 to indicate whether the near-end crosstalk channel needs to perform the equalization processing.
Alternatively, when step S313 is implemented, the following process may be implemented: acquiring the equalization parameters of the equalizer of the equalized victim line channel under the optimal figure of merit (FOM); and configuring an equalizer required by the near-end crosstalk channel by using the equalization parameter, and performing equalization processing on the near-end crosstalk channel after channel filtering processing by using the configured equalizer.
Specifically, when the near-end crosstalk channel is subjected to equalization processing, the equalization parameters of the equalizer of the victim line channel at the best quality factor FOM can be reserved, the equalizer of the near-end crosstalk channel is configured by using the equalization parameters of the equalizer of the victim line channel at the best quality factor FOM, and then the configured equalizer is used for performing equalization processing on the near-end crosstalk channel after channel filtering.
And S314, converting the equalized near-end crosstalk channel from a frequency domain to a time domain.
Specifically, the equalized near-end crosstalk signal on the near-end crosstalk channel may be subjected to a frequency-domain to time-domain conversion process by using an inverse fourier transform, and then step S316 is performed.
And S315, converting the near-end crosstalk channel subjected to channel filtering from a frequency domain to a time domain.
Specifically, when the near-end crosstalk channel does not need to perform the equalization processing, the frequency-domain to time-domain conversion processing may be directly performed on the near-end crosstalk signal on the near-end crosstalk channel filtered in step S311.
And S316, adding interference noise to the converted near-end crosstalk channel, and determining the channel noise of the near-end crosstalk channel added with the interference noise.
Specifically, the interference noise in the present application may include, but is not limited to, deterministic jitter noise, random jitter noise, and the like. When the interference noise is added, the channel noise of the near-end crosstalk channel to which the interference noise is added in the time domain can be determined.
S317, determining the noise signal amplitude of the noise signal in the DDR SDRAM channel according to the channel noise of the far-end crosstalk channel and the channel noise of the near-end crosstalk channel.
Specifically, the noise superposition processing may be performed on the channel noise of the far-end crosstalk channel and the channel noise of the near-end crosstalk channel, so that the noise signal amplitude An of the noise signal in the DDR SDRAM channel may be obtained.
S318, calculating a channel margin COM of the current DDR SDRAM channel according to the signal amplitude of the channel signal of the victim line and the noise signal amplitude.
Specifically, after the signal amplitude As of the channel signal of the victim line and the noise signal amplitude An are determined, the channel margin COM value of the current DDR SDRAM channel may be determined according to the following formula:
COM=20*lg(As/An)
note that, in the above formula of the channel margin COM, the channel margin COM islg() Is logarithmic to base 10.
And S319, converting the channel-filtered victim line channel from the frequency domain to the time domain.
Specifically, when the victim line channel does not need equalization processing, inverse fourier transform may be directly performed on the channel-filtered victim line channel obtained in step S31, so as to obtain a channel-filtered victim line channel in the time domain.
And S320, determining the signal amplitude of the victim line channel signal of the converted victim line channel.
Specifically, after obtaining the victim line channel in the time domain based on step S319, the signal amplitude As of the victim line channel signal in the victim line channel can be obtained.
S321, calculating a channel margin COM of the current DDR SDRAM channel according to the signal amplitude of the converted signal of the victim line channel and the noise signal amplitude.
Specifically, after the signal amplitude As is obtained based on step S320, the channel margin COM value of the current DDR SDRAM channel is obtained according to the channel margin COM value calculation formula in S318 by combining the noise signal amplitude An obtained in step S317.
It should be noted that the flow shown in fig. 3 may be implemented by at least one process, when the flow shown in fig. 3 is executed by one process, and the process is implemented when the above-mentioned flow is implemented, step S35 may be implemented after step S34, step S311 may be implemented after step S34, step S35 and step S311 may be implemented in parallel, step S35 may be executed first and step S311 is executed second, step S311 may be executed first and step S34 is executed first, and for convenience of illustration, input arrows of step S35 and step S311 in fig. 3 are shown by dashed lines. When the flow shown in fig. 3 is executed by 3 processes in real time, the first process implements the implementation process of the victim line channel, the second process implements the implementation process of the far-end crosstalk channel, the third process implements the implementation process of the near-end crosstalk channel, then the first process collects channel noise of the far-end crosstalk channel and channel noise of the near-end crosstalk channel, then obtains the noise signal amplitude of the noise signal in the DDR SDRAM channel, and finally calculates the channel margin COM value of the DDR SDRAM channel based on the signal amplitude of the victim line channel signal determined by the first process. When the flow shown in fig. 3 is implemented by 2 processes, the first process implements an implementation process of a victim line channel, the second process implements implementation processes of a far-end crosstalk channel and a near-end crosstalk channel, then the first process summarizes channel noise of the far-end crosstalk channel and channel noise of the near-end crosstalk channel, then obtains a noise signal amplitude of a noise signal in a DDR SDRAM channel, and finally calculates a channel margin COM value of the DDR SDRAM channel based on the signal amplitude of the victim line channel signal determined by the first process.
By implementing the flow shown in fig. 3 and combining the flow shown in fig. 2, the determination speed of the COM value of the DDR SDRAM channel is increased, and the optimization speed of the DDR SDRAM channel is further increased.
Based on the same inventive concept, the application also provides a DDR SDRAM channel optimization device corresponding to the DDR SDRAM channel optimization method. The implementation of the DDR SDRAM channel optimization device can refer to the above description of the DDR SDRAM channel optimization method, which is not discussed herein.
Referring to fig. 5, fig. 5 is a device for optimizing a DDR SDRAM channel according to an exemplary embodiment of the present application, including:
a file obtaining module 501, configured to obtain a DDR SDRAM design file;
a model obtaining module 502, configured to obtain a passive channel description model for describing a DDR SDRAM channel in the design file;
a calculating module 503, configured to calculate a channel margin COM of the current DDR SDRAM channel according to the passive channel description model;
a judging module 504, configured to judge whether the current DDR SDRAM channel meets an electrical performance optimization output condition based on the channel margin COM;
an optimization processing module 505, configured to perform optimization processing on the DDR SDRAM channel in the design file if the determination result of the determining module is negative; and continuing to execute the step of obtaining the passive channel description model for describing the DDR SDRAM channel in the design file until the optimized DDR SDRAM channel meets the electrical performance optimization output condition.
In a possible embodiment, the passive channel description model provided by this embodiment includes a victim channel description model, a far-end crosstalk channel description model, and a near-end crosstalk channel description model; then
The calculating module 503 is specifically configured to:
performing channel filtering processing on the victim line channel represented by the victim line channel description model;
judging whether the victim line channel needs equalization processing or not according to the DDR SDRM design file;
if the channel filtering is needed to be balanced, the equalizer is utilized to execute the needed balancing processing on the victim line channel after the channel filtering;
carrying out frequency domain to time domain conversion on the victim line channel after the equalization processing, and determining the signal amplitude of the victim line channel signal of the victim line channel at the optimal figure of merit (FOM);
for the far-end crosstalk channel description model and the near-end crosstalk channel description model, respectively performing channel filtering processing on a far-end crosstalk channel represented by the far-end crosstalk channel description model and a near-end crosstalk channel represented by the near-end crosstalk channel description model;
if the far-end crosstalk channel needs equalization processing according to the DDR SDRM design file, performing equalization processing on the far-end crosstalk channel after channel filtering; and are
Converting the balanced far-end crosstalk channel from a frequency domain to a time domain, adding interference noise into the converted far-end crosstalk channel, and determining channel noise of the far-end crosstalk channel added with the interference noise;
if the near-end crosstalk channel needs equalization processing according to the DDR SDRM design file, performing equalization processing on the near-end crosstalk channel after channel filtering; and are
Converting the frequency domain to the time domain of the equalized near-end crosstalk channel, adding interference noise into the converted near-end crosstalk channel, and determining channel noise of the near-end crosstalk channel added with the interference noise;
determining the noise signal amplitude of the noise signal in the DDR SDRAM channel according to the channel noise of the far-end crosstalk channel and the channel noise of the near-end crosstalk channel;
and calculating the channel margin COM of the current DDR SDRAM channel according to the signal amplitude of the channel signal of the victim line and the noise signal amplitude.
In a possible embodiment, the calculating module 503 is further configured to perform frequency domain to time domain conversion on the victim line channel after channel filtering if it is determined that the victim line channel does not need equalization processing; determining the signal amplitude of the victim line channel signal of the converted victim line channel; and calculating the channel margin COM of the current DDR SDRAM channel according to the signal amplitude of the victim line channel signal of the converted victim line channel and the noise signal amplitude.
In a possible embodiment, the calculating module 503 is further configured to perform frequency-domain to time-domain conversion on the far-end crosstalk channel after channel filtering if the far-end crosstalk channel does not need equalization processing; adding interference noise to the converted far-end crosstalk channel, and determining the channel noise of the far-end crosstalk channel added with the interference noise; if the near-end crosstalk channel does not need equalization processing, converting the near-end crosstalk channel subjected to channel filtering from a frequency domain to a time domain; and adding interference noise to the converted near-end crosstalk channel, and determining the channel noise of the near-end crosstalk channel added with the interference noise.
In a possible embodiment, the calculating module 503 is specifically configured to obtain an equalization parameter of the equalizer of the equalized victim line channel at the optimal figure of merit FOM; and configuring an equalizer required by the far-end crosstalk channel by using the equalization parameter, and performing equalization processing on the far-end crosstalk channel after channel filtering processing by using the configured equalizer.
In a possible embodiment, the calculating module 503 is specifically configured to obtain an equalization parameter of the equalizer of the equalized victim line channel at the optimal figure of merit FOM; and configuring an equalizer required by the near-end crosstalk channel by using the equalization parameter, and performing equalization processing on the near-end crosstalk channel after channel filtering processing by using the configured equalizer.
In a possible embodiment, the device for optimizing a DDR SDRAM channel provided in this application further includes: the simulation processing module 506 and the confirmation module 507 are also shown in fig. 5, in which:
the simulation processing module 506 is configured to perform time domain eye diagram simulation processing on the DDR SDRAM channel meeting the electrical performance optimization output condition;
and the confirming module 507 is configured to confirm that the DDR SDRAM channel meeting the electrical performance optimization output condition meets the requirement if the time domain eye diagram simulation result is successful.
Based on the same inventive concept, the embodiment of the application also provides a memory chip, wherein the memory chip comprises a double-rate synchronous dynamic random access memory DDR SDRAM, the DDR SDRAM comprises a DDR SDRAM channel, and the DDR SDRAM channel is obtained by optimizing the DDR SDRAM channel optimization method provided by any one of the embodiments of the application.
The embodiment of the present application provides an electronic device, as shown in fig. 6, including a processor 601 and a DDR SDRAM memory 602, where the DDR SDRAM memory 602 stores a computer program capable of being executed by the processor 601, and the processor 601 is caused by the computer program to execute the method for optimizing the DDR SDRAM channel provided in the embodiment of the present application.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.
For the embodiment of the electronic device, since the content of the related method is substantially similar to that of the foregoing embodiment of the method, the description is relatively simple, and the related points can be referred to only in the partial description of the embodiment of the method.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The implementation process of the functions and actions of each unit in the above device is specifically described in the implementation process of the corresponding step in the above method, and is not described herein again.
For the device embodiments, since they substantially correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims (8)

1. A method for optimizing a DDR SDRAM channel, comprising:
obtaining a DDR SDRAM design file;
obtaining a passive channel description model for describing a DDR SDRAM channel in the design file, wherein the passive channel description model comprises a victim line channel description model, a far-end crosstalk channel description model and a near-end crosstalk channel description model;
calculating a channel margin COM of the current DDR SDRAM channel according to the passive channel description model, wherein the calculation comprises the following steps: performing channel filtering processing on the victim line channel represented by the victim line channel description model; judging whether the victim line channel needs equalization processing or not according to the DDR SDRM design file; if the channel filtering is needed to be balanced, the equalizer is utilized to execute the needed balancing processing on the victim line channel after the channel filtering; carrying out frequency domain to time domain conversion on the victim line channel after the equalization processing, and determining the signal amplitude of the victim line channel signal of the victim line channel at the optimal figure of merit (FOM); for the far-end crosstalk channel description model and the near-end crosstalk channel description model, respectively performing channel filtering processing on a far-end crosstalk channel represented by the far-end crosstalk channel description model and a near-end crosstalk channel represented by the near-end crosstalk channel description model; if the far-end crosstalk channel needs equalization processing according to the DDR SDRM design file, performing equalization processing on the far-end crosstalk channel after channel filtering; converting the balanced far-end crosstalk channel from a frequency domain to a time domain, adding interference noise into the converted far-end crosstalk channel, and determining the channel noise of the far-end crosstalk channel added with the interference noise; if the near-end crosstalk channel needs equalization processing according to the DDR SDRM design file, performing equalization processing on the near-end crosstalk channel after channel filtering; converting the frequency domain to the time domain of the equalized near-end crosstalk channel, adding interference noise into the converted near-end crosstalk channel, and determining the channel noise of the near-end crosstalk channel added with the interference noise; determining the noise signal amplitude of the noise signal in the DDR SDRAM channel according to the channel noise of the far-end crosstalk channel and the channel noise of the near-end crosstalk channel; calculating a channel margin COM of the current DDR SDRAM channel according to the signal amplitude of the channel signal of the victim line and the noise signal amplitude;
if the current DDR SDRAM channel does not meet the electrical performance optimization output condition based on the channel margin COM, performing optimization processing on the DDR SDRAM channel in the design file; and continuing to execute the step of obtaining the passive channel description model for describing the DDR SDRAM channel in the design file until the optimized DDR SDRAM channel meets the electrical performance optimization output condition.
2. The method of claim 1, wherein if it is determined that the victim line channel does not require equalization processing, calculating a channel margin COM of a current DDR SDRAM channel according to the passive channel description model, comprises:
carrying out frequency domain to time domain conversion on the channel of the victim line after channel filtering; determining the signal amplitude of the victim line channel signal of the converted victim line channel;
and calculating the channel margin COM of the current DDR SDRAM channel according to the signal amplitude of the victim line channel signal of the converted victim line channel and the noise signal amplitude.
3. The method according to claim 1 or 2, wherein if the far-end crosstalk channel does not require equalization processing, performing frequency-domain to time-domain conversion on the channel-filtered far-end crosstalk channel; adding interference noise to the converted far-end crosstalk channel, and determining the channel noise of the far-end crosstalk channel added with the interference noise;
if the near-end crosstalk channel does not need equalization processing, converting the near-end crosstalk channel subjected to channel filtering from a frequency domain to a time domain; and adding interference noise to the converted near-end crosstalk channel, and determining the channel noise of the near-end crosstalk channel added with the interference noise.
4. The method of claim 1, wherein equalizing the channel filtered far-end crosstalk channels comprises:
acquiring the equalization parameters of the equalizer of the equalized victim line channel under the optimal figure of merit (FOM);
and configuring an equalizer required by the far-end crosstalk channel by using the equalization parameter, and performing equalization processing on the far-end crosstalk channel after channel filtering processing by using the configured equalizer.
5. The method of claim 1, wherein equalizing the channel filtered near-end crosstalk channels comprises:
acquiring the equalization parameters of the equalizer of the equalized victim line channel under the optimal figure of merit (FOM);
and configuring an equalizer required by the near-end crosstalk channel by using the equalization parameter, and performing equalization processing on the near-end crosstalk channel after channel filtering processing by using the configured equalizer.
6. The method of claim 1, further comprising:
performing time domain eye diagram simulation processing on the DDR SDRAM channel meeting the electrical property optimization output condition;
and if the time domain eye pattern simulation result is successful, confirming that the DDR SDRAM channel meeting the electrical property optimization output condition meets the requirement.
7. An apparatus for optimizing a DDR SDRAM channel, comprising:
the file acquisition module is used for acquiring a DDR SDRAM design file;
the model obtaining module is used for obtaining a passive channel description model for describing the DDR SDRAM channel in the design file, and the passive channel description model comprises a victim line channel description model, a far-end crosstalk channel description model and a near-end crosstalk channel description model;
a calculating module, configured to calculate a channel margin COM of the current DDR SDRAM channel according to the passive channel description model, where the calculating module includes: performing channel filtering processing on the victim line channel represented by the victim line channel description model; judging whether the victim line channel needs equalization processing or not according to the DDR SDRM design file; if the channel filtering is needed to be balanced, the equalizer is utilized to execute the needed balancing processing on the victim line channel after the channel filtering; carrying out frequency domain to time domain conversion on the victim line channel after the equalization processing, and determining the signal amplitude of the victim line channel signal of the victim line channel at the optimal figure of merit (FOM); for the far-end crosstalk channel description model and the near-end crosstalk channel description model, respectively performing channel filtering processing on a far-end crosstalk channel represented by the far-end crosstalk channel description model and a near-end crosstalk channel represented by the near-end crosstalk channel description model; if the far-end crosstalk channel needs equalization processing according to the DDR SDRM design file, performing equalization processing on the far-end crosstalk channel after channel filtering; converting the balanced far-end crosstalk channel from a frequency domain to a time domain, adding interference noise into the converted far-end crosstalk channel, and determining the channel noise of the far-end crosstalk channel added with the interference noise; if the near-end crosstalk channel needs equalization processing according to the DDR SDRM design file, performing equalization processing on the near-end crosstalk channel after channel filtering; converting the frequency domain to the time domain of the equalized near-end crosstalk channel, adding interference noise into the converted near-end crosstalk channel, and determining the channel noise of the near-end crosstalk channel added with the interference noise; determining the noise signal amplitude of the noise signal in the DDR SDRAM channel according to the channel noise of the far-end crosstalk channel and the channel noise of the near-end crosstalk channel; calculating a channel margin COM of the current DDR SDRAM channel according to the signal amplitude of the channel signal of the victim line and the noise signal amplitude;
the judging module is used for judging whether the current DDR SDRAM channel meets the electrical performance optimization output condition or not based on the channel margin COM;
the optimization processing module is used for optimizing the DDR SDRAM channel in the design file if the judgment result of the judgment module is negative; and continuing to execute the step of obtaining the passive channel description model for describing the DDR SDRAM channel in the design file until the optimized DDR SDRAM channel meets the electrical performance optimization output condition.
8. A memory chip comprising a double-data-rate synchronous dynamic random access memory (DDR SDRAM) memory, the DDR SDRAM comprising a DDR SDRAM channel, the DDR SDRAM channel optimized based on the method of any one of claims 1 to 6.
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