CN112596083A - High dynamic tracking loop and satellite navigation receiver - Google Patents
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
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Abstract
The application provides a high dynamic tracking loop and a satellite navigation receiver. The high dynamic tracking loop includes: a phase-locked loop and an acceleration digital oscillator; the acceleration digital oscillator is used for generating real-time change frequency; wherein the real-time change frequency is the change frequency of the acceleration; the frequency output accumulator is used for adding the real-time change frequency and the updating frequency generated by the phase-locked loop to obtain a real-time frequency, and inputting the real-time frequency to the carrier digital oscillator; the carrier digital oscillator is used for generating a real-time phase based on the real-time frequency. By additionally arranging the acceleration digital oscillator in the high dynamic tracking loop, the change frequency of the acceleration in the loop is tracked, so that the phase tracking precision in the loop is improved, and the problems of PVT precision reduction and even loop lock loss caused by the influence of crystal oscillator output frequency change or Doppler frequency in a received signal on the loop in a high dynamic scene are effectively solved.
Description
Technical Field
The application relates to the technical field of satellite navigation positioning, in particular to a high dynamic tracking loop and a satellite navigation receiver.
Background
In order to realize high-precision and high-sensitivity positioning, a tracking loop of a satellite navigation receiver is designed to be very sensitive to frequency change, and the receiver is easily influenced by crystal oscillator output frequency change or Doppler frequency in a received signal, so that PVT (Position; Velocity; Time) precision is reduced and even the loop is unlocked. When the satellite navigation receiver is applied to aircrafts such as an unmanned aerial vehicle and the like or other scenes with high dynamic performance, vibration or rapid temperature change and the like, on one hand, the receiver can generate Doppler frequency in a received signal, on the other hand, vibration or temperature change enables crystal oscillator output frequency in the receiver to generate time-varying components, the time-varying components are amplified in equal proportion when the crystal oscillator output frequency is multiplied to radio frequency, the time-varying components are translated to intermediate frequency during down-conversion and act on a loop, the influence on the loop is the same as the Doppler frequency generated dynamically, and then the tracking accuracy of the receiver is seriously reduced or the loop is unlocked.
Disclosure of Invention
An object of the embodiments of the present application is to provide a high dynamic tracking loop and a satellite navigation receiver, so as to improve the problem that "the tracking loop of the satellite navigation receiver is designed to be very sensitive to frequency variation, which may cause the receiver to be easily affected by the variation of the output frequency of a crystal oscillator or the doppler frequency in a received signal".
The invention is realized by the following steps:
in a first aspect, an embodiment of the present application provides a high dynamic tracking loop, including: a phase-locked loop and an acceleration digital oscillator; the phase-locked loop comprises a frequency output accumulator and a carrier digital oscillator; the output end of the frequency output accumulator is connected with the carrier digital oscillator; the input end of the acceleration digital oscillator is connected with the phase input end of the phase-locked loop, and the output end of the acceleration digital oscillator is connected with the input end of the frequency output accumulator; the acceleration digital oscillator is used for generating real-time change frequency; wherein the real-time change frequency is the change frequency of the acceleration; the acceleration represents an acceleration of the high dynamic tracking loop in a direction of sight with the received satellite; the frequency output accumulator is used for adding the real-time change frequency and the updating frequency generated by the phase-locked loop to obtain a real-time frequency, and inputting the real-time frequency to the carrier digital oscillator; the carrier digital oscillator is used for generating a real-time phase based on the real-time frequency.
In a high dynamic scene, the influence of the crystal oscillator output frequency change or the doppler frequency in the received signal on the loop is mainly reflected as a frequency change error caused by acceleration, so in the embodiment of the application, the acceleration digital oscillator is additionally arranged in the high dynamic tracking loop, the tracking of the change frequency of the acceleration in the loop is realized, the phase tracking precision in the loop is further improved, and the problem that the loop is influenced by the crystal oscillator output frequency change or the doppler frequency in the received signal to cause the reduction of the PVT precision and even the loss of the loop lock in the high dynamic scene is effectively solved.
With reference to the technical solution provided by the first aspect, in some possible implementation manners, the phase-locked loop is a second-order phase-locked loop, and the phase-locked loop includes a first digital oscillator; the first digital oscillator has a coefficient of T0；T0Indicating a loop update period; the output end of the first digital oscillator is connected with the input end of the frequency output accumulator; the input end of the first digital oscillator is the phase input end of the phase-locked loop.
In the embodiment of the application, the acceleration digital oscillator is additionally arranged on the second-order phase-locked loop, so that the change frequency of the acceleration in the second-order phase-locked loop is tracked, the phase tracking precision in the loop is further improved, and the problems that the PVT precision is reduced and even the loop is unlocked due to the fact that the second-order phase-locked loop is influenced by the output frequency change of a crystal oscillator or the Doppler frequency in a received signal under a high dynamic scene are effectively solved.
With reference to the technical solution provided by the first aspect, in some possible implementation manners, the phase-locked loop is a second-order phase-locked loop, and the phase-locked loop includes a first digital oscillator; the first digital oscillator has a coefficient of T0；T0Indicating a loop update period; the output end of the first digital oscillator is connected with the input end of the frequency output accumulator; the output end of the first digital oscillator is the phase input end of the phase-locked loop.
With reference to the technical solution provided by the first aspect, in some possible implementation manners, the phase-locked loop is a third-order phase-locked loop, and the phase-locked loop includes: a frequency second-order processing circuit and a frequency first-order processing circuit; the output end of the frequency second-order processing circuit is connected with the input end of the frequency first-order processing circuit, and the output end of the frequency first-order processing circuit is connected with the frequency output accumulator; the input end of the acceleration digital oscillator is connected with the input end of the frequency first-order processing circuit; the input end of the frequency first-order processing circuit is the phase input end of the phase-locked loop.
In the embodiment of the application, the acceleration digital oscillator is additionally arranged on the third-order phase-locked loop, so that the change frequency of the acceleration in the second-order phase-locked loop is tracked, the phase tracking precision in the loop is further improved, and the problem that the third-order phase-locked loop is influenced by the change of the output frequency of the crystal oscillator or the Doppler frequency in a received signal under a high dynamic scene, so that the PVT precision is reduced and even the loop is unlocked is effectively solved.
With reference to the technical solution provided by the first aspect, in some possible implementations, the frequency first-order processing circuit includes a second digital oscillator; the second digital oscillator has a coefficient of T0；T0Indicating a loop update period; the input end of the second digital oscillator is connected with the frequency second-order processing circuit, and the output end of the second digital oscillator is connected with the input end of the frequency output accumulator; and the input end of the acceleration digital oscillator is connected with the input end of the second digital oscillator.
With reference to the technical solution provided by the first aspect, in some possible implementation manners, the high dynamic tracking loop further includes: a jerk digital oscillator and a first accumulator; the input end of the jerk digital oscillator is connected with the input end of the frequency second-order processing circuit, and the output end of the jerk digital oscillator is connected with the input end of the first accumulator; the output end of the first accumulator is connected with the acceleration digital oscillator; the jerk digital oscillator is used for generating a variation frequency of jerk; the input end of the acceleration digital oscillator is connected with the input end of the second digital oscillator through the first accumulator; correspondingly, the real-time change frequency is the sum of the change frequency of the acceleration and the change frequency of the jerk.
In the embodiment of the present application, by adding an acceleration digital oscillator and an acceleration digital oscillator in the high dynamic tracking loop, tracking of the change frequency of the acceleration and the change frequency of the jerk in the loop is achieved, so as to improve the phase tracking accuracy in the loop, and effectively solve the problem that the loop is affected by the change of the crystal oscillator output frequency or the doppler frequency in the received signal to reduce the PVT accuracy and even lose the loop lock in the high dynamic scene.
With reference to the technical solution provided by the first aspect, in some possible implementations, the frequency second-order processing circuit includes a third digital oscillator and a fourth digital oscillator; the fourth digital oscillator has a coefficient of T0；T0Indicating a loop update period; the output end of the third digital oscillator is connected with the input end of the fourth digital oscillator; the output end of the fourth digital oscillator is connected to the frequency first-order processing circuit; and the input end of the third digital oscillator is the input end of the frequency second-order processing circuit.
With reference to the technical solution provided by the first aspect, in some possible implementations, the frequency second-order processing circuit includes a third digital oscillator and a fourth digital oscillator; the fourth digital oscillator has a coefficient of T0；T0Indicating a loop update period; the output end of the third digital oscillator is connected with the input end of the fourth digital oscillator; the output end of the fourth digital oscillator is connected to the frequency first-order processing circuit; and the output end of the third digital oscillator is the input end of the frequency second-order processing circuit.
With reference to the technical solution provided by the first aspect, in some possible implementations, the frequency second-order processing circuit includes a third digital oscillator and a fourth digital oscillator; what is needed isThe fourth digital oscillator has a coefficient of T0；T0Indicating a loop update period; the output end of the third digital oscillator is connected with the input end of the fourth digital oscillator; the output end of the fourth digital oscillator is connected to the frequency first-order processing circuit; and the output end of the fourth digital oscillator is the input end of the frequency second-order processing circuit.
In a second aspect, an embodiment of the present application provides a satellite navigation receiver, including: a receiving unit and a high dynamic tracking loop connected with the receiving unit as provided in the embodiments of the first aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a block diagram of a high dynamic tracking loop according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a second-order phase-locked loop according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a frequency change rate in an update period according to an embodiment of the present application.
Fig. 4 is a schematic diagram of real-time frequency in an update period according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a real-time phase within an update period according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram of a first high dynamic tracking loop provided in an embodiment of the present application.
Fig. 7 is a schematic structural diagram of a third-order phase-locked loop according to an embodiment of the present disclosure.
Fig. 8 is a schematic structural diagram of a second high dynamic tracking loop provided in the embodiment of the present application.
Fig. 9 is a schematic structural diagram of a third high dynamic tracking loop provided in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
In view of the fact that the tracking loop of the current satellite navigation receiver is designed to be very sensitive to frequency variation, there is a problem that the receiver is easily affected by the variation of the crystal oscillator output frequency or the doppler frequency in the received signal. The present inventors have made studies and studies to provide the following examples to solve the above problems.
Referring to fig. 1, an embodiment of the present application provides a high dynamic tracking loop, which includes a phase locked loop and an acceleration digital oscillator.
The phase-locked loop comprises a frequency output accumulator and a carrier digital oscillator. The output end of the frequency output accumulator is connected with the carrier digital oscillator.
The input end of the acceleration digital oscillator is connected with the phase input end of the phase-locked loop, and the output end of the acceleration digital oscillator is connected with the input end of the frequency output accumulator. The acceleration digital oscillator is used for generating real-time change frequency. Wherein the real-time change frequency is the change frequency of the acceleration; the accelerometer represents the acceleration of the high dynamic tracking loop and the received satellite line of sight.
The frequency output accumulator is used for adding the real-time change frequency and the updating frequency generated by the phase-locked loop to obtain a real-time frequency, and inputting the real-time frequency to the carrier digital oscillator; the carrier digital oscillator is used to generate a real-time phase based on the real-time frequency.
It should be noted that, in a high dynamic scene, the influence of the crystal oscillator output frequency change or the doppler frequency in the received signal on the loop is mainly reflected as a frequency change error caused by acceleration, so in the embodiment of the present application, the acceleration digital oscillator is additionally arranged in the high dynamic tracking loop, so that the tracking of the change frequency of the acceleration in the loop is realized, the phase tracking accuracy in the loop is further improved, and the problem that the PVT accuracy is reduced or even the loop is unlocked due to the influence of the crystal oscillator output frequency change or the doppler frequency in the received signal on the loop in the high dynamic scene is effectively solved.
The structure of the high dynamic tracking loop is explained below for different phase locked loops.
Optionally, the pll is a second-order pll, and a structure of the existing second-order pll is shown in fig. 2, where a triangle frame in fig. 2 represents a coefficient multiplier, and characters in the frame represent coefficients. The circles represent accumulators and the characters within the circles are summation symbols. The rectangular box represents a register, Z-1Representing a one beat delay. If the existing second-order phase-locked loop is adopted to directly track the phase, the expression of the output phase is as follows:
wherein the content of the first and second substances,
which is indicative of the phase of the loop output,
representing the phase at the start of the loop, k representing the number of sampling points in the update period of the loop, f0Indicating the frequency of the start of a loop update, which remains constant during the loop update period, fsRepresenting the sampling frequency.
In the above equation, the phase change is linear, which does not take into account the acceleration contribution to the phase during the update time period.
Supposing that the second-order phase-locked loop is applied to a GPS (Global Positioning System) satellite navigation receiver, a high dynamic tracking error is analyzed according to a frequency point L1 of the GPS. The radio frequency of the frequency point of the GPS L1 is 1575.42MHz, the wavelength is 0.19m, when the receiver moves with the acceleration of 1g, the frequency change rate of 51.58Hz/s is generated on the radio frequency signal of the GPS L1, and when the acceleration reaches 25g, the frequency change rate is 1289.5 Hz/s. Wherein, the formula of the frequency change rate is as follows:
wherein m is0Is the first derivative of frequency, representing the rate of change of frequency; a is the acceleration of the receiver and the satellite in the sight line direction; f. ofLThe frequency of the L1 frequency point of the GPS is 1575.42e6Hz, which represents the satellite transmitting frequency; and c represents the speed of light.
The effect of acceleration (i.e., rate of change of frequency) in the loop is analyzed below. As shown in FIG. 3, assume that during the loop update period T00.02s inner frequency change rate m01250HZ/s remains unchanged (the rate of change of frequency produced by about 25g line-of-sight acceleration at the frequency point of GPS L1).
At nT0The frequency of the time loop update is f0At nT0And (n +1) T0The frequency components in between are shown in fig. 4. In FIG. 4, curve (r) represents nT0The initial frequency of the moment remains unchanged during the loop update period, curve representing the chirp component, the frequency with time with slope m0The linear increase (namely the change frequency of the acceleration) and the curve (c) represent the instantaneous frequency in the loop updating period and are the sum of the curve (c) and the curve (c).
At nT0The phase of the time loop update is
At nT0And (n +1) T0The respective phase components in between are shown in fig. 5. In FIG. 5, curve (r) represents nT0The initial phase of the moment remains constant during the loop update period, curve c represents the value f0The resulting phase, the component having a slope f with time0Linear increase, curve c represents by m0The resulting phase, the square of which increases with time, curve iv represents the instantaneous phase within the loop update period and is the sum of the first three.
As can be seen from the above-mentioned graphs, the loop of fig. 2 only tracks the phase changes of the curves (i) and (ii) in fig. 5, and does not track the phase change of the curve (iii), so that a fixed phase error occurs at the end of the tracking periodπm0T0 2The frequency change rate is about m at the frequency point of GPS L1 according to the acceleration of 25g01250HZ/s, loop update period T0The tracking phase error of the second order phase-locked loop of fig. 2 at the end of each update period is calculated as 0.02 s: pi m0T0 2Pi × 1250 × 0.02 × 0.5 pi, which error easily causes a loop to lose lock.
Thus, the rate of change of frequency causes the phase to change non-linearly over the loop update period, and the formula for its phase output should be:
wherein, T0＝k/fs. The formula is arranged to obtain:
that is, in the formula after finishing, f0+0.5m0k/fsReplaces f in the output phase formula of the existing second-order phase-locked loop0The meaning of the formula is to track the variation frequency generated by the acceleration, so that the finally obtained phase is not influenced by the acceleration in the updating period.
Therefore, the high dynamic tracking loop provided by the embodiment of the application is modified on the existing second-order phase-locked loop, and the acceleration digital oscillator is additionally arranged, and the specific structure of the acceleration digital oscillator is shown in fig. 6.
The phase-locked loop comprises a first digital oscillator. The first digital oscillator has a coefficient of T0；T0Indicating a loop update period. The output of the first digital oscillator is connected to the input of the frequency output accumulator (in fig. 6, two accumulators, one register and one digital oscillator are also included between the output of the first oscillator and the frequency output accumulator).
As an alternative connection mode, the input end of the first digital oscillator is a phase input end of the phase-locked loop, that is, the input end of the acceleration digital oscillator is connected to the input end of the first digital oscillator.
As another alternative connection mode, the output end of the first digital oscillator is the phase input end of the phase-locked loop, that is, the input end of the acceleration digital oscillator is connected to the output end of the first digital oscillator.
That is, the input terminal of the acceleration digital oscillator may be connected to either the point a in fig. 6 or the point B in fig. 6. The present application is not limited thereto.
Optionally, the pll is a third-order pll, and a structure of the existing third-order pll is shown in fig. 7, where the third-order pll includes a frequency second-order processing circuit and a frequency first-order processing circuit, and an output end of the frequency second-order processing circuit is connected to an input end of the frequency first-order processing circuit. The triangular boxes in fig. 7 represent coefficient multipliers, and the characters within the boxes represent coefficients. The circles represent accumulators and the characters within the circles are summation symbols. The rectangular box represents a register, Z-1Representing a one beat delay. If the existing third-order phase-locked loop is adopted to directly track the phase, the expression of the output phase is as follows:
wherein the content of the first and second substances,
which is indicative of the phase of the loop output,
representing the phase at the start of the loop, k representing the number of sampling points in the update period of the loop, f0Indicating the frequency of the start of a loop update, which remains constant during the loop update period, fsRepresenting the sampling frequency.
Similarly, the phase expression output by the third-order phase-locked loop does not consider the contribution of the acceleration to the phase in the update time period. The analysis process can refer to the analysis process in the second-order phase-locked loop, and is not repeated here to avoid redundancy.
Therefore, the high dynamic tracking loop provided by the embodiment of the application is modified on the existing third-order phase-locked loop, and the acceleration digital oscillator is additionally arranged, and the specific structure of the acceleration digital oscillator is shown in fig. 8. The input end of the acceleration digital oscillator is connected with the input end of the frequency first-order processing circuit. The input end of the frequency first-order processing circuit is the phase input end of the phase-locked loop.
Specifically, the frequency first-order processing circuit comprises a second digital oscillator. Coefficient of the second digital oscillator is T0；T0Indicating a loop update period. The output of the second digital oscillator is connected to the input of the frequency output accumulator (in fig. 8, two accumulators, one register and one digital oscillator are also included between the output of the second digital oscillator and the frequency output accumulator).
As an alternative connection, the input terminal of the second digital oscillator is the phase input terminal of the phase-locked loop, that is, the input terminal of the acceleration digital oscillator is connected to the input terminal of the second digital oscillator.
As another alternative connection, the output terminal of the second digital oscillator is the phase input terminal of the phase-locked loop, that is, the input terminal of the acceleration digital oscillator is connected to the output terminal of the second digital oscillator.
That is, the input terminal of the acceleration digital oscillator may be connected to either the point a in fig. 8 or the point B in fig. 8. The present application is not limited thereto.
It should be noted that all the above embodiments relate to the first derivative of frequency (frequency change rate m)0) The applicant has found in his research that, in a third order phase-locked loop, the second derivative of the frequency a0The (indicative of jerk) also has an effect on the output phase.
According to the taylor expansion, the contribution of the higher order frequency derivative to the phase in the loop update period can be obtained:
wherein the content of the first and second substances,
if only the second derivative a of the frequency is considered0First derivative of frequency m0And the frequency f of the start of the loop update0If n is 3, the phase formula output in the loop update period is:
wherein, a0In order to be the second derivative of the frequency,
t is k/fs. The formula is arranged to obtain:
that is, in the formula after finishing, f0+(0.5m0+a0k/fs/3)k/fsReplaces f in the output phase formula of the existing third-order phase-locked loop0The meaning of the formula is to track the change frequency generated by the acceleration and the change frequency generated by the jerk, so that the finally obtained phase is not influenced by the acceleration and the jerk in the update period.
Therefore, the high dynamic tracking loop provided by the embodiment of the present application is modified on the existing third-order phase-locked loop, and is additionally provided with a jerk digital oscillator and a first accumulator in addition to the acceleration digital oscillator, where the jerk digital oscillator is used to generate a change frequency of jerk, and a specific structure of the jerk digital oscillator is shown in fig. 9.
The input end of the jerk digital oscillator is connected with the input end of the frequency second-order processing circuit, and the output end of the jerk digital oscillator is connected with the input end of the first accumulator. The output end of the first accumulator is connected with the acceleration digital oscillator.
The jerk digital oscillator is used for generating a variation frequency of jerk; the input end of the acceleration digital oscillator is connected with the input end of the second digital oscillator through the first accumulator; correspondingly, the real-time change frequency is the sum of the change frequency of the acceleration and the change frequency of the jerk.
Specifically, the frequency second-order processing circuit includes a third digital oscillator and a fourth digital oscillator. The fourth digital oscillator has a coefficient of T0；T0Indicating a loop update period. The output end of the third digital oscillator is connected with the input end of the fourth digital oscillator; the output of the fourth digital oscillator is connected to the first-order frequency processing circuit (in fig. 9, two accumulators, one register and one digital oscillator are also included between the output of the fourth digital oscillator and the first-order frequency processing circuit).
As an optional connection manner, the input end of the third digital oscillator is the input end of the frequency second-order processing circuit, that is, the input end of the jerk digital oscillator is connected to the input end of the third digital oscillator.
As another optional connection mode, the output end of the third digital oscillator is the output end of the frequency second-order processing circuit, that is, the input end of the jerk digital oscillator is connected to the output end of the third digital oscillator.
As another alternative connection, the output terminal of the fourth digital oscillator is the input terminal of the frequency second-order processing circuit, that is, the input terminal of the jerk digital oscillator is connected to the output terminal of the fourth digital oscillator.
That is, the input terminal of the jerk digital oscillator may be connected to point C in fig. 9, to point D in fig. 9, or to point E in fig. 9. The present application is not limited thereto.
In summary, in a high dynamic scene, the influence of the crystal oscillator output frequency change or the doppler frequency in the received signal on the loop is also reflected as a frequency change error caused by the jerk, so in the embodiment of the present application, by adding the acceleration digital oscillator and the acceleration digital oscillator in the high dynamic tracking loop, the tracking of the change frequency of the jerk and the change frequency of the jerk in the loop is realized, and then the phase tracking accuracy in the loop is improved, thereby effectively solving the problem that the loop is influenced by the crystal oscillator output frequency change or the doppler frequency in the received signal to cause the PVT accuracy reduction or even the loop is unlocked in the high dynamic scene.
Based on the same inventive concept, the embodiment of the present application further provides a satellite navigation receiver, including: a receiving unit and a high dynamic tracking loop as provided in the above embodiments connected to the receiving unit.
The receiving unit may include a receiving antenna, a frequency converter, and other devices. The present application is not limited.
It should be noted that, because the high dynamic tracking loop provided in the embodiment of the present application can implement high-precision reliable tracking in a high dynamic and vibration change scene, a satellite navigation receiver carrying the high dynamic tracking loop may use a common crystal oscillator to replace an expensive high-stability crystal oscillator or reduce the anti-seismic and thermal insulation protection cost of the receiver, thereby achieving the effect of the same positioning precision.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A high dynamic tracking loop, comprising: a phase-locked loop and an acceleration digital oscillator; the phase-locked loop comprises a frequency output accumulator and a carrier digital oscillator; the output end of the frequency output accumulator is connected with the carrier digital oscillator;
the input end of the acceleration digital oscillator is connected with the phase input end of the phase-locked loop, and the output end of the acceleration digital oscillator is connected with the input end of the frequency output accumulator; the acceleration digital oscillator is used for generating real-time change frequency; wherein the real-time change frequency is the change frequency of the acceleration; the acceleration represents an acceleration of the high dynamic tracking loop in a direction of sight with the received satellite;
the frequency output accumulator is used for adding the real-time change frequency and the updating frequency generated by the phase-locked loop to obtain a real-time frequency, and inputting the real-time frequency to the carrier digital oscillator; the carrier digital oscillator is used for generating a real-time phase based on the real-time frequency.
2. The high dynamics tracking loop of claim 1, wherein the phase locked loop is a second order phase locked loop, the phase locked loop including a first digital oscillator; the first digital oscillator has a coefficient of T0；T0Indicating a loop update period;
the output end of the first digital oscillator is connected with the input end of the frequency output accumulator;
the input end of the first digital oscillator is the phase input end of the phase-locked loop.
3. The high dynamics tracking loop of claim 1, wherein the phase locked loop is a second order phase locked loop, the phase locked loop including a first digital oscillator; the first digital oscillator has a coefficient of T0；T0Indicating a loop update period;
the output end of the first digital oscillator is connected with the input end of the frequency output accumulator;
the output end of the first digital oscillator is the phase input end of the phase-locked loop.
4. The high dynamics tracking loop of claim 1 wherein the phase locked loop is a third order phase locked loop comprising: a frequency second-order processing circuit and a frequency first-order processing circuit; the output end of the frequency second-order processing circuit is connected with the input end of the frequency first-order processing circuit, and the output end of the frequency first-order processing circuit is connected with the frequency output accumulator;
the input end of the acceleration digital oscillator is connected with the input end of the frequency first-order processing circuit; the input end of the frequency first-order processing circuit is the phase input end of the phase-locked loop.
5. The high dynamic tracking loop of claim 4, wherein the frequency first order processing circuit comprises a second digital oscillator; the second digital oscillator has a coefficient of T0；T0Indicating a loop update period; the input end of the second digital oscillator is connected with the frequency second-order processing circuit, and the output end of the second digital oscillator is connected with the input end of the frequency output accumulator;
and the input end of the acceleration digital oscillator is connected with the input end of the second digital oscillator.
6. The high dynamic tracking loop of claim 5, further comprising: a jerk digital oscillator and a first accumulator;
the input end of the jerk digital oscillator is connected with the input end of the frequency second-order processing circuit, and the output end of the jerk digital oscillator is connected with the input end of the first accumulator; the output end of the first accumulator is connected with the acceleration digital oscillator; the jerk digital oscillator is used for generating a variation frequency of jerk; the input end of the acceleration digital oscillator is connected with the input end of the second digital oscillator through the first accumulator; correspondingly, the real-time change frequency is the sum of the change frequency of the acceleration and the change frequency of the jerk.
7. The high dynamics tracking loop of claim 6 wherein the frequency second order processing circuit comprises a third digital oscillator and a fourth digital oscillator; the fourth digital oscillator has a coefficient of T0；T0Indicating a loop update period;
the output end of the third digital oscillator is connected with the input end of the fourth digital oscillator; the output end of the fourth digital oscillator is connected to the frequency first-order processing circuit;
and the input end of the third digital oscillator is the input end of the frequency second-order processing circuit.
8. The high dynamics tracking loop of claim 6 wherein the frequency second order processing circuit comprises a third digital oscillator and a fourth digital oscillator; the fourth digital oscillator has a coefficient of T0；T0Indicating a loop update period;
the output end of the third digital oscillator is connected with the input end of the fourth digital oscillator; the output end of the fourth digital oscillator is connected to the frequency first-order processing circuit;
and the output end of the third digital oscillator is the input end of the frequency second-order processing circuit.
9. The high dynamics tracking loop of claim 6 wherein the frequency second order processing circuit comprises a third digital oscillator and a fourth digital oscillator; the fourth digital oscillator has a coefficient of T0；T0Indicating a loop update period;
the output end of the third digital oscillator is connected with the input end of the fourth digital oscillator; the output end of the fourth digital oscillator is connected to the frequency first-order processing circuit;
and the output end of the fourth digital oscillator is the input end of the frequency second-order processing circuit.
10. A satellite navigation receiver, comprising: a receiving unit and a high dynamic tracking loop according to any of claims 1-9 connected to the receiving unit.
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| CN1613177A (en) * | 2001-11-09 | 2005-05-04 | 高通股份有限公司 | Multiple analog and digital downconversion |
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| CN1613177A (en) * | 2001-11-09 | 2005-05-04 | 高通股份有限公司 | Multiple analog and digital downconversion |
| CN103698782A (en) * | 2013-09-05 | 2014-04-02 | 北京捷星广达科技有限责任公司 | Digital voltage-controlled oscillator with Doppler frequency shift speed compensation |
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