CN112580277A - Chip design method, device and equipment - Google Patents
Chip design method, device and equipment Download PDFInfo
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- CN112580277A CN112580277A CN202011417077.0A CN202011417077A CN112580277A CN 112580277 A CN112580277 A CN 112580277A CN 202011417077 A CN202011417077 A CN 202011417077A CN 112580277 A CN112580277 A CN 112580277A
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Abstract
The embodiment of the invention provides a chip design method, a device and equipment, wherein the method models part or all of the design content of a chip in at least one stage of design stage to obtain a design model of the chip in at least one stage of design stage, and further determines the design result of the chip in the current stage of design by calling the design model of the chip in the current stage of design stage and utilizing the design model to complete the design task of the chip in the current stage of design. Therefore, the embodiment of the invention can model part or all of the design content of the chip in at least one stage of design stage and set the design model of the chip in at least one stage of design stage, so that the design of the chip can be processed in a model calling mode, and the design efficiency and accuracy of the chip are improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of chips, in particular to a chip design method, a device and equipment.
Background
The chip is a very small silicon chip with an integrated circuit, which is commonly used in electronic devices such as computers; the chip design is the basis of chip manufacturing, and mainly comprises the following multi-stage design stages: software level (software level), behavior level (behavior level), transmission level (RTL, Register Transfer level), gate (gate) level, and circuit (circuit) level.
At present, chip Design is mainly implemented by Design tools such as EDA (electronic Design Automation), however, these Design tools have more or less problems in Design efficiency, and therefore it is very urgent to provide an improved chip Design method.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, an apparatus, and a device for designing a chip, so as to model part or all of the design content of the chip in at least one stage of design stage to obtain a design model of the chip in at least one stage of design stage, so as to implement chip design by using the design model, thereby implementing improvement of chip design efficiency and chip design accuracy.
In order to solve the above problem, an embodiment of the present invention provides a chip design method, including:
calling a design model of a chip at a current level design stage; the design model includes at least: basic information of the chip in the current level design stage, power consumption information estimated by the design model, and selectable implementation mode combination; the power consumption information is determined based on the design attribute of the chip in the next stage of design, and the abstract level of the next stage of design is lower than that of the current stage of design;
and determining the design result of the chip at the current stage of design by using the design model.
An embodiment of the present invention further provides a chip design apparatus, including:
the calling module is used for calling the design model of the chip at the current level design stage; the design model includes at least: basic information of the chip in the current level design stage, power consumption information estimated by the design model, and selectable implementation mode combination; the power consumption information is determined based on the design attribute of the chip in the next stage of design, and the abstract level of the next stage of design is lower than that of the current stage of design;
and the result determining module is used for determining the design result of the chip in the current level design stage by using the design model.
The embodiment of the invention also provides chip design equipment which comprises the chip design device.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a chip design method, a device and equipment, wherein the method models part or all of the design content of a chip in at least one stage of design stage to obtain a design model of the chip in at least one stage of design stage, and further, in the current stage of design of the chip, the embodiment of the invention can determine the design result of the chip in the current stage of design by calling the design model in the current stage of design of the chip and utilizing the design model to complete the design task of the chip in the current stage of design. Therefore, the embodiment of the invention can model part or all of the design content of the chip in at least one stage of design stage and set the design model of the chip in at least one stage of design stage, so that the design of the chip can be processed in a model calling mode, and the test efficiency and the test accuracy of the chip are improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a chip design method according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for determining power consumption information according to an embodiment of the present invention;
FIG. 3 is a flow chart of estimating dynamic power consumption according to an embodiment of the present invention;
FIG. 4 is a flow chart of estimating static power consumption according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a chip design apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a chip design apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As an optional implementation, fig. 1 is a flowchart of a chip design method provided in an embodiment of the present invention, and referring to fig. 1, the chip design method provided in the embodiment of the present invention may include:
and S100, calling a design model of the chip at the current level design stage.
The design model includes at least: basic information of the chip in the current level design stage, power consumption information estimated by the design model, and selectable implementation mode combination; the power consumption information is determined based on the design attribute of the chip in the next stage of design, and the abstraction level of the next stage of design is lower than that of the current stage of design.
The current stage design stage of the chip may be any stage design stage of the chip, such as any one of a software stage, a behavioral stage, a transmission (RTL) stage, a gate stage, and a circuit stage; the next stage of design is the next stage of the current stage of design, and the abstraction level of the next stage of design is lower than that of the current stage of design; if the current stage of the chip is the RTL stage, the next stage is the gate stage.
The embodiment of the invention can model part or all of the design content of the chip in the current level design stage to obtain the design model of the chip in the current level design stage; in the embodiment of the present invention, the design model in the current stage of design may include at least the following design contents: basic information of the chip in the current level design stage, power consumption information estimated by the design model and optional implementation modes are combined;
optionally, the basic information of the current stage design stage may include design targets of the current stage design stage, for example, chip functions of the current stage design stage; the power consumption information is determined based on the design attributes of the chip in the next stage of design, including power consumption estimated values and the like; the selectable implementation combinations can be considered as selectable implementation combinations of the units of the current level design stage and/or target implementation combinations of the next level design stage; the target implementation mode is the implementation mode of the chip determined according to the design attribute in the next stage of design, and is used as reference information for estimating the power consumption estimation value of the chip in the current stage of design;
the implementation modes of the chip at each stage of design are different, for example, the RTL stage mainly uses a hardware description language (such as Verilog or VHDL) to describe the logic function of the chip, and the RTL description is used for explaining the movement of data among registers and describing the register-level implementation of the hardware; the register stage unit comprises a register, a counter, a multiplexer, an arithmetic logic unit and the like, basic operations on data comprise arithmetic operation, logic operation, storage operation, shifting, circulating operation and the like, and the register stage of hardware is realized by the time sequence relation among register stage elements, hardware resource allocation, scheduling, microcode control unit design, bus design and the like; the embodiment of the invention can define the unit implementation mode of the RTL level design stage;
the gate level of a chip is to describe the chip functions by using logic units (dependent cell libraries, such as logic gates, etc.), and the embodiment of the invention can define the logic unit implementation manner of the gate level design stage.
In an example, taking the current-level design stage as an RTL level as an example, the embodiment of the present invention may model part or all of design contents of a chip at the RTL level to obtain an RTL-level design model, where the RTL-level design model may at least include the following design contents: RLT level basic information (such as RTL information), power consumption information estimated by RTL level design models, and selectable implementation mode combinations;
in the embodiment of the present invention, the design model at the current level design stage includes power consumption information estimated by the design model, and the power consumption estimation information may be determined based on the design attribute of the chip at the next level design stage, for example, the power consumption information at the RTL level of the chip may be determined based on the design attribute at the gate level of the chip; because the abstract level of the next stage design stage is lower than that of the current stage design stage, the power consumption information of the chip in the current stage design stage is estimated based on the design attribute of the chip in the next stage design stage, so that the power consumption estimation result is more accurate.
After modeling part or all of the design content of the chip in the current-level design stage to obtain the design model of the chip in the current-level design stage, the embodiment of the invention can call the design model of the current-level design stage when the chip design stage reaches the current-level design stage so as to design the chip in the current-level design stage by using the design model.
And step S110, determining a design result of the chip at the current level design stage by using the design model.
Based on a design model including part or all of the contents of a chip in the current-level design stage, the embodiment of the invention can utilize the design model to realize part or all of the design tasks of the chip in the current-level design stage and determine the design result of the chip in the current-level design stage; the design result includes, for example, a final implementation manner used by the chip at the current stage of design, power consumption information, a target implementation manner of the next stage of design determined based on the design attribute of the chip at the next stage of design, and the like.
The chip design method provided by the embodiment of the invention can model part or all of the design content of the chip in the current level design stage to obtain the design model of the chip in the current level design stage, so that the design model of the current level design stage can be called in the current level design stage of the chip; the design model may include at least the following design contents in the current stage of design: basic information of the chip in the current level design stage, power consumption information estimated by the design model, and selectable implementation mode combination; the power consumption information is determined based on the design attribute of the chip in the next stage of design, and the abstract level of the next stage of design is lower than that of the current stage of design; furthermore, the embodiment of the invention can determine the design result of the chip in the current level design stage by using the design model, and complete the design task of the chip in the current level design stage. Therefore, the embodiment of the invention can model part or all of the design content of the chip in at least one stage of design stage and set the design model of the chip in at least one stage of design stage, so that the design of the chip can be processed in a model calling mode, and the test efficiency and the test accuracy of the chip are improved.
It should be noted that the content included in the design model of the chip at the current level design stage may be set according to the actual situation, and is not limited to the content described above, that is, the design content included in the design model may be flexibly set according to the chip design requirement in the embodiment of the present invention, so as to facilitate the chip design.
An important link of chip design is power consumption optimization based on power consumption estimation, so accurate power consumption estimation is beneficial to chip design; power consumption estimation is typically performed at multiple design stages of a chip design, e.g., at the software level, the behavioral level, the transmission (RTL) level, the gate level, and the circuit level of the chip, respectively; it can be understood that, the earlier stage of chip design, the higher the abstraction level, the lower the accuracy of power consumption estimation, for example, the power consumption estimation result in the RTL design stage and the power consumption estimation result in the gate level design stage generally have a larger difference, so there is a need to improve the accuracy of power consumption estimation to be more beneficial to chip design.
The existing power consumption estimation method is that power consumption estimation is independently performed at a software level, a behavior level, an RTL level, a gate level and a circuit level of a chip respectively, namely, independent power consumption estimation is performed at different chip design stages according to information of the design stages:
taking an RTL level design stage as an example, an RTL level in the chip design process mainly uses a hardware description language and describes the chip functions in a register level description mode; when estimating the power consumption of a chip at the RTL level, the current common method is: establishing a power consumption information formula for the design component (for example, the power consumption information formula is established by simulating, counting power consumption data and drawing a curve form under different environment variable combinations); then, through static analysis circuit structure or dynamic simulation, collecting circuit action probability data, substituting the circuit action probability data into the power consumption information formula, and obtaining the power consumption value of each module; finally, summing the power consumption values of all the modules to obtain estimated power consumption;
the RTL level can obtain a gate level (such as a gate level Netlist) after logic synthesis, and the gate level can realize the chip function by using a specific logic unit; the power consumption estimation of the chip is carried out at a gate level, the basic unit of the power consumption estimation is a standard unit in a unit library, and a power consumption equation is obtained through circuit simulation, so that the power consumption estimation is more accurate compared with the power consumption estimation of an RTL level.
It can be seen that, due to different abstraction levels, the power consumption estimation result at the RTL level and the power consumption estimation result at the gate level may have a large difference, and the large power consumption estimation difference undoubtedly causes a barrier to power consumption optimization, thereby affecting chip design. Based on the design attribute of the chip at the next stage of design, the embodiment of the invention can estimate the power consumption information of the chip at the current stage of design, thereby improving the accuracy of the estimated power consumption information of the chip at the current stage of design.
Optionally, fig. 2 shows a process of obtaining power consumption information by predicting a design model provided in the embodiment of the present invention, where the process may be applied to estimate the power consumption information of a chip in a current-level design stage, for example, the power consumption information of the chip in an RLT-level design stage is estimated based on a design attribute of the chip in a gate-level design stage; as shown in FIG. 2, the process may be performed by a design model, and may include:
and step S200, acquiring the design attribute of the input chip at the next stage of design.
The design attributes may be input into a design model. The design attributes of the next-level design stage are the design requirements of the next-level design stage, such as the design timing sequence limiting parameters and the unit area limiting parameters of the chip at the next-level design stage. Taking the next-level design stage as a gate-level design stage as an example, the design attribute may be used to define the contents of the design timing, the power consumption of the cell, the area of the cell, and the like, and accordingly, the design timing defining parameter may be used to define the cell timing, and the cell area defining parameter is used to define the cell area. Optionally, the design attribute may also be a design requirement such as performance priority or low power consumption priority.
The design attributes of the chip at each stage of design stage can be preset; for example, the design attributes may be set and configured in the design tool in advance by a user, or configured in the chip simulation tool as an optimization condition of the design simulation process of the chip at each stage of the design stage.
And step S210, determining the target unit type of the chip in the next stage of design stage and the target implementation mode corresponding to the target unit type according to the design attribute.
After the design model acquires the design attribute of the input chip in the next design stage, the design model can determine the target unit type of the chip in the next design stage and the target implementation mode corresponding to the target unit type based on the continuously collected information of the next design stage; and estimating the power consumption information of the chip at the current level design stage by a table look-up mode according to the target implementation mode.
Optionally, the target unit type refers to a unit type used by the chip at the next stage of design, and one unit type can implement one basic function; for example, in the design description of the RTL level, different units of the register level may be used to implement different basic functions, and after the functions of the units of the register level are integrated, the logic functions of the chip may be formed;
the implementation of each unit may be different, or one unit may have multiple implementations, for example, different kinds of units may implement different basic functions, and a unit implementing the same basic function may include multiple implementations.
The method and the device can determine the target unit type of the chip in the next stage of design stage according to the design attribute based on the information of the chip in the next stage of design stage continuously collected by the design model, and can further determine the target implementation mode corresponding to the target unit type after determining the target unit type;
optionally, the design attribute may directly define a target unit type of the chip at the next stage of design, or may be a target unit type that is queried from a unit library and conforms to the design attribute, and the unit library may record multiple types of units.
And step S220, estimating the power consumption information of the chip in the current level design stage according to the target implementation mode.
As an optional implementation, the power consumption information of the chip at the current stage of design may include a dynamic power consumption estimation value and a static power consumption estimation value; the embodiment of the invention can estimate the dynamic power consumption estimated value and the static power consumption estimated value of the chip in the current level design stage in a table look-up mode according to the target implementation mode, thereby realizing the estimation of the power consumption information of the chip in the current level design stage.
Taking power consumption estimation in an RTL level design stage as an example, dynamic power consumption refers to power consumption consumed in a switching logic state conversion process, and a calculation formula of the dynamic power consumption may be Pd ═ CV2And F, wherein C is a load, V is a voltage swing, and F is the frequency of logic state transition. Static power consumption (also referred to as leakage power consumption) is power consumption consumed when a transistor does not perform a switching operation;
in the dynamic power consumption estimation process, a spreadsheet (spreadsheet) or selected library may provide an approximate number of gates and activity values for each module, mW/MHz data and associated power consumption estimates, specifically by estimating the number of gates per module (number of cells per type of library) and activity values for each module, and determining the energy consumed by each type of cell when switched on and off (data in the library vendor's manual determines the power consumption speed ratio (mW/MHz)).
Prior to synthesis, the number of gates can be estimated based on the chosen architecture and an understanding of the design itself. For example, the approximate number of gates can be derived from the bus width, word length, control layer, memory depth, and the like. After the bank is selected, the number of gates of the module can be estimated after initial integration using the report-reference command of Design Compiler.
One key aspect of power consumption calculation is the activity level of the module, with gates in the design all having different activity levels.
It should be noted that the power consumption estimation at any abstraction level is meaningful only when the switching operation represents the actual operating state of the chip.
Referring to fig. 3, fig. 3 shows a flow of estimating dynamic power consumption according to an embodiment of the present invention, and referring to fig. 3, the flow may include:
and step S300, acquiring a power consumption estimated value of the target implementation mode from a power consumption library of the design model.
The design model can be provided with a power consumption library, the power consumption library can record the power consumption estimated value of each implementation mode, and the embodiment of the invention can acquire the power consumption estimated value of the target implementation mode from the power consumption library.
And S310, determining an activity value of the target implementation mode according to a design simulation result of the target implementation mode.
In this embodiment, the chip is simulated at the current stage of design to obtain a design simulation result, and then the activity level (i.e., activity value) of the specific implementation manner can be estimated according to the design simulation result. Specifically, after the design is simulated, the activity value of the target implementation mode is estimated according to the switching action turnover rate in the design simulation result.
In this step, since the target implementation has already been determined, the corresponding design simulation result is also the result obtained by the simulation performed by the specific target implementation.
And step S320, estimating a dynamic power consumption estimated value of the chip in the current stage of design according to the power consumption estimated value and the activity value.
When a plurality of target implementation modes are included, the power consumption estimated value and the activity value of each target implementation mode can be calculated one by one, the dynamic power consumption estimated value of each target implementation mode is calculated, and the dynamic power consumption estimated values of the target implementation modes are summed to obtain the dynamic power consumption estimated value of the chip in the current stage of design.
In this embodiment, the static power consumption estimation process may estimate based on the power consumption leakage data and the static probability of the target implementation. Since the leakage in the high and low states of different cell types is different, the power consumption leakage data analysis must be based on the static probability that the signal is in a certain logic state. The static probability is expressed as a number between 0 and 1, which can be estimated according to the function of the signal. For example, the logic "1" static probability (SP1) of an active-low reset signal is typically equal to or close to 1.0 (100%). For a data bus signal, its SP1 can be assumed to be typically 0.5 (50%) unless some architectural characteristics suggest other probabilities. After the library is selected, the static probability can be calculated during simulation by comparing the time the signal is in a particular logic state to the total simulation time.
Referring to fig. 4, fig. 4 shows a process of estimating static power consumption according to an embodiment of the present invention, and referring to fig. 4, the process may:
and S400, acquiring power consumption leakage data of the target implementation mode from a database of the design model.
In this step, the embodiment of the present invention may obtain power consumption leakage data of the target implementation manner from the database, and the database may record the power consumption leakage data of each implementation manner.
And S410, determining the static probability of the target implementation mode through a design simulation result.
After the target implementation is determined, the static probability of the target implementation may be determined from the design simulation results corresponding to the target implementation.
And step S420, estimating a static power consumption estimation value of the chip at the current stage of design according to the power consumption leakage data and the static probability of the target implementation mode.
When the chip design comprises a plurality of target implementation modes, the static power consumption estimated value of each target implementation mode can be determined one by one according to the power consumption leakage data and the static probability of each target implementation mode, so that the static power consumption estimated values of the target implementation modes are summed to obtain the static power consumption estimated value of the chip at the current stage of design.
It can be seen that, in this embodiment, since the target implementation manner of the next stage design stage is already determined, the accuracy of the power consumption leakage data and the design simulation result is better than that of the power consumption leakage data and the design simulation result calculated for the information of the current stage design stage, and thus the estimated static power consumption value of the chip at the current stage design stage has higher accuracy.
In the embodiment of the present invention, the design model of the chip at the current stage of design may further provide a visual menu, and the menu of the design model may be displayed on the design interface of the design tool by associating the selectable implementation manners at the current stage of design with the menu and/or combining the combination options formed by combining a plurality of selectable implementation manners, so that the selectable implementation manners at the current stage of design are presented to the user through the menu and/or the combination options formed by combining a plurality of selectable implementation manners; furthermore, the user can select the selectable implementation mode used in the current level design stage and/or combine the options based on the menu, so as to determine the implementation mode used by the chip in the current level design stage, and the implementation mode can be selected more conveniently in the design process of the chip in the current level design stage. Optionally, the menu may further show a target implementation manner of the next stage design stage determined based on the design attribute of the chip at the next stage design stage, for use as a reference for estimating the power consumption estimation value of the chip at the current stage design stage.
In another embodiment of the present invention, a chip design apparatus is further provided, and the contents of the chip design apparatus described below and the contents of the above description are referred to in correspondence.
Fig. 5 shows a schematic structural diagram of a chip design apparatus provided in an embodiment of the present invention, where the apparatus may be a stand-alone apparatus or may be embedded in a chip design tool, so as to implement chip design. The chip design device provided by the embodiment of the invention can be used for chip design in each design stage of a chip and can also be used for chip design in a specific chip design stage.
Referring to fig. 5, the chip designing apparatus may include:
the calling module 1 is used for calling a design model of a chip at a current level design stage; the design model includes at least: basic information of the chip in the current level design stage, power consumption information estimated by the design model, and selectable implementation mode combination; the power consumption information is determined based on the design attribute of the chip in the next stage of design, and the abstract level of the next stage of design is lower than that of the current stage of design;
and the result determining module 2 is used for determining the design result of the chip at the current stage of design by using the design model.
The current stage design stage of the chip may be any stage design stage of the chip, such as any one of a software stage, a behavioral stage, a transmission (RTL) stage, a gate stage, and a circuit stage; the next stage of design is the next stage of the current stage of design, and the abstraction level of the next stage of design is lower than that of the current stage of design; if the current stage of the chip is the RTL stage, the next stage is the gate stage.
The basic information of the current level design stage may include design targets of the current level design stage, for example, chip functions of the current level design stage, and the like; the power consumption information is determined based on the design attributes of the chip in the next stage of design, including power consumption estimated values and the like; the selectable implementation combinations can be considered as selectable implementation combinations of the units of the current level design stage and/or target implementation combinations of the next level design stage; the target implementation mode is the implementation mode of the chip determined according to the design attribute in the next level of design stage;
the design attributes of the next-level design stage are the design requirements of the next-level design stage, such as the design timing sequence limiting parameters and the unit area limiting parameters of the chip at the next-level design stage. Taking the next-level design stage as a gate-level design stage as an example, the design attribute may be used to define the contents of the design timing, the power consumption of the cell, the area of the cell, and the like, and accordingly, the design timing defining parameter may be used to define the cell timing, and the cell area defining parameter is used to define the cell area.
The method and the device can model part or all of the design content of the chip in the current stage of design to obtain the design model of the chip in the current stage of design, and the design model of the current stage of design can comprise part or all of the design content of the current stage of design; in the embodiment of the present invention, the design model in the current stage of design may include at least the following design contents: basic information of the chip in the current level design stage, power consumption information estimated by the design model and optional implementation modes are combined; the design model of the current level design stage of the chip is called through the calling module 1, and the result determining module 2 determines the design result of the chip at the current level design stage by using the design model, so that the design of the chip at the current level design stage is realized.
Therefore, the embodiment of the invention can model part or all of the design content of the chip in at least one stage of design stage and set the design model of the chip in at least one stage of design stage, so that the design of the chip can be processed in a model calling mode, and the test efficiency and the test accuracy of the chip are improved.
Optionally, with continuing reference to fig. 5, the chip design apparatus further includes a power consumption estimation module 3; the power consumption estimation module 3 can be arranged in the design model and used for estimating power consumption information;
the power consumption estimation module 3 may be configured to: obtaining the design attribute of an input chip at the next stage of design; determining the target unit type of the chip in the next stage of design stage and the target implementation mode corresponding to the target unit type according to the design attribute; and estimating the power consumption information of the chip in the current level design stage according to the target implementation mode.
Optionally, the power consumption estimation module is configured to estimate power consumption information of the chip at a current level design stage according to the target implementation manner, and includes: and estimating a dynamic power consumption estimation value and a static power consumption estimation value of the chip at the current stage of design according to the target implementation mode.
Optionally, the power consumption estimation module is configured to estimate a dynamic power consumption estimation value of the chip at a current stage of design according to the target implementation manner, and includes: acquiring a power consumption estimated value of the target implementation mode from a power consumption library of a design model; determining an activity value of the target implementation mode according to a design simulation result of the target implementation mode; and estimating the dynamic power consumption estimated value of the chip in the current stage of design according to the power consumption estimated value and the activity value.
Optionally, the power consumption estimation module is configured to estimate a static power consumption estimation value of the chip at a current stage of design according to the target implementation manner, and includes: acquiring power consumption leakage data of the target implementation mode from a database of a design model; determining the static probability of the target implementation mode through a design simulation result; and estimating a static power consumption estimation value of the chip at the current stage of design according to the power consumption leakage data and the static probability of the target implementation mode.
It can be seen that, in this embodiment, since the target implementation manner of the next stage design stage is already determined, the accuracy of the power consumption leakage data and the design simulation result is better than that of the power consumption leakage data and the design simulation result calculated for the information of the current stage design stage, and thus the estimated static power consumption value of the chip at the current stage design stage has higher accuracy.
Optionally, the result determining module is configured to determine a design result of the chip at the current stage of design by using the design model, and may specifically include: displaying a menu of the design model; the menu is associated with selectable implementation modes of the current stage of design and/or combination options formed by combining a plurality of selectable implementation modes; and determining the implementation mode of the chip used in the current level design stage through the menu.
In the embodiment of the present invention, the design model of the chip at the current stage of design may further provide a visual menu, and the menu of the design model may be displayed on the design interface of the design tool by associating the selectable implementation manners at the current stage of design with the menu and/or combining the combination options formed by combining a plurality of selectable implementation manners, so that the selectable implementation manners at the current stage of design are presented to the user through the menu and/or the combination options formed by combining a plurality of selectable implementation manners; furthermore, the user can select the selectable implementation mode used in the current level design stage and/or combine the options based on the menu, so as to determine the implementation mode used by the chip in the current level design stage, and the implementation mode can be selected more conveniently in the design process of the chip in the current level design stage.
In another embodiment of the present invention, a chip design apparatus is further provided, and the contents of the chip design apparatus described below may be referred to in correspondence with the contents described above.
Fig. 6 shows a schematic structural diagram of a chip design apparatus provided in an embodiment of the present invention, where the chip design apparatus includes a chip design device 10, and the chip design device 10 is the chip design device in the above embodiment. The device can be an independent device, and can also be integrated with other devices, so that the chip is designed.
In the embodiment of the invention, the design model of the chip at the at least one stage of design stage is obtained by modeling part or all of the design content of the chip at the at least one stage of design stage, so that the design model is utilized to realize chip design, the design efficiency of the chip is improved, and the accuracy of the chip design is improved.
While various embodiments of the present invention have been described above, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in connection with the embodiments of the present invention.
Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of chip design, comprising:
calling a design model of a chip at a current level design stage; the design model includes at least: basic information of the chip in the current level design stage, power consumption information estimated by the design model, and selectable implementation mode combination; the power consumption information is determined based on the design attribute of the chip in the next stage of design, and the abstract level of the next stage of design is lower than that of the current stage of design;
and determining the design result of the chip at the current stage of design by using the design model.
2. The chip design method according to claim 1, wherein the process of estimating the power consumption information by the design model comprises:
obtaining the design attribute of an input chip at the next stage of design;
determining the target unit type of the chip in the next stage of design stage and the target implementation mode corresponding to the target unit type according to the design attribute;
and estimating the power consumption information of the chip in the current level design stage according to the target implementation mode.
3. The chip design method according to claim 2, wherein the estimating power consumption information of the chip at the current stage of design according to the target implementation comprises:
and estimating a dynamic power consumption estimation value and a static power consumption estimation value of the chip at the current stage of design according to the target implementation mode.
4. The chip design method according to claim 3, wherein the estimating the dynamic power consumption estimation value of the chip at the current stage of design according to the target implementation comprises:
acquiring a power consumption estimated value of the target implementation mode from a power consumption library of a design model;
determining an activity value of the target implementation mode according to a design simulation result of the target implementation mode;
and estimating the dynamic power consumption estimated value of the chip in the current stage of design according to the power consumption estimated value and the activity value.
5. The chip design method of claim 3, wherein the estimating the static power consumption estimation value of the chip at the current stage of design according to the target implementation comprises:
acquiring power consumption leakage data of the target implementation mode from a database of a design model;
determining the static probability of the target implementation mode through a design simulation result;
and estimating a static power consumption estimation value of the chip at the current stage of design according to the power consumption leakage data and the static probability of the target implementation mode.
6. The chip design method of claim 1, wherein determining the design result of the chip at the current stage of design using the design model comprises:
displaying a menu of the design model; the menu is associated with selectable implementation modes of the current stage of design and/or combination options formed by combining a plurality of selectable implementation modes;
and determining the implementation mode of the chip used in the current level design stage through the menu.
7. The method of claim 1, wherein the design attributes include a design timing definition parameter and a cell area definition parameter.
8. The method of any of claims 1 to 7, wherein the current stage design stage is an RTL stage and the next stage design stage is a gate stage.
9. A chip design apparatus, comprising:
the calling module is used for calling the design model of the chip at the current level design stage; the design model includes at least: basic information of the chip in the current level design stage, power consumption information estimated by the design model, and selectable implementation mode combination; the power consumption information is determined based on the design attribute of the chip in the next stage of design, and the abstract level of the next stage of design is lower than that of the current stage of design;
and the result determining module is used for determining the design result of the chip in the current level design stage by using the design model.
10. A chip design apparatus, comprising: the chip designing apparatus as recited in claim 9.
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