CN112579294B

CN112579294B - Method and device for realizing multi-core scheduling of virtual machine

Info

Publication number: CN112579294B
Application number: CN202011560917.9A
Authority: CN
Inventors: 李燕
Original assignee: Kedong Guangzhou Software Technology Co Ltd
Current assignee: Kedong Guangzhou Software Technology Co Ltd
Priority date: 2020-12-25
Filing date: 2020-12-25
Publication date: 2022-03-25
Anticipated expiration: 2040-12-25
Also published as: CN112579294A

Abstract

The application provides a method and a device for realizing multi-core scheduling of a virtual machine, wherein the method comprises the following steps: correspondingly configuring a main virtual machine of a virtual machine and N-1 shadow virtual machines on N CPU cores; scheduling the primary virtual machine and the shadow virtual machine to respectively run on corresponding CPU cores under the same time window through a time scheduling table; the time schedule is configured with time windows for scheduling the primary virtual machine and the shadow virtual machine to run. Based on the method and the device, the CPU resource utilization rate and the real-time performance of the virtual machine can be better coordinated.

Description

Method and device for realizing multi-core scheduling of virtual machine

Technical Field

The present application relates to the field of virtual machines, and in particular, to a method and an apparatus for implementing multi-core scheduling of a virtual machine.

Background

Virtual machine technology has appeared in the sixty-seven decades of the last century and is mainly applied to mainframes. Generally, the Virtual Machine technology refers to a system-level virtualization technology, and virtualization software in the system-level virtualization technology is called a Virtual Machine Monitor (VMM), which aims at a Virtual instruction system architecture. The core of the system level virtualization technology is to construct a virtual machine monitor, then create a virtual machine on the virtual machine monitor, and place an operating system which is directly run on an actual hardware platform in the virtual machine for running. Through the virtual machine monitor, a plurality of virtual machines can be operated on a single physical machine, each virtual machine can support operation of different operating systems, and the operating systems operated on the virtual machines have better isolation and expansibility. The appearance of the virtual machine technology realizes the possibility that a plurality of users commonly use rich resources on a mainframe system, realizes higher utilization rate of mainframe equipment and saves cost. In the case where a plurality of virtual machines coexist, scheduling of the virtual machines is particularly important. The scheduling of the virtual machines determines the running time and running state of the virtual machines. Due to the adoption of the proper scheduling strategy, the resource sharing maximization can be realized, and the time cost can be saved.

In the prior art, scheduling algorithms such as time slice scheduling, non-preemptive priority scheduling, preemptive priority scheduling and the like are mainly adopted to realize scheduling of multiple virtual machines. However, these scheduling algorithms can only implement time slot scheduling, and therefore, the scheduling accuracy of these scheduling algorithms is not high.

Disclosure of Invention

In view of this, the present application provides a method and an apparatus for implementing multi-core scheduling of a virtual machine, so as to improve the real-time performance of virtual machine scheduling.

A first aspect of the present application provides a method for implementing multi-core scheduling of a virtual machine, including:

correspondingly configuring a main virtual machine of a virtual machine and N-1 shadow virtual machines on N CPU cores;

scheduling the primary virtual machine and the shadow virtual machine to respectively run on corresponding CPU cores under the same time window through a time scheduling table; the time schedule is configured with time windows for scheduling the primary virtual machine and the shadow virtual machine to run.

Therefore, the primary virtual machine and the shadow virtual machine are correspondingly configured on the N CPU cores, and the running of the virtual machines is scheduled by utilizing the time scheduling tables configured with different time windows of different primary virtual machines running on the CPUs in a time-sharing mode, so that the scheduling precision can be improved, and the time scheduling tables can be applied to the CPU cores, and the scheduling instantaneity is ensured.

As an implementation manner of the first aspect, the primary virtual machine and the shadow virtual machine are further configured with different virtual CPU identities for virtual machine differentiation.

Therefore, by setting different virtual CPU identifications, whether the currently running primary virtual machine or the shadow virtual machine is the primary virtual machine or the shadow virtual machine can be quickly identified, and support is provided for a multi-core operating system in the virtual machine.

As an implementation manner of the first aspect, the time schedule is configured as a self-starting time schedule, and the time schedule starts the CPU identification of the running CPU core, so as to establish a mapping relationship between the CPU core and the time schedule.

Therefore, an implementation mode of the time scheduling table is provided, and real-time scheduling of the virtual machine is achieved through the time scheduling table.

As an implementation manner of the first aspect, the mapping relationship between the designated CPU core and the time schedule is dynamically adjusted according to the demand.

As an implementation manner of the first aspect, under a time window of the time schedule, each CPU core runs a virtual machine currently configured to the CPU core, and a virtual machine not configured to the currently running CPU core is an idle virtual machine.

As an implementation of the first aspect, the shadow virtual machine has the same address space, scheduling priority, or scheduling type as the primary virtual machine.

As an implementation manner of the first aspect, when the primary virtual machine and each shadow virtual machine are started, the primary virtual machine is configured on the started CPU core first, and the shadow virtual machine is configured on the started CPU core again.

A second aspect of the present application provides an apparatus for implementing multi-core scheduling of a virtual machine, including:

the configuration module is used for correspondingly configuring a main virtual machine and N-1 shadow virtual machines of a virtual machine to N CPU cores;

the scheduling module is used for scheduling the primary virtual machine and the shadow virtual machine to respectively run on corresponding CPU cores under the same time window through a time scheduling table; the time schedule is configured with time windows for scheduling the primary virtual machine and the shadow virtual machine to run.

A third aspect of the present application provides a computing device comprising:

a bus;

a communication interface connected to the bus;

at least one processor coupled to the bus; and

at least one memory, connected to the bus, storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform a method for implementing multi-core scheduling of a virtual machine according to any one of the first aspect.

A fourth aspect of the present application provides a computer-readable storage medium, on which program instructions are stored, which, when executed by a computer, cause the computer to perform an implementation method of multi-core scheduling of a virtual machine according to any one of the above first aspects.

In conclusion, the technical scheme provided by the application can better coordinate the CPU resource utilization rate and the real-time performance of the virtual machine, and improve the scheduling precision of the virtual machine.

Drawings

Fig. 1 is a flowchart of an implementation method for multi-core scheduling of a virtual machine according to an embodiment of the present application;

fig. 2 is a schematic diagram of CPU core affinity of a virtual machine according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a time schedule of a virtual machine according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of an apparatus for implementing multi-core scheduling of a virtual machine according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

The terms "first, second, third and the like" or "module a, module B, module C and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order, it being understood that specific orders or sequences may be interchanged where permissible to effect embodiments of the present application in other than those illustrated or described herein.

In the following description, reference to reference numerals indicating steps, such as S110, S120 … …, etc., does not necessarily indicate that the steps are performed in this order, and the order of the preceding and following steps may be interchanged or performed simultaneously, where permissible.

The term "comprising" as used in the specification and claims should not be construed as being limited to the contents listed thereafter; it does not exclude other elements or steps. It should therefore be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, and groups thereof. Thus, the expression "an apparatus comprising the devices a and B" should not be limited to an apparatus consisting of only the components a and B.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, as would be apparent to one of ordinary skill in the art from this disclosure.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. In the case of inconsistency, the meaning described in the present specification or the meaning derived from the content described in the present specification shall control. In addition, the terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

To accurately describe the technical content of the present application and to accurately understand the present application, the terms used in the present specification are given the following explanations or definitions before the description of the specific embodiments.

1. Virtual Machine (VM): the computer system is a complete computer system which has complete hardware system functions and runs in a completely isolated environment through software simulation. The work that can be done in a physical computer can be implemented in a virtual machine. When creating a virtual machine in a computer, it is necessary to use a part of the hard disk and the memory capacity of the physical machine as the hard disk and the memory capacity of the virtual machine. Each virtual machine has a separate CMOS, hard disk, and operating system.

2. A primary virtual machine: in the embodiment of the application, the primary virtual machine refers to a first child virtual machine created on a system of virtual machines, and after entering the primary virtual machine, any operation performed on the primary virtual machine is independent of the shadow virtual machine.

3. The shadow virtual machine: in the embodiment of the present application, the shadow virtual machine refers to a child virtual machine created on a system of the virtual machine, and after entering the shadow virtual machine, any operation performed on the shadow virtual machine is independent from any operation performed on the primary virtual machine, so that the shadow virtual machine and the primary virtual machine are independently operating child virtual machines.

The application provides a method for realizing multi-core scheduling of a virtual machine, which can enable the scheduling of the virtual machine to be accurate to a time point and achieve the purpose of improving the scheduling accuracy.

The following describes in detail a method for implementing multi-core scheduling of a virtual machine according to an embodiment of the present application with reference to the accompanying drawings. Specifically, as shown in fig. 1, the method may include the following steps S110 to S120:

s110: correspondingly configuring a main virtual machine of a virtual machine and N-1 shadow virtual machines on N CPU cores.

S120: scheduling the primary virtual machine and the shadow virtual machine to respectively run on corresponding CPU cores under the same time window through a time scheduling table; the time schedule is configured with time windows for scheduling the primary virtual machine and the shadow virtual machine to run.

Specifically, in this embodiment, the virtual machine can be run on a plurality of CPU cores by the shadow virtual machine technology. In addition, the time schedule provides a real-time scheduling strategy for the multi-core operation of the virtual machine. Specifically, each main virtual machine and each shadow virtual machine can only run in a corresponding time window, so that multi-core scheduling of the virtual machines is guaranteed.

In this embodiment, the shadow virtual machine has the same address space, scheduling priority, or scheduling type as the primary virtual machine.

The primary virtual machine and the shadow virtual machine are also configured with different virtual CPU identifications for distinguishing the virtual machines. Preferably, the virtual CPU identifier may be a virtual CPUID. Through the virtual CPU identification, whether the current running is the primary virtual machine or the shadow virtual machine can be distinguished. In addition, in the multi-core scheduling of the virtual machines in this embodiment, the first started virtual machine is a primary virtual machine, and the subsequently started virtual machines are shadow virtual machines.

In addition, in the present embodiment, the time schedule table in step S120 is configured as a self-starting time schedule table, and the time schedule table configures the CPU identification of the CPU core whose time schedule table starts to run, so as to establish the mapping relationship between the CPU core and the time schedule table. In addition, the time scheduling table can dynamically adjust the mapping relation between the appointed CPU core and the time scheduling table according to the requirement. And under the time window of the time scheduling table, each CPU core runs the virtual machine which is currently configured on the CPU core, and the virtual machine which is not configured on the currently running CPU core is an idle virtual machine.

Based on the configuration process of the primary virtual machine and the shadow virtual machine in this embodiment, when the virtual machine starts to run, the primary virtual machine is configured on the CPU core that is started first, and the shadow virtual machine is configured on the CPU core that is started again.

In order to further better understand the scheduling method of the virtual machine provided in the embodiment of the present application, a specific implementation of the method for implementing multi-core scheduling of the virtual machine provided in the embodiment of the present application is described below with reference to fig. 2 to 3. Before the present embodiment is described in detail, it should be noted that:

in this embodiment, one virtual machine may comprise one primary virtual machine; alternatively, a virtual machine may include a primary virtual machine and at least one shadow virtual machine.

Referring to fig. 2, first, the CPU core parent attribute of the virtual machine is configured.

Specifically, a user needs to configure a CPU core set, i.e., the CPU core parent attribute, in which the virtual machine operates according to actual requirements. The following two cases are included:

case 1: and configuring the virtual machine to run on a CPU core. Binding virtual machine 3(VM3) to run on CPU0, such as shown in FIG. 2; virtual machine 4(VM4) is bound to run on CPU1 as shown in fig. 2, for example.

Case 2: and configuring the virtual machine to run on a plurality of CPU cores. Binding virtual machine 1(VM1) to run on

CPUs

0, 1, 2, 3 as shown, for example, in FIG. 2; for example, as shown in fig. 2, virtual machine 2(VM2) is bound to run on CPU0, 1; further for example, as shown in FIG. 2, virtual machine 5(VM5) is bound to run on

CPUs

0, 2, 3.

After configuring the CPU core affinity of the virtual machine, a shadow virtual machine in the virtual machine needs to be constructed. The number of the shadow virtual machines required to be constructed in the step is 1 less than the number of CPUs (central processing units) for affinity operation of the virtual machines.

In this step, the shadow virtual machine and the primary virtual machine use the same address space, scheduling type, scheduling time window, and scheduling priority. In addition, the shadow virtual machine also has a CPU and a system stack which run independently. In this embodiment, preferably, the primary virtual machine may be bound to a first CPU core (primary CPU core) to run, and the shadow virtual machine may be bound to other CPU cores (secondary CPU cores) to run in turn.

As an implementation, it is possible to distinguish which CPU is currently bound and running from the CPUID. Preferably, the CPUID of the master virtual machine bound to the first CPU core (master CPU core) is 0, and the CPUID of the slave CPU core bound to the shadow virtual machine may be any value of 1, 2, and 3 … …. For example, virtual machine 1(VM1) shown in fig. 2 is bound to run on

CPUs

0, 1, 2 and 3, wherein its primary virtual machine is bound to run on CPU0, and its shadow virtual machine is bound to run on CPU1, CPU2 and CPU3 in turn; for example, virtual machine 2(VM2) shown in fig. 2 is bound to run on CPU0, 1, its primary virtual machine is bound to run on CPU0, and its shadow virtual machine is bound to run on CPU 1; for example, the virtual machine 5(VM5) shown in fig. 2 is bound to run on the

CPUs

0, 2 and 3, the primary virtual machine is bound to run on the CPU0, and the shadow virtual machine is bound to run on the

CPUs

2 and 3 in turn. In addition, when the virtual machine only has a primary virtual machine and does not have a shadow virtual machine, the virtual machine can be bound to a CPU core with any ID to run. For example, virtual machine 3(VM3) as shown in fig. 2 is bound to run on CPU0, because it does not have a shadow virtual machine, so its primary virtual machine is bound to run on CPU 0; again, for example, virtual machine 4(VM4) shown in fig. 2 is bound to run on CPU1, which again does not have a shadow virtual machine present, and therefore its primary virtual machine is bound to run on CPU 1.

After a shadow virtual machine in a virtual machine is built, a time schedule table of the virtual machine needs to be configured, and the running of the virtual machine is scheduled by utilizing the time schedule table.

As shown in fig. 3, a time schedule of the virtual machine is provided for this step. In this time schedule, the runtime window of each virtual machine on each CPU core needs to be configured.

The method for using the time schedule provided by this step is described by taking the example that the VM2 is bound to the CPU0 and the CPU 1. Wherein the primary virtual machine configuration of VM2 runs on CPU0 and the shadow virtual machine configuration of VM2 runs on CPU 1. As shown in fig. 3, the CPU0 main frame runtime is, in order: VM1 operation duration T1 → VM2 operation duration T2 → idle duration T3 → VM1 operation duration T4 → VM5 operation duration T5 → idle duration T6 → VM2 operation duration T7. In contrast to the main frame runtime of the CPU0, the CPU1 main frame runtime, in the time windows T2 and T7 where the CPU0 runs the VM2, the CPU1 runs the shadow virtual machine of the VM 2. (the principle that the main virtual machine and the shadow virtual machine of other virtual machines run on corresponding CPU cores is similar only by taking VM2 as an example here, and details are not repeated here)

Based on the specific implementation manner of the scheduling method of the virtual machine, the virtual machine in this embodiment is similar to the entity multi-core machine in starting, and the main CPU core is started first, and then the slave CPU cores are started in sequence.

In addition, when the virtual machine runs, each CPU core only binds to the virtual machine scheduled by the current time schedule, and the virtual machine which is not bound to the currently running CPU core is considered as an idle virtual machine. Through the setting, the same time scheduling table can be applied to a plurality of CPU cores, and the real-time performance of the primary virtual machine and the shadow virtual machine can be ensured, so that the real-time performance of the virtual machine running on the time window of the time scheduling table is ensured.

The present application further provides an apparatus for implementing multi-core scheduling of a virtual machine, as shown in fig. 4, including:

the configuration module is used for correspondingly configuring a main virtual machine and N-1 shadow virtual machines to N CPU cores; the shadow virtual machine is subordinate to the primary virtual machine;

the scheduling module is used for scheduling the N CPU cores to respectively run the correspondingly configured primary virtual machine or shadow virtual machine under the same time window through a time scheduling table; the time schedule is configured with time windows for scheduling the primary virtual machine and the shadow virtual machine to run.

In this embodiment, the primary virtual machine and the shadow virtual machine are further configured with different virtual CPU identifiers for virtual machine differentiation. The time scheduling table in the scheduling module is configured to be a self-starting time scheduling table, and the CPU identification of the CPU core started and operated by the time scheduling table is configured to establish the mapping relation between the CPU core and the time scheduling table. In addition, the mapping relation between the designated CPU core and the time scheduling table can be dynamically adjusted according to the requirement.

And under the time window of the time scheduling table, each CPU core runs the virtual machine which is currently configured on the CPU core, and the virtual machine which is not configured on the currently running CPU core is an idle virtual machine.

The shadow virtual machine has the same address space, scheduling priority, or scheduling type as the primary virtual machine.

When the primary virtual machine and each shadow virtual machine are started, the primary virtual machine is configured on the started CPU core, and the shadow virtual machine is configured on the started CPU core.

The present application further provides a computing device, described in detail below with reference to fig. 5.

The computing device 400 includes a processor 410, a memory 420, a communication interface 430, and a bus 440.

It should be appreciated that the communication interface 430 in the computing device 410 shown in this figure may be used to communicate with other devices.

The processor 410 may be coupled to the memory 420. The memory 420 may be used to store the program codes and data. Therefore, the memory 420 may be a storage unit inside the processor 410, an external storage unit independent of the processor 410, or a component including a storage unit inside the processor 410 and an external storage unit independent of the processor 410.

Optionally, computing device 400 may also include a bus 440. The memory 420 and the communication interface 430 may be connected to the processor 410 through a bus 440. The bus 440 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown, but this does not represent only one bus or one type of bus.

It should be understood that, in the embodiment of the present invention, the processor 410 may adopt a Central Processing Unit (CPU). The processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 410 may employ one or more integrated circuits for executing related programs to implement the technical solutions provided by the embodiments of the present invention.

The memory 420 may include a read-only memory and a random access memory, and provides instructions and data to the processor 410. A portion of the processor 410 may also include non-volatile random access memory. For example, the processor 410 may also store information of the device type.

When the computing device 400 is running, the processor 410 executes the computer-executable instructions in the memory 420 to perform the operational steps of method embodiment one or method embodiment two or method embodiment three.

It should be understood that the computing device 400 according to the embodiment of the present invention may correspond to a corresponding main body for executing the method according to the embodiments of the present invention, and the above and other operations and/or functions of each module in the computing device 400 are respectively for implementing corresponding flows of each method of the embodiment, and are not described herein again for brevity.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, is configured to perform the operation steps of the first method embodiment or the operation steps of the second method embodiment or the operation steps of the third method embodiment.

Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention.

Claims

1. A method for implementing multi-core scheduling of a virtual machine is characterized by comprising the following steps:

correspondingly configuring a main virtual machine of a virtual machine and N-1 shadow virtual machines on N CPU cores; the main virtual machine refers to a first sub virtual machine established on a system of the virtual machine, and the shadow virtual machine refers to the rest sub virtual machines established on the system of the virtual machine; the shadow virtual machine has the same address space, scheduling priority or scheduling type as the primary virtual machine;

scheduling the primary virtual machine and the shadow virtual machine to respectively run on corresponding CPU cores under the same time window through a time scheduling table; the time scheduling table is configured with time windows for scheduling the operation of the primary virtual machine and the shadow virtual machine; when the primary virtual machine and each shadow virtual machine are started, the primary virtual machine is configured on the started CPU core, and the shadow virtual machine is configured on the started CPU core.

2. The method of claim 1, wherein the primary virtual machine and the shadow virtual machine are further configured with different virtual CPU identifications for virtual machine differentiation.

3. The method of claim 1, wherein the time schedule is configured as a self-initiated time schedule and the time schedule initiates a CPU identification of a running CPU core to establish a mapping relationship between the CPU core and the time schedule.

4. The method of claim 3, further comprising: and dynamically adjusting the mapping relation between the appointed CPU core and the time scheduling table according to the requirement.

5. The method of claim 1, wherein each CPU core runs a virtual machine currently configured to the CPU core and a virtual machine not configured to the currently running CPU core is an idle virtual machine within a time window of the time schedule.

6. An apparatus for implementing multi-core scheduling of a virtual machine, comprising:

the configuration module is used for correspondingly configuring a main virtual machine and N-1 shadow virtual machines of a virtual machine to N CPU cores; the main virtual machine refers to a first sub virtual machine established on a system of the virtual machine, and the shadow virtual machine refers to the rest sub virtual machines established on the system of the virtual machine; the shadow virtual machine has the same address space, scheduling priority or scheduling type as the primary virtual machine;

the scheduling module is used for scheduling the primary virtual machine and the shadow virtual machine to respectively run on corresponding CPU cores under the same time window through a time scheduling table; the time scheduling table is configured with time windows for scheduling the operation of the primary virtual machine and the shadow virtual machine; when the primary virtual machine and each shadow virtual machine are started, the primary virtual machine is configured on the started CPU core, and the shadow virtual machine is configured on the started CPU core.

7. A computing device, comprising:

a bus;

a communication interface connected to the bus;

at least one processor coupled to the bus; and

at least one memory coupled to the bus and storing program instructions that, when executed by the at least one processor, cause the at least one processor to perform a method for implementing multi-core scheduling of virtual machines as recited in any of claims 1-5.

8. A computer-readable storage medium having stored thereon program instructions, which, when executed by a computer, cause the computer to perform an implementation method of multi-core scheduling of a virtual machine according to any one of claims 1 to 5.