CN112559428A - HDLC controller's FPGA chip based on PCIe - Google Patents
HDLC controller's FPGA chip based on PCIe Download PDFInfo
- Publication number
- CN112559428A CN112559428A CN202011519806.3A CN202011519806A CN112559428A CN 112559428 A CN112559428 A CN 112559428A CN 202011519806 A CN202011519806 A CN 202011519806A CN 112559428 A CN112559428 A CN 112559428A
- Authority
- CN
- China
- Prior art keywords
- hdlc
- fpga
- pcie
- hdlc controller
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 238000006243 chemical reaction Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 6
- 238000013507 mapping Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 230000007547 defect Effects 0.000 description 5
- 230000001502 supplementing effect Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Bus Control (AREA)
Abstract
The invention discloses an FPGA chip of an HDLC controller based on PCIe, wherein the HDLC controller is realized by adopting an FPGA, and the FPGA comprises an HDLC protocol transmission unit, a data cache unit and a main control unit; the HDLC protocol transmission unit comprises an HDLC data sending module and an HDLC data receiving module; the HDLC controller comprises the following steps when in work: (1) the HDLC control module interrupts signals to apply for the upper computer to correspond, wherein PCIe is connected with the upper computer and the HDLC controller and is used for converting the internal bus behavior into PCIe bus behavior; (2) the FPGA is a conversion chip and converts a PCIe bus into a plurality of paths of mutually independent E1 communication; the HDLC controller has the advantages that the HDLC controller can replace an ASIC chip to be used in the HDLC controller, the use effect is good, multiple paths of mutually independent communication can be supported, the communication mode is better, and different contents of the multiple paths of communication can be realized on the premise of not delaying work.
Description
Technical Field
The invention relates to the technical field of FPGA chips, in particular to an FPGA chip of an HDLC controller based on PCIe.
Background
The HDLC protocol is one of the most widely applied protocols in the communication field, is a bit-oriented high-level data link control procedure, has the characteristics of strong error detection function, high efficiency and synchronous transmission, an ASIC chip is currently used by the HDLC controller, but the chip has the defect of long development time, and once the chip has technical defects in the use process, the defect is difficult to solve;
in view of the above, there is a need for an improved chip for use in an existing HDLC controller, which can accommodate the current requirements for normal use of the HDLC controller.
Disclosure of Invention
Because the chip used by the HDLC controller is usually an ASIC chip, and although the chip can achieve related purposes, the chip has the problems of long development time and difficulty in maintenance, an FPGA chip is designed on the basis of the defects of the prior art, the functions of the HDLC controller can be solved, and multiple paths of mutually independent communication can be supported, so that the HDLC controller is convenient for people to use.
The technical scheme of the invention is that the HDLC controller is realized by adopting an FPGA, and the FPGA comprises an HDLC protocol transmission unit, a data cache unit and a main control unit; the HDLC protocol transmission unit comprises an HDLC data sending module and an HDLC data receiving module; the HDLC controller comprises the following steps when in work:
(1) the HDLC control module interrupts signals to apply for the upper computer to correspond, wherein PCIe is connected with the upper computer and the HDLC controller and is used for converting the internal bus behavior into PCIe bus behavior;
(2) the FPGA is a conversion chip and converts a PCIe bus into a plurality of paths of mutually independent E1 communication.
Further supplementing the technical scheme, the working of the FPGA chip comprises the following steps: firstly, DMA access is realized through an HDLC protocol transmission unit, and then data can be received or taken out through a data cache unit; and then the data is converted into a plurality of paths of mutually independent communication through bit processing, and then time slot mapping is carried out, and finally serial ports send the data.
Further supplementing the technical scheme, in the step (2), the FPGA can convert the PCIe bus into 4 paths of mutually independent E1 communications.
To further supplement the technical scheme, the FPGA adopts the logo 2 of 28ns process of purple light transmission.
To further supplement the technical scheme, the FPGA adopts the A7 series of Xilinx.
The HDLC controller has the advantages that an ASIC chip can be replaced in the HDLC controller, the use effect is good, multiple paths of mutually independent communication can be supported, the communication mode is better, and different contents of multiple paths of communication can be realized on the premise of not delaying work; and by adopting the modular design, each module can be transplanted to a new bus interface more simply and can be used repeatedly more conveniently.
Drawings
FIG. 1 is a schematic overall workflow of the present invention;
FIG. 2 is a schematic diagram of the FPGA chip of the present invention;
Detailed Description
At present, an ASIC chip is generally applied when an HDLC controller is normally used in the market, but the chip has some defects in use, such as long development time, difficulty in maintenance, single-path communication and inconvenience in use for people, so that an FPGA chip of the HDLC controller based on PCIe is designed, multiple paths of mutually independent communication can be supported, and the communication mode is better.
In order to make the technical solution more clear to those skilled in the art, the technical solution of the present invention will be explained in detail below: an HDLC controller based on PCIe is realized by adopting an FPGA, currently, the FPGA usually adopts Xilinx A7 series, the using effect is good, but the series is foreign technology and is a long-term monopoly process; in order to design a novel FPGA chip which can replace the foreign technology and avoid monopoly of the foreign FPGA when the normal use of the HDLC controller is not influenced, namely, the FPGA adopts the logo 2 of 28ns process of purple light simultaneous transmission, the technology of the foreign FPGA chip can be basically realized, and the normal use of the HDLC is not influenced; the FPGA comprises an HDLC protocol transmission unit, a data cache unit and a main control unit; the HDLC protocol transmission unit comprises an HDLC data sending module and an HDLC data receiving module; the HDLC controller comprises the following steps when in work:
(1) the HDLC control module interrupts signals to apply for the upper computer to correspond, wherein PCIe is connected with the upper computer and the HDLC controller and is used for converting the internal bus behavior into PCIe bus behavior;
(2) the FPGA is a conversion chip and converts a PCIe bus into a plurality of paths of mutually independent E1 communication.
Further supplementing the technical scheme, the working of the FPGA chip comprises the following steps: firstly, DMA access is realized through an HDLC protocol transmission unit, and then data can be received or taken out through a data cache unit; and then the data is converted into a plurality of paths of mutually independent communication through bit processing, and then time slot mapping is carried out, and finally serial ports send the data.
Further supplementing the technical scheme, in the step (2), the FPGA can convert the PCIe bus into 4 paths of mutually independent E1 communications.
The technical solutions described above only represent the preferred technical solutions of the present invention, and some possible modifications to some parts of the technical solutions by those skilled in the art all represent the principles of the present invention, and fall within the protection scope of the present invention.
Claims (5)
1. An FPGA chip of an HDLC controller based on PCIe is characterized in that the HDLC controller is realized by adopting an FPGA, and the FPGA comprises an HDLC protocol transmission unit, a data cache unit and a main control unit; the HDLC protocol transmission unit comprises an HDLC data sending module and an HDLC data receiving module; the HDLC controller comprises the following steps when in work:
(1) the HDLC control module interrupts signals to apply for the upper computer to correspond, wherein PCIe is connected with the upper computer and the HDLC controller and is used for converting the internal bus behavior into PCIe bus behavior;
(2) the FPGA is a conversion chip and converts a PCIe bus into a plurality of paths of mutually independent E1 communication.
2. The FPGA chip of claim 1 wherein the FPGA chip operation comprises the steps of: firstly, DMA access is realized through an HDLC protocol transmission unit, and then data can be received or taken out through a data cache unit; and then the data is converted into a plurality of paths of mutually independent communication through bit processing, and then time slot mapping is carried out, and finally serial ports send the data.
3. The FPGA chip of an HDLC controller based on PCIe of claim 2, wherein in step (2), the FPGA can convert the PCIe bus into 4 independent E1 communications.
4. The FPGA chip of an HDLC controller based on PCIe of claim 1, wherein the FPGA adopts a logo 2 of 28ns procedure of purple light transmission.
5. The FPGA chip of a PCIe-based HDLC controller of claim 1, wherein the FPGA is in the A7 series of Xilinx.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011519806.3A CN112559428A (en) | 2020-12-21 | 2020-12-21 | HDLC controller's FPGA chip based on PCIe |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011519806.3A CN112559428A (en) | 2020-12-21 | 2020-12-21 | HDLC controller's FPGA chip based on PCIe |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112559428A true CN112559428A (en) | 2021-03-26 |
Family
ID=75031638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011519806.3A Pending CN112559428A (en) | 2020-12-21 | 2020-12-21 | HDLC controller's FPGA chip based on PCIe |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112559428A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1258146A (en) * | 1998-07-24 | 2000-06-28 | 休斯电子公司 | Time-division multiplex buffering |
| CN1467970A (en) * | 2002-07-08 | 2004-01-14 | 华为技术有限公司 | Method for implementing multiple protocol processing in communication central processor |
| CN1984148A (en) * | 2006-05-15 | 2007-06-20 | 华为技术有限公司 | Device and method for controlling high-level data link |
| CN101051879A (en) * | 2007-04-06 | 2007-10-10 | 华为技术有限公司 | Method and device for multiplying and de-multiplying low speed service |
| CN102510351A (en) * | 2011-09-26 | 2012-06-20 | 迈普通信技术股份有限公司 | Method for receiving and transmitting data by adopting data communication bus |
| CN102611615A (en) * | 2012-02-16 | 2012-07-25 | 珠海市佳讯实业有限公司 | FPGA (Field Programmable Gate Array)-based integrated system |
| CN202503528U (en) * | 2012-03-28 | 2012-10-24 | 广东宜通世纪科技股份有限公司 | Signaling link access and identification device |
| CN105262659A (en) * | 2015-11-02 | 2016-01-20 | 日立永济电气设备（西安）有限公司 | HDLC protocol controller based on FPGA chip |
| CN105302753A (en) * | 2015-11-13 | 2016-02-03 | 中国电子科技集团公司第五十四研究所 | Multi-channel HDLC data processing device based on FPGA and FIFO chips |
| CN110224789A (en) * | 2019-06-10 | 2019-09-10 | 哈尔滨工业大学 | A kind of multi-mode hdlc controller based on FPGA |
| CN110932810A (en) * | 2019-11-28 | 2020-03-27 | 江苏久高电子科技有限公司 | Digital duplication method and digital duplication system based on FPGA |
-
2020
- 2020-12-21 CN CN202011519806.3A patent/CN112559428A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1258146A (en) * | 1998-07-24 | 2000-06-28 | 休斯电子公司 | Time-division multiplex buffering |
| CN1467970A (en) * | 2002-07-08 | 2004-01-14 | 华为技术有限公司 | Method for implementing multiple protocol processing in communication central processor |
| CN1984148A (en) * | 2006-05-15 | 2007-06-20 | 华为技术有限公司 | Device and method for controlling high-level data link |
| CN101051879A (en) * | 2007-04-06 | 2007-10-10 | 华为技术有限公司 | Method and device for multiplying and de-multiplying low speed service |
| CN102510351A (en) * | 2011-09-26 | 2012-06-20 | 迈普通信技术股份有限公司 | Method for receiving and transmitting data by adopting data communication bus |
| CN102611615A (en) * | 2012-02-16 | 2012-07-25 | 珠海市佳讯实业有限公司 | FPGA (Field Programmable Gate Array)-based integrated system |
| CN202503528U (en) * | 2012-03-28 | 2012-10-24 | 广东宜通世纪科技股份有限公司 | Signaling link access and identification device |
| CN105262659A (en) * | 2015-11-02 | 2016-01-20 | 日立永济电气设备（西安）有限公司 | HDLC protocol controller based on FPGA chip |
| CN105302753A (en) * | 2015-11-13 | 2016-02-03 | 中国电子科技集团公司第五十四研究所 | Multi-channel HDLC data processing device based on FPGA and FIFO chips |
| CN110224789A (en) * | 2019-06-10 | 2019-09-10 | 哈尔滨工业大学 | A kind of multi-mode hdlc controller based on FPGA |
| CN110932810A (en) * | 2019-11-28 | 2020-03-27 | 江苏久高电子科技有限公司 | Digital duplication method and digital duplication system based on FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 刘卓才等: "大容量SDH信令采集的FPGA实现", 《信息通信》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103905281A (en) | FC-AE-1553 bus node card capable of interchangeably achieving functions of network controller and network terminal | |
| CN103178872B (en) | Method and the device of USB system transfers distance is extended by Ethernet | |
| CN102088444A (en) | PROFIBUS DP and PROFIBUS PA protocol conversion gateway module | |
| CN106528486A (en) | Method for exchanging serial port data | |
| CN103972909A (en) | TSC (thyristor switched capacitor) system and RS485 communication method thereof based on FPGA (Field Programmable Gate Array) | |
| CN111131933B (en) | FC dual-redundancy switch configuration management device and configuration management method | |
| CN108039041A (en) | A kind of high speed 4G concentrators communication module, power information acquisition system and method | |
| CN202111737U (en) | Network management enhanced E1/ETH protocol converter | |
| CN112559428A (en) | HDLC controller's FPGA chip based on PCIe | |
| CN108156099A (en) | Srio switching system | |
| CN204231388U (en) | The gateway apparatus of a kind of CAN and ethernet communication | |
| CN207976991U (en) | A kind of high speed 4G concentrators communication module and power information acquisition system | |
| CN202617157U (en) | PCI express (PCIE) switched circuit | |
| CN102023959A (en) | Communication conversion bridge set based on USB-HID (universal serial bus-human input device) protocol | |
| CN212183548U (en) | IEC61850 protocol and Modbus protocol keysets | |
| CN203522744U (en) | Multi-service optical access apparatus | |
| CN110262989B (en) | Multifunctional communication converter and communication method | |
| CN112637197A (en) | Multi-channel multiplexing based on HDLC controller | |
| CN203933026U (en) | The TSC system of communicating by letter with RS485 based on FPGA | |
| CN214067776U (en) | Novel multipurpose communication conversion interface | |
| CN206863938U (en) | A kind of data communication machine with breakpoint transmission | |
| CN112187766A (en) | Modbus protocol conversion terminal configuration method and Modbus protocol conversion terminal | |
| CN109818941A (en) | Realize that 10GE interface equipment supports the system and method for 25GE interface | |
| CN203596924U (en) | Network adaptor used for mobile communication | |
| CN214253208U (en) | IP core of dual-redundancy serial port controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210326 |
|
| RJ01 | Rejection of invention patent application after publication |