CN112559120B - Customized PCIE bus IO virtualization supporting method - Google Patents
Customized PCIE bus IO virtualization supporting method Download PDFInfo
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- CN112559120B CN112559120B CN201910918611.7A CN201910918611A CN112559120B CN 112559120 B CN112559120 B CN 112559120B CN 201910918611 A CN201910918611 A CN 201910918611A CN 112559120 B CN112559120 B CN 112559120B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a customized PCIE bus IO virtualization supporting method.A virtual machine kernel initiates a PCIE bus scanning action and initiates read-write operation of a PCIE IO address space; the processor automatically enters a TLB Miss exception handling entry; executing a TLB Miss exception handling code in a TLB Miss exception handling process of the processor, obtaining transmitted information by upper-layer virtual machine management software, and judging whether to perform PCIE IO address space reading operation or writing operation according to instruction coding information; after the upper-layer virtual machine management software reads PCIE IO address space for simulation execution, the read result is set into a register in a register field stack of the virtual machine, and the read result is returned to the virtual processor running field of the virtual machine; after writing PCIE IO address space simulation execution, the upper layer virtual machine management software sets the upper layer virtual machine management software to a correct state and prepares to return to a virtual processor operation site. The invention realizes the IO virtualization of the PCIE bus on the processor which does not support the hardware virtualization expansion, and supports the virtualization of pure simulation PCIE equipment and the direct binding of the virtual machine to the PCIE equipment.
Description
Technical Field
The invention relates to a customized PCIE bus IO virtualization supporting method, and belongs to the technical field of processor platform operating system kernels.
Background
IO virtualization (Input/output virtualization) is an important component in system virtualization technology. In virtual machine platforms such as commercial VMWare and Virtualbox and KVM and Xen virtual machine platforms with open sources, virtual external devices such as a virtual display card, a virtual disk and a virtual network card all depend on the IO virtualization technology. In KVM and Xen virtual machine platforms with an open source in a Linux system, a VirtiO-based semi-virtualization technology is provided, a simulated PCIE bus DMA can be not relied on in an IO virtualization data transmission protocol, but scanning, discovery, configuration and the like of VirtiO equipment also need the IO virtualization technology relying on the PCIE bus.
In order to provide a higher-performance IO access for a virtual machine, a Single-root I/O virtualization (SR-IOV) specification is introduced by a pcie (peripheral component interconnect express) organization, and a mainstream high-performance network card dispute supports the SR-IOV specification. The network card supports the SR-IOV technology, and simultaneously supports a Physical Function (PF) and a plurality of Virtual Functions (VFs), each VF can be regarded as an independent small-sized network card and can be independently distributed to a Virtual machine for use, so that the Virtual machine can obtain the network communication capacity close to the performance of the Physical network card. The virtual machine platform PCIE bus virtualization technology is to support binding of such a VF to a virtual machine, so that a virtual machine kernel can discover, configure, and use the VF, and it is ensured that the virtual machine is not exited in a use process, and no additional virtualization overhead is introduced.
The prior art implementations are mainly directed to commercial processors supporting virtualized hardware extensions, such as Intel, AMD, Power processors, which have full MMU virtualization extensions and IOMMU virtualization extensions for IO virtualization, and additionally have hardware virtualized interrupt controllers for interrupts. Because the domestic processor does not support hardware virtualization extension, the support of the PCIE bus IO virtualization technology cannot be realized.
Disclosure of Invention
The invention aims to provide a customized PCIE bus IO virtualization supporting method which realizes the PCIE bus IO virtualization on a processor which does not support hardware virtualization expansion and supports pure simulation PCIE equipment virtualization.
In order to achieve the purpose, the invention adopts the technical scheme that: a customized PCIE bus IO virtualization supporting method comprises the following steps:
s10: the virtual machine kernel initiates a PCIE bus scanning action;
s11: when the virtual machine scans the PCIE bus, the virtual machine kernel can initiate read-write operation of the PCIE IO address space; the first read and written PCIE IO address space triggers TLB Miss exception of the processor, and the processor automatically enters a TLB Miss exception handling entry;
s12: after entering a processor TLB Miss exception handling entry, executing a TLB Miss exception handling code in a processor TLB Miss exception handling process, wherein the code firstly judges that the current processor runs in a virtual machine mode and when the address accessed in the S11 step is a PCIE IO address space, the TLB Miss exception handling code is not filled in the subsequent steps, and the running state of the processor is switched from the running state of the virtual machine to the running state of a host machine;
s13: after the running state of the virtual processor exits and is switched to the state of the host processor, the virtual processor enters the kernel of the host operating system, and the kernel of the host operating system can know that the virtual processor has read-write access to the PCIE IO address space by inquiring the reason for exiting the virtual processor;
s14: the kernel of the host operating system analyzes the target address and the corresponding instruction code read and written in the step S11, and transmits the target address and the corresponding instruction code to the upper-layer virtual machine management software;
s15: the upper layer virtual machine management software obtains the information transmitted in the step S14, and judges whether to perform PCIE IO address space reading operation or writing operation according to the instruction coding information; if the command is encoded as a read command operation, proceed to S16; if the command is encoded as a write command operation, proceed to S17;
s16: after the upper layer virtual machine management software reads PCIE IO address space simulation execution, the upper layer virtual machine management software needs to set a read result into a corresponding register in a virtual machine register field stack and return to a virtual processor operation field of the virtual machine;
s17: after writing PCIE IO address space simulation execution by the upper layer virtual machine management software, setting the simulated PCIE IO address space to a corresponding correct state, and preparing to return to a virtual processor operation site of the virtual machine;
s18: because the TLB is not filled in the S12, the TLB Miss exception is caused by each PCIE IO address space read-write operation initiated by the virtual machine kernel in S10, and thus S11 is entered, and processing is performed in a cyclic reciprocating manner, thereby implementing read-write simulation of the PCIE IO space.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages:
1) the customized PCIE bus IO virtualization supporting method utilizes the semi-virtualization, realizes the PCIE bus IO virtualization support through the customized interface, greatly reduces the design difficulty and the cost of a processor architecture, realizes the perfect PCIE bus IO virtualization support under the condition of not increasing any hardware interface, and supports the virtualization of pure simulation PCIE equipment and the direct binding of a virtual machine with the PCIE equipment.
Drawings
Fig. 1 is a schematic flow diagram of a customized PCIE bus IO virtualization support method according to the present invention.
Detailed Description
As shown in fig. 1, a customized PCIE bus IO virtualization supporting method includes the following steps, S10: the virtual machine kernel initiates a PCIE bus scan action.
S11: when a virtual machine scans a PCIE bus, a virtual machine kernel can initiate read-write operation of a PCIE IO address space; the first read and written PCIE IO address space triggers TLB Miss exception of the processor, and the processor automatically enters a TLB Miss exception handling entry; the PCIE bus is a protocol specification, and a PCIE IO address space needs to be accessed when the bus is scanned and the PCIE device is operated according to the protocol specification.
S12: after entering a processor TLB Miss exception handling entry, executing a TLB Miss exception handling code in a processor TLB Miss exception handling process, firstly judging that the current processor runs in a virtual machine mode and the address accessed in the S11 is a PCIE IO address space, not filling the TLB in the subsequent steps of the TLB Miss exception handling code, and switching the running state of the processor from the running state of the virtual machine to the running state of a host machine.
S13: after the running state of the processor is switched to the running state of the host machine from the running state of the virtual machine, the processor enters the kernel of the host machine operating system, and the kernel of the host machine operating system can know that the virtual machine kernel has read-write access of the PCIE IO address space by inquiring the reason for the exit of the virtual processor.
S14: and the kernel of the host operating system analyzes the target address and the corresponding instruction code read and written in the step S11, and transmits the target address and the corresponding instruction code to the upper-layer virtual machine management software.
S15: the upper layer virtual machine management software obtains the information transmitted in the S14, and judges whether to perform PCIE IO address space reading operation or writing operation according to the instruction coding information; if the command is encoded as a read command operation, proceed to S16; if the command is encoded as a write command operation, the process proceeds to S17.
S16: after the upper layer virtual machine management software reads the PCIE IO address space for simulation execution, the upper layer virtual machine management software needs to set the read result into a corresponding register in the register field stack of the virtual machine and return to the virtual processor operation field of the virtual machine. The specific method is to return to the next instruction of the virtual processor read PCIE IO address space instruction in the step S11, that is, skip the PCIE IO space read instruction that triggers the TLB Miss exception of the processor in S11, and make the corresponding target register indicated in the read instruction code have the correct numerical value.
S17: after writing PCIE IO address space simulation execution by the upper layer virtual machine management software, setting the simulated PCIE IO address space to a corresponding correct state, and preparing to return to a virtual processor running field of the virtual machine. The specific method is to return to the next instruction of writing the PCIE IO address space instruction by the virtual processor in the step S11, that is, skip the PCIE IO space write instruction triggering the TLB Miss exception of the processor in S11.
S18: because the TLB is not loaded in S12, the TLB Miss exception is caused by each PCIE IO address space read-write operation initiated by the virtual machine kernel in S10, so that S11 is entered, and processing is performed in a cyclic and reciprocating manner, thereby implementing read-write simulation of the PCIE IO space.
When the customized PCIE bus IO virtualization supporting method is adopted, the PCIE bus IO virtualization support is realized through the customized interface by using the semi-virtualization, the design difficulty and the cost of the processor architecture are greatly reduced, the perfect PCIE bus IO virtualization support is realized under the condition that no hardware interface is added, and the pure simulation PCIE equipment virtualization and the direct binding of the virtual machine with the PCIE equipment are supported.
To facilitate a better understanding of the invention, the terms used herein will be briefly explained as follows:
virtual processor (VCPU): the virtual CPU in the virtual machine platform runs on the physical CPU, and the virtual machine manager is responsible for maintaining the time-sharing scheduling running of different VCPUs on the physical CPU.
TLB-Miss: modern processors support the replacement of virtual addresses and physical addresses, and when a virtual address read-write request is initiated, the processor needs to query the TLB to obtain the replacement relationship between the virtual address and the physical address, and determine the physical address to be accessed. If the replacement relationship is not looked up in the TLB, a TLB-Miss occurs.
Semi-virtualization: the kernel needs to be adapted to the virtual machine, and can recognize the running mode and the virtual machine mode or the physical machine mode, and select a proper mode to execute the matched code. A software interface exists between the kernel and the virtual machine manager.
The Translation Lookaside Buffer (TLB) is used for interaction between a virtual address and a real address, provides a cache region for searching the real address, and can effectively reduce the time consumed by searching the physical address.
The runtime generic refers to the running state of the processor, including the processor's current general purpose register state and certain privileged states.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered in the protection scope of the present invention.
Claims (1)
1. A customized PCIE bus IO virtualization supporting method is characterized in that: the method comprises the following steps:
s10: the virtual machine kernel initiates a PCIE bus scanning action;
s11: when the virtual machine scans the PCIE bus, the virtual machine kernel can initiate read-write operation of the PCIE IO address space; the first read and written PCIE IO address space triggers TLB Miss exception of the processor, and the processor automatically enters a TLB Miss exception handling entry;
s12: after entering a processor TLB Miss exception handling entry, executing a TLB Miss exception handling code in a processor TLB Miss exception handling process, wherein the code firstly judges that the current processor runs in a virtual machine mode and when the address accessed in the S11 step is a PCIE IO address space, the TLB Miss exception handling code is not filled in the subsequent steps, and the running state of the processor is switched from the running state of the virtual machine to the running state of a host machine;
s13: after the running state of the processor is switched from the running state of the virtual machine to the running state of the host machine, the running state of the processor enters the kernel of the host machine operating system, and the kernel of the host machine operating system can know that the virtual machine kernel has read-write access of a PCIE IO address space by inquiring the reason for exiting the virtual processor;
s14: the host operating system kernel analyzes the target address and the corresponding instruction code read and written in the step S11, and transmits the target address and the corresponding instruction code to upper-layer virtual machine management software;
s15: the upper layer virtual machine management software obtains the information transmitted in the S14, and judges whether to perform PCIE IO address space reading operation or writing operation according to the instruction coding information; if the command is encoded as a read command operation, go to S16; if the command is encoded as a write command operation, proceed to S17;
s16: after the upper layer virtual machine management software reads PCIE IO address space simulation execution, the upper layer virtual machine management software needs to set a read result into a corresponding register in a virtual machine register field stack and return to a virtual processor operation field of the virtual machine;
s17: after writing PCIE IO address space simulation execution by upper layer virtual machine management software, setting the simulated PCIE IO address space to a corresponding correct state, and preparing to return to a virtual processor operation site of a virtual machine;
s18: because the TLB is not filled in the S12, the TLB Miss exception is caused by each PCIE IO address space read-write operation initiated by the virtual machine kernel in S10, and thus S11 is entered, and processing is performed in a cyclic reciprocating manner, thereby implementing read-write simulation of the PCIE IO space.
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| US20190258503A1 (en) * | 2017-04-07 | 2019-08-22 | NEC Laboratories Europe GmbH | Method for operating virtual machines on a virtualization platform and corresponding virtualization platform |
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| US20190258503A1 (en) * | 2017-04-07 | 2019-08-22 | NEC Laboratories Europe GmbH | Method for operating virtual machines on a virtualization platform and corresponding virtualization platform |
| CN109522087A (en) * | 2018-09-13 | 2019-03-26 | 上海交通大学 | Processor-based Imaginary Mechanism construction method and system |
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