CN112542998B - Digital down-conversion method and system - Google Patents
Digital down-conversion method and system Download PDFInfo
- Publication number
- CN112542998B CN112542998B CN202011423661.7A CN202011423661A CN112542998B CN 112542998 B CN112542998 B CN 112542998B CN 202011423661 A CN202011423661 A CN 202011423661A CN 112542998 B CN112542998 B CN 112542998B
- Authority
- CN
- China
- Prior art keywords
- parallel
- data
- frequency offset
- parallel channel
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004364 calculation method Methods 0.000 claims abstract description 46
- 238000009825 accumulation Methods 0.000 claims abstract description 21
- 238000005070 sampling Methods 0.000 claims abstract description 18
- 230000000694 effects Effects 0.000 claims description 4
- 238000012986 modification Methods 0.000 claims description 2
- 230000004048 modification Effects 0.000 claims description 2
- 238000004891 communication Methods 0.000 description 9
- 101100021996 Arabidopsis thaliana CYP97C1 gene Proteins 0.000 description 4
- 108700041286 delta Proteins 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006978 adaptation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention provides a digital down-conversion method and a system, wherein the method comprises the following steps: before refreshing the prompting signal with the parameters changed, acquiring the intermediate frequency and the sampling rate, and calculating a frequency offset compensation value and the initial phases of all parallel channels according to a parallel processing mode; when the prompting signal with the parameters changed is refreshed, carrying out phase accumulation calculation on the frequency offset compensation value and the initial phase of each parallel channel to obtain a phase accumulated value; after serial-parallel conversion is carried out on input data, carrying out coordinate rotation digital calculation on the input data of each parallel channel and a corresponding phase accumulated value to obtain coarse rotation data; according to the coarse rotation data of each parallel channel, table lookup is carried out to obtain each output data; and carrying out parallel-serial conversion on the output data and outputting the output data. The scheme has the advantages of fewer storage resources, lower time delay and higher compensation precision.
Description
Technical Field
The present invention relates to the field of wireless communication technologies, and in particular, to a digital down-conversion method and system.
Background
In wireless communication systems, it is often desirable to frequency offset compensate the received signal, e.g., with a signal sampling rate f s The frequency offset to be compensated is f 0 The received signal is X (K) (k=0, 1..n), the frequency offset compensated signal is y (K) (X, y is complex), then:
y (k) =x (k) (cos (f 0/fs 2 pi (k-1)) +1i sin (f 0/fs 2 pi (k-1))), wherein k=1, 2,3 … n;
the equivalence is considered as: y (k) =x (k) × (cos (delta) +1i×sin (delta)), where k=1, … n, delta is between 0-2×pi.
When eight parallel lines are adopted, the mth line (m=0, 1,2 … 7) at the k moment: y_m (k) =x (8×k+m) (cos (8×f0/fs×2×pi (k-1) +m×f0/fs) +1i×sin (f8×0/fs×2×pi (k-1)) +mf0/fs. For each way in parallel, it can be seen that:
y (k) =x (k) × (cos (delta) +1i×sin (delta)), where k=1, … n, delta is between 0-2×pi.
In a broadband wireless system, when the bandwidth is large, the signal bandwidth of hundreds of megabytes can be often reached, and the corresponding requirement on the sampling rate is also met, namely, the input data sampling rate can reach hundreds of megabytes or even more than 1G, which is a very high requirement on the processing speed of hardware. The existing processing architecture has two types of serial and parallel, and the parallel can reduce the requirement on the hardware processing speed. In addition, the existing down-conversion scheme comprises a table lookup method, a coordinate rotation digital calculation method, a secondary table lookup method and the like.
However, in order to realize high-precision frequency offset compensation, the table lookup method needs to store a relatively large table, and occupies more resources; the coordinate rotation digital calculation method increases time delay, requires larger iteration times for realizing higher precision, and increases power consumption; a compromise scheme in the secondary table lookup method can balance the storage space and the power consumption well, but complex multiplication is needed to be performed once more after the secondary table lookup, certain resources are consumed, the performance is also influenced by the size of the secondary table lookup, and high precision is difficult to achieve. Therefore, a digital down-conversion method with less memory resources, low latency, and higher compensation accuracy is needed.
Disclosure of Invention
The invention aims to provide a digital down-conversion method and a digital down-conversion system, which have the advantages of less required storage resources, lower time delay and higher compensation precision.
The technical scheme provided by the invention is as follows:
the invention provides a digital down-conversion method, which comprises the following steps:
before refreshing the prompting signal with the parameters changed, acquiring the intermediate frequency and the sampling rate, and calculating a frequency offset compensation value and the initial phases of all parallel channels according to a parallel processing mode;
when the prompting signal with the parameters changed is refreshed, carrying out phase accumulation calculation on the frequency offset compensation value and the initial phase of each parallel channel to obtain a phase accumulated value;
after serial-parallel conversion is carried out on input data, carrying out coordinate rotation digital calculation on the input data of each parallel channel and a corresponding phase accumulated value to obtain coarse rotation data;
according to the coarse rotation data of each parallel channel, table lookup is carried out to obtain each output data;
and carrying out parallel-serial conversion on the output data and outputting the output data.
According to the scheme, before refreshing the parameter-changed prompt signals, the frequency offset compensation value and the initial phase of each parallel channel are calculated according to the intermediate frequency and the sampling rate in a parallel processing mode, the frequency offset compensation value and the initial phase of each parallel channel can be subjected to phase accumulation calculation when the parameter-changed prompt signals are refreshed, the phase accumulation value is obtained, the input data of each parallel channel after serial-parallel conversion and the corresponding phase accumulation value are subjected to coordinate rotation digital calculation, coarse rotation data can be obtained, then table lookup is carried out according to the coarse rotation data of each parallel channel, each output data can be obtained, and final output data can be obtained after the output data are subjected to parallel-serial conversion; the scheme adopts a method combining parallel processing and a coordinate rotation digital computing method to realize digital down conversion of the wide bandwidth wireless communication system, so that smaller storage resources and less multipliers can be used to realize higher compensation precision, and the parallel processing reduces the requirement on hardware processing speed; meanwhile, the input data of each parallel channel after serial-parallel conversion and the corresponding phase accumulated value are subjected to coordinate rotation digital calculation, so that the iteration times of the coordinate rotation digital calculation are not required to be too much, and the time delay and the power consumption can be reduced.
Further, the coordinate rotation digital calculation is performed on the input data of each parallel channel and the corresponding phase accumulated value to obtain coarse rotation data, which specifically includes:
carrying out iteration for preset times on the input data of each parallel channel and the corresponding phase accumulated value to obtain a rotation angle and a residual angle;
and obtaining the data after rotation according to the rotation angle.
Further, the performing table lookup according to the coarse rotation data of each parallel channel to obtain each output data specifically includes:
performing table lookup on the residual angle to obtain a table lookup result;
and obtaining the output data according to the table look-up result and the rotated data.
Further, the calculating the frequency offset compensation value according to the parallel processing mode and the initial phase of each parallel channel specifically includes:
and calculating a frequency offset compensation value and an initial phase of each parallel channel according to the eight-path parallel processing mode.
Further, after the frequency offset compensation value is calculated according to the parallel processing mode and the initial phases of the parallel channels, before the parameter-modified prompt signal is refreshed, the method further comprises:
the frequency offset compensation value and the corresponding initial phase of each parallel channel are configured through a register, and the frequency offset compensation value and the corresponding initial phase configured by the register take effect when a prompt signal for parameter change is refreshed.
In addition, the invention also provides a digital down-conversion system, which comprises:
the register is used for configuring the frequency offset compensation value calculated according to the parallel processing mode and the initial phase of each parallel channel according to the intermediate frequency and the sampling rate before refreshing the prompting signal with the parameter changed;
the serial-to-parallel converter is used for carrying out serial-to-parallel conversion on input data;
the down converters are connected with the register and the serial-parallel converter and are used for performing down conversion processing on each parallel channel when the prompting signal for parameter change is refreshed to obtain each output data;
the parallel-serial converter is used for carrying out parallel-serial conversion on the output data and outputting the output data;
wherein, down converter all includes:
the phase accumulator is used for carrying out phase accumulation calculation on the frequency offset compensation value and the initial phase of each parallel channel when the prompt signal with the parameter changed is refreshed, so as to obtain a phase accumulated value;
the CORDIC calculator is used for carrying out coordinate rotation digital calculation on the input data of each parallel channel and the corresponding phase accumulated value to obtain coarse rotation data;
and the fine table look-up calculator is used for looking up a table according to the coarse rotation data of each parallel channel to obtain each output data.
According to the scheme, before refreshing the parameter-changed prompt signals, a frequency offset compensation value and the initial phases of all parallel channels are calculated according to an intermediate frequency and a sampling rate in a parallel processing mode, the frequency offset compensation value and the initial phases of all parallel channels are configured into a register, when the parameter-changed prompt signals are refreshed, the frequency offset compensation value and the initial phases of all parallel channels are subjected to phase accumulation calculation through a phase accumulator to obtain a phase accumulation value, the input data of all parallel channels after serial-parallel conversion and the corresponding phase accumulation value are subjected to coordinate rotation digital calculation through a CORDI calculator, coarse rotation data can be obtained, the coarse rotation data of all parallel channels can be subjected to table lookup through a fine table lookup calculator, all output data can be obtained, and final output data can be obtained after the output data are subjected to parallel-serial conversion; the scheme adopts a method combining parallel processing and a coordinate rotation digital computing method to realize digital down conversion of the wide bandwidth wireless communication system, so that smaller storage resources and less multipliers can be used to realize higher compensation precision, and the parallel processing reduces the requirement on hardware processing speed; meanwhile, the input data of each parallel channel after serial-parallel conversion and the corresponding phase accumulated value are subjected to coordinate rotation digital calculation, so that the iteration times of the coordinate rotation digital calculation are not required to be too much, and the time delay and the power consumption can be reduced.
Further, the CORDCI calculator iterates the input data and the corresponding phase accumulated values of each parallel channel for a preset number of times to obtain a rotation angle and a residual angle, and obtains rotated data according to the rotation angle.
Further, the fine table lookup calculator performs table lookup on the residual angle to obtain a table lookup result, and obtains the output data according to the table lookup result and the rotated data.
Further, the register configures the frequency offset compensation value calculated according to the eight-path parallel processing mode and the initial phase of each parallel channel.
Further, the frequency offset compensation value and the corresponding initial phase of the register configuration are effective when the prompt signal of parameter change is refreshed.
According to the digital down-conversion method and system provided by the invention, the digital down-conversion of the wide bandwidth wireless communication system is realized by adopting a method combining parallel processing and coordinate rotation digital computing methods, so that a relatively small storage resource and a relatively small multiplier can be used for realizing relatively high compensation precision, and the parallel processing reduces the requirement on hardware processing speed; meanwhile, the input data of each parallel channel after serial-parallel conversion and the corresponding phase accumulated value are subjected to coordinate rotation digital calculation, so that the iteration times of the coordinate rotation digital calculation are not required to be too much, and the time delay and the power consumption can be reduced.
Drawings
The above features, technical features, advantages and implementation modes of the present invention will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and understandable manner.
FIG. 1 is a schematic overall flow diagram of an embodiment of the present invention;
FIG. 2 is a schematic overall structure of an embodiment of the present invention;
FIG. 3 is a schematic diagram of a down converter according to an embodiment of the present invention;
FIG. 4 is a block diagram of an iteration of a CORDIC calculator of an embodiment of the present invention;
FIG. 5 is a block diagram of a fine table lookup calculator according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For the sake of simplicity of the drawing, the parts relevant to the present invention are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
Example 1
In one embodiment of the present invention, as shown in fig. 1, the present invention provides a digital down-conversion method, including the steps of:
s1, before refreshing a prompt signal (Refresh signal) with parameters changed, acquiring an intermediate frequency and a sampling rate, and calculating a frequency offset compensation value and an initial phase of each parallel channel according to a parallel processing mode.
Preferably, in this embodiment, the frequency offset compensation value is calculated according to an eight-path parallel processing mode, and the initial phases of the parallel channels, and in other embodiments, other multi-path parallel processing modes may also be selected.
Specifically, a flag of the Refresh signal to be generated is obtained, the intermediate frequency f0 and the sampling rate fs are configured in advance, and the frequency offset compensation value fac, the initial phase phi_0 and the initial phase phi (m) of each channel are converted in an eight-path parallel processing mode, wherein m=1, 2,3,4,5,6,7 and 8.
In addition, in a wireless communication system, frequency offset compensation is often required for a received signal, e.g., a signal sampling rate f s The frequency offset to be compensated is f 0 The received signal is X (K) (k=0, 1..n), the frequency offset compensated signal is y (K) (X, y is complex), then:
y (k) =x (k) (cos (f 0/fs 2 pi (k-1)) +1i sin (f 0/fs 2 pi (k-1))), wherein k=1, 2,3 … n;
the equivalence is considered as: y (k) =x (k) × (cos (delta) +1i×sin (delta)), where k=1, … n, delta is between 0-2×pi.
When eight parallel lines are adopted, the mth line (m=0, 1,2 … 7) at the k moment: y_m (k) =x (8×k+m) (cos (8×f0/fs×2×pi (k-1) +m×f0/fs) +1i×sin (f8×0/fs×2×pi (k-1)) +mf0/fs. For each way in parallel, it can be seen that:
y (k) =x (k) × (cos (delta) +1i×sin (delta)), where k=1, … n, delta is between 0-2×pi.
The delta angle rotation can be directly carried out on the data through the CORDIC, after the CORDIC passes through limited iteration, the rotation angle is delta1, the residual angle is delta2, and
delta＝delta1+delta2。
let the rotated data be x2=x (cos (delta 1) +1i sin (delta 1)); then we need the required frequency offset compensation data y=x2 (cos (delta 2) +1i sin (delta 2)); since the delta2 angle is small, it can be obtained by looking up the table.
For any angle a, 0.ltoreq.a <2 pi, a=b+m pi/2 can be written, where 0= < b < pi/2, m is a number from among 0 to 3. Then
cos(a)＝cos(b+m*pi/2)。
For m=0, cos (a) =cos (b); m=1, cos (a) = -sin (b); similarly, cos (a) can always be expressed as the sine and cosine value of b, and the result of the sign of the sine and cosine value. Similarly, sin (a) can be expressed as such, so that we can calculate and convert the angle sine and cosine values in the range of 0-2 pi into the result of calculating the range of 0-pi/2, namely, can convert the rotation of any angle of 0-2 pi into the rotation within 0-pi/2, and then obtain the sine and cosine values through a conversion formula.
S2, when the prompting signals with the parameters changed are refreshed, carrying out phase accumulation calculation on the frequency offset compensation value and the initial phase of each parallel channel to obtain a phase accumulated value.
Preferably, the frequency offset compensation value and the corresponding initial phase of each parallel channel are configured through the register, and the frequency offset compensation value and the corresponding initial phase configured by the register take effect when the prompt signal for parameter change is refreshed.
Specifically, for each initial phase phi (m), m=1, 2,3,4,5,6,7,8, and fac input to the parallel channel, the phase accumulator outputs a phase accumulation delta and index Findex each time the phase accumulator accumulates.
S3, after serial-parallel conversion is carried out on the input data, coordinate rotation digital calculation is carried out on the input data of each parallel channel and the corresponding phase accumulated value, and coarse rotation data are obtained.
Preferably, the coordinate rotation digital calculation is performed on the input data of each parallel channel and the corresponding phase accumulated value to obtain coarse rotation data, which specifically includes:
s31, iterating the input data of each parallel channel and the corresponding phase accumulated value for preset times to obtain a rotation angle and a residual angle.
S32, acquiring data after rotation according to the rotation angle.
As shown in fig. 4, the phase accumulated value delta, the input data of each parallel channel are input to the CORDIC calculator to perform coordinate rotation digital calculation, z (1) =delta, x1 (1) =real (x), x2 (1) =imag (x), antantext is a stored atan table, the iteration number is 10, CORDIC calculation is performed, and the rotated data x and the residual angle index2 are output.
Specifically, if z (i) = 0, then x1 (i+1) = x1 (i), x2 (i+1) = x2 (i), the iteration is skipped, otherwise d=sign (z (i)),
x1(i+1)＝x1(i)-d*(x2(i)>>i-1)；
x2(i+1)＝x2(i)+d*(x1(i)>>i-1)；
z(i+1)＝z(i)-d*atantext(i)。
when the iteration is performed i times, updating calibrated rotated data x=x1 (i+1) +1i×2 (i+1) after the iteration is completed; index 2=z (i+1).
S4, looking up a table according to the coarse rotation data of each parallel channel to obtain each output data.
Preferably, the table look-up is performed according to the coarse rotation data of each parallel channel to obtain each output data, which specifically includes:
s41, carrying out table lookup on the residual angle to obtain a table lookup result.
S42, obtaining output data according to the table look-up result and the rotated data.
As shown in fig. 5, the data x and the residual index2 outputted from the CORDIC are inputted to the fine table calculator.
If index2<0, findex2=1, then index 2=abs (index 2), index 1=index 2 right-shifted 17; look-up table (i.e., look-up table is input to LUT1 in fig. 4, LUT1 represents a locally stored waveform table) is performed using index2 to obtain look-up table result x1; calibrating the table look-up result x1, and performing complex multiplication on the table look-up result x1 and the rotated data x to obtain calibrated x; output data y is obtained from Findex and calibrated x.
S5, carrying out parallel-serial conversion on the output data and outputting the output data.
According to the scheme, before refreshing the parameter-changed prompt signals, the frequency offset compensation value and the initial phase of each parallel channel are calculated according to the intermediate frequency and the sampling rate in a parallel processing mode, the frequency offset compensation value and the initial phase of each parallel channel can be subjected to phase accumulation calculation when the parameter-changed prompt signals are refreshed, the phase accumulation value is obtained, the input data of each parallel channel after serial-parallel conversion and the corresponding phase accumulation value are subjected to coordinate rotation digital calculation, coarse rotation data can be obtained, then table lookup is carried out according to the coarse rotation data of each parallel channel, each output data can be obtained, and final output data can be obtained after the output data are subjected to parallel-serial conversion; the scheme adopts a method combining parallel processing and a coordinate rotation digital computing method to realize digital down conversion of the wide bandwidth wireless communication system, so that smaller storage resources and less multipliers can be used to realize higher compensation precision, and the parallel processing reduces the requirement on hardware processing speed; meanwhile, the input data of each parallel channel after serial-parallel conversion and the corresponding phase accumulated value are subjected to coordinate rotation digital calculation, so that the iteration times of the coordinate rotation digital calculation are not required to be too much, and the time delay and the power consumption can be reduced.
Example 2
In one embodiment of the present invention, as shown in fig. 2 to 5, the present invention further provides a digital down-conversion system, which includes a register, a serial-to-parallel converter, a down-converter, and a parallel-to-serial converter.
The register is used for configuring the frequency offset compensation value calculated according to the parallel processing mode and the initial phase of each parallel channel according to the intermediate frequency and the sampling rate before refreshing the prompting signal with the parameter changed.
Preferably, in this embodiment, the register configures the frequency offset compensation value calculated according to the eight-path parallel processing mode, and the initial phase of each parallel channel, and in other embodiments, other multi-path parallel processing modes may also be selected.
Specifically, a flag of the Refresh signal to be generated is obtained, the intermediate frequency f0 and the sampling rate fs are configured in advance, the frequency offset compensation value fac, the initial phase phi_0 and the initial phase phi (m) of each channel are converted in an eight-path parallel processing mode, m=1, 2,3,4,5,6,7,8 are configured, and the frequency offset compensation value and the initial phase of each parallel channel are configured in a register.
In addition, in a wireless communication system, frequency offset compensation is often required for a received signal, e.g., a signal sampling rate f s The frequency offset to be compensated is f 0 The received signal is X (K) (k=0, 1..n), the frequency offset compensated signal is y (K) (X, y is complex), then:
y (k) =x (k) (cos (f 0/fs 2 pi (k-1)) +1i sin (f 0/fs 2 pi (k-1))), wherein k=1, 2,3 … n;
the equivalence is considered as: y (k) =x (k) × (cos (delta) +1i×sin (delta)), where k=1, … n, delta is between 0-2×pi.
When eight parallel lines are adopted, the mth line (m=0, 1,2 … 7) at the k moment: y_m (k) =x (8×k+m) (cos (8×f0/fs×2×pi (k-1) +m×f0/fs) +1i×sin (f8×0/fs×2×pi (k-1)) +mf0/fs. For each way in parallel, it can be seen that:
y (k) =x (k) × (cos (delta) +1i×sin (delta)), where k=1, … n, delta is between 0-2×pi.
The delta angle rotation can be directly carried out on the data through the CORDIC, after the CORDIC passes through limited iteration, the rotation angle is delta1, the residual angle is delta2, and
delta＝delta1+delta2。
let the rotated data be x2=x (cos (delta 1) +1i sin (delta 1)); then we need the required frequency offset compensation data y=x2 (cos (delta 2) +1i sin (delta 2)); since the delta2 angle is small, it can be obtained by looking up the table.
For any angle a, 0.ltoreq.a <2 pi, a=b+m pi/2 can be written, where 0= < b < pi/2, m is a number from among 0 to 3. Then
cos(a)＝cos(b+m*pi/2)。
For m=0, cos (a) =cos (b); m=1, cos (a) = -sin (b); similarly, cos (a) can always be expressed as the sine and cosine value of b, and the result of the sign of the sine and cosine value. Similarly, sin (a) can be expressed as such, so that we can calculate and convert the angle sine and cosine values in the range of 0-2 pi into the result of calculating the range of 0-pi/2, namely, can convert the rotation of any angle of 0-2 pi into the rotation within 0-pi/2, and then obtain the sine and cosine values through a conversion formula.
The serial-to-parallel converter is used for carrying out serial-to-parallel conversion on input data.
And the down converters are connected with the register and the serial-parallel converter and are used for performing down conversion processing on each parallel channel when the prompting signal for parameter change is refreshed, so as to obtain each output data.
The parallel-serial converter is used for carrying out parallel-serial conversion on the output data and outputting the output data;
the down-converters each include a phase accumulator, a CORDCI calculator, and a fine-look-up-table calculator, as shown in fig. 3.
And the phase accumulator is used for carrying out phase accumulation calculation on the frequency offset compensation value and the initial phase of each parallel channel when the prompt signal with the parameter changed is refreshed, so as to obtain a phase accumulated value.
Preferably, the frequency offset compensation value and the corresponding initial phase of the register configuration are validated when the prompting signal of parameter change is refreshed.
Specifically, for each initial phase phi (m), m=1, 2,3,4,5,6,7,8, and fac input to the parallel channel, the phase accumulator outputs a phase accumulation delta and index Findex each time the phase accumulator accumulates.
The CORDIC calculator is used for carrying out coordinate rotation digital calculation on the input data of each parallel channel and the corresponding phase accumulated value to obtain coarse rotation data.
Preferably, the CORDCI calculator iterates the input data of each parallel channel and the corresponding phase accumulated value for a preset number of times, obtains a rotation angle and a residual angle, and obtains rotated data according to the rotation angle.
As shown in fig. 4, the phase accumulated value delta, the input data of each parallel channel are input to the CORDIC calculator to perform coordinate rotation digital calculation, z (1) =delta, x1 (1) =real (x), x2 (1) =imag (x), antantext is a stored atan table, the iteration number is 10, CORDIC calculation is performed, and the rotated data x and the residual angle index2 are output.
Specifically, if z (i) = 0, then x1 (i+1) = x1 (i), x2 (i+1) = x2 (i), the iteration is skipped, otherwise d=sign (z (i)),
x1(i+1)＝x1(i)-d*(x2(i)>>i-1)；
x2(i+1)＝x2(i)+d*(x1(i)>>i-1)；
z(i+1)＝z(i)-d*atantext(i)。
when the iteration is performed i times, updating calibrated rotated data x=x1 (i+1) +1i×2 (i+1) after the iteration is completed; index 2=z (i+1).
The fine-look-up table calculator is used for looking up a table according to the coarse rotation data of each parallel channel to obtain each output data.
Preferably, the fine table-lookup calculator performs table-lookup on the residual angle to obtain a table-lookup result, and obtains output data according to the table-lookup result and the rotated data.
As shown in fig. 5, the data x and the residual index2 outputted from the CORDIC are inputted to the fine table calculator.
If index2<0, findex2=1, then index 2=abs (index 2), index 1=index 2 right-shifted 17; look-up table (i.e., look-up table is input to LUT1 in fig. 4, LUT1 represents a locally stored waveform table) is performed using index2 to obtain look-up table result x1; calibrating the table look-up result x1, and performing complex multiplication on the table look-up result x1 and the rotated data x to obtain calibrated x; output data y is obtained from Findex and calibrated x.
According to the scheme, before refreshing the parameter-changed prompt signals, a frequency offset compensation value and the initial phases of all parallel channels are calculated according to an intermediate frequency and a sampling rate in a parallel processing mode, the frequency offset compensation value and the initial phases of all parallel channels are configured into a register, when the parameter-changed prompt signals are refreshed, the frequency offset compensation value and the initial phases of all parallel channels are subjected to phase accumulation calculation through a phase accumulator to obtain a phase accumulation value, the input data of all parallel channels after serial-parallel conversion and the corresponding phase accumulation value are subjected to coordinate rotation digital calculation through a CORDI calculator, coarse rotation data can be obtained, the coarse rotation data of all parallel channels can be subjected to table lookup through a fine table lookup calculator, all output data can be obtained, and final output data can be obtained after the output data are subjected to parallel-serial conversion; the scheme adopts a method combining parallel processing and a coordinate rotation digital computing method to realize digital down conversion of the wide bandwidth wireless communication system, so that smaller storage resources and less multipliers can be used to realize higher compensation precision, and the parallel processing reduces the requirement on hardware processing speed; meanwhile, the input data of each parallel channel after serial-parallel conversion and the corresponding phase accumulated value are subjected to coordinate rotation digital calculation, so that the iteration times of the coordinate rotation digital calculation are not required to be too much, and the time delay and the power consumption can be reduced.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. A digital down conversion method, comprising the steps of:
before refreshing the prompting signal with the parameters changed, acquiring the intermediate frequency and the sampling rate, and calculating a frequency offset compensation value and the initial phases of all parallel channels according to a parallel processing mode;
when the prompting signal with the parameters changed is refreshed, carrying out phase accumulation calculation on the frequency offset compensation value and the initial phase of each parallel channel to obtain a phase accumulated value;
after serial-parallel conversion is carried out on input data, carrying out coordinate rotation digital calculation on the input data of each parallel channel and a corresponding phase accumulated value to obtain coarse rotation data;
according to the coarse rotation data of each parallel channel, table lookup is carried out to obtain each output data;
and carrying out parallel-serial conversion on the output data and outputting the output data.
2. The digital down-conversion method according to claim 1, wherein the performing coordinate rotation digital calculation on the input data of each parallel channel and the corresponding phase accumulated value to obtain coarse rotation data specifically includes:
carrying out iteration for preset times on the input data of each parallel channel and the corresponding phase accumulated value to obtain a rotation angle and a residual angle;
and obtaining the data after rotation according to the rotation angle.
3. The digital down conversion method according to claim 2, wherein the performing a table look-up according to the coarse rotation data of each parallel channel to obtain each output data comprises:
performing table lookup on the residual angle to obtain a table lookup result;
and obtaining the output data according to the table look-up result and the rotated data.
4. The digital down conversion method according to claim 1, wherein the calculating the frequency offset compensation value according to the parallel processing mode and the initial phase of each parallel channel specifically comprises:
and calculating a frequency offset compensation value and an initial phase of each parallel channel according to the eight-path parallel processing mode.
5. The digital down conversion method as set forth in claim 1, wherein the calculating the frequency offset compensation value according to the parallel processing mode, and after the initial phase of each parallel channel, before refreshing the prompting signal of parameter modification, further includes:
the frequency offset compensation value and the corresponding initial phase of each parallel channel are configured through a register, and the frequency offset compensation value and the corresponding initial phase configured by the register take effect when a prompt signal for parameter change is refreshed.
6. A digital down conversion system, comprising:
the register is used for configuring the frequency offset compensation value calculated according to the parallel processing mode and the initial phase of each parallel channel according to the intermediate frequency and the sampling rate before refreshing the prompting signal with the parameter changed;
the serial-to-parallel converter is used for carrying out serial-to-parallel conversion on input data;
the down converters are connected with the register and the serial-parallel converter and are used for performing down conversion processing on each parallel channel when the prompting signal for parameter change is refreshed to obtain each output data;
the parallel-serial converter is used for carrying out parallel-serial conversion on the output data and outputting the output data;
wherein, down converter all includes:
the phase accumulator is used for carrying out phase accumulation calculation on the frequency offset compensation value and the initial phase of each parallel channel when the prompt signal with the parameter changed is refreshed, so as to obtain a phase accumulated value;
the CORDIC calculator is used for carrying out coordinate rotation digital calculation on the input data of each parallel channel and the corresponding phase accumulated value to obtain coarse rotation data;
and the fine table look-up calculator is used for looking up a table according to the coarse rotation data of each parallel channel to obtain each output data.
7. A digital down conversion system as recited in claim 6, wherein: and the CORDIC calculator iterates the input data of each parallel channel and the corresponding phase accumulated value for preset times to obtain a rotation angle and a residual angle, and obtains rotated data according to the rotation angle.
8. A digital down conversion system as recited in claim 7, wherein: and the fine table-checking calculator performs table-checking on the residual angle to obtain a table-checking result, and obtains the output data according to the table-checking result and the rotated data.
9. A digital down conversion system as recited in claim 6, wherein: the register is configured with the frequency offset compensation value calculated according to the eight-path parallel processing mode and the initial phase of each parallel channel.
10. A digital down conversion system as recited in claim 6, wherein: the frequency offset compensation value and the corresponding initial phase configured by the register take effect when the prompting signal of parameter change is refreshed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011423661.7A CN112542998B (en) | 2020-12-08 | 2020-12-08 | Digital down-conversion method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011423661.7A CN112542998B (en) | 2020-12-08 | 2020-12-08 | Digital down-conversion method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112542998A CN112542998A (en) | 2021-03-23 |
| CN112542998B true CN112542998B (en) | 2024-03-19 |
Family
ID=75019406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011423661.7A Active CN112542998B (en) | 2020-12-08 | 2020-12-08 | Digital down-conversion method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112542998B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183853A (en) * | 2007-12-10 | 2008-05-21 | 华中科技大学 | Coordinate rotation numerical computation algorithm based digital low converter |
| CN102088431A (en) * | 2009-12-03 | 2011-06-08 | 中兴通讯股份有限公司 | Method and device for solving normalization value in OFDMA system |
-
2020
- 2020-12-08 CN CN202011423661.7A patent/CN112542998B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183853A (en) * | 2007-12-10 | 2008-05-21 | 华中科技大学 | Coordinate rotation numerical computation algorithm based digital low converter |
| CN102088431A (en) * | 2009-12-03 | 2011-06-08 | 中兴通讯股份有限公司 | Method and device for solving normalization value in OFDMA system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112542998A (en) | 2021-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8519875B2 (en) | System and method for background calibration of time interleaved analog to digital converters | |
| CN104779989B (en) | A kind of wideband array correcting filter coefficient calculation method | |
| US8115519B2 (en) | Phase accumulator generating reference phase for phase coherent direct digital synthesis outputs | |
| US8340225B2 (en) | System and method for performing blind IQ-imbalance estimation and compensation | |
| NO317449B1 (en) | Digital calibration of transceivers | |
| US8260836B2 (en) | Method and device for generating a filter coefficient in real time | |
| CN101807903B (en) | Self-adapting filter, filtration method and repeater | |
| CN112542998B (en) | Digital down-conversion method and system | |
| US10090854B1 (en) | Digital-to-analog converter and method for correcting gain mismatch between a first segment and a second segment of a digital-to-analog converter | |
| US5382913A (en) | Method and apparatus for generating two phase-coherent signals with arbitrary frequency ratio | |
| CN103916199A (en) | Device and method for time delay and phase adjustment of antenna signal | |
| US10274584B2 (en) | Apparatus and method for generating bidirectional chirp signal by using phase accumulation polynomial | |
| CN100458646C (en) | Trigonometric value determiner, determining method and telecommunicating apparatus therewith | |
| US8242829B1 (en) | Multichannel interpolator | |
| CN112565130B (en) | Low-delay parallel digital down-conversion method and system | |
| WO2014181075A1 (en) | Correction of quadrature phase and gain mismatch in receiver down-conversion using a dual cordic architecture | |
| CN108334157B (en) | Carrier signal generation method and device | |
| CN112600520A (en) | Parallel digital frequency conversion method, system and storage medium | |
| CN112600776B (en) | Frequency offset compensation method and device suitable for OFDM system | |
| CN112565129A (en) | Frequency offset compensation method and system | |
| US11558078B1 (en) | Lookup table (LUT) interpolation with optimized multiplier width using companding in correction slope | |
| CN115276704B (en) | Up-conversion link system and device suitable for broadband digital TR chip | |
| CN112600777B (en) | Frequency offset compensation method and device suitable for 5G-NR receiver | |
| JP4430473B2 (en) | Offset compensation circuit | |
| WO2023103976A1 (en) | Local oscillator leakage calibration method and apparatus, electronic device and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |