CN112532331A - Engineering method for obtaining testability modeling test information - Google Patents

Abstract

The invention provides an engineering method for obtaining testability modeling test information, which carries out induction analysis on testability information required in a testability modeling process and designs four tables as a bridge for communication between product designers and testability modeling personnel, wherein the four tables are mainly used for obtaining input and output ports, fault modes, fault rate information, signal information and test point information of each functional unit; the method provides the acquisition method of the testability information and the engineering operation flow of the testability modeling, the flow is clear and simple, the information is complete and accurate, an effective information transmission channel can be established between designers and modelers, and the operation requirement of the engineering flow of the testability modeling is met.

Description

Engineering method for obtaining testability modeling test information

Technical Field

The invention belongs to the field of system fault test analysis, and particularly relates to an engineering method for obtaining testability modeling test information.

Background

The testability analysis and evaluation based on the multi-signal model provides a new idea for testability design, realizes that testability data such as fault detection rate, isolation rate and the like are obtained at the early stage of product design, is used for analyzing and evaluating the defects of the testability design, and improves the testability level of the product.

In engineering practice, testability information required by a multi-signal-based testability modeling process is difficult to accurately and completely acquire, so that testability modeling is very difficult. Because product development is completed by designers and testability modeling is completed by personnel engaged in testability design, the interaction between the two is less, professional docking is difficult, and information transfer is complex. Therefore, the key to accurately and completely acquire testability information is to eliminate the knowledge barrier existing between the product designer and the modeler. How to provide an engineering method for obtaining testability modeling test information by analyzing the characteristics of a multi-signal model and combining engineering practice research is very necessary.

Disclosure of Invention

In order to solve the problem of difficult information transmission caused by professional estrangement between product designers and modelers and further obtain accurate and complete testability information, the invention provides an engineering method for obtaining testability modeling test information by combining engineering practice so as to meet the requirement of improving the accuracy of a built testability model.

The engineering method for obtaining the testability modeling test information mainly comprises the following steps:

step1, defining the hierarchy of the system: according to the system function and structure, the system is divided into module units by layers step by step, and a tree-shaped hierarchical structure is established;

step2, filling the input and output signal tables of each functional unit of the system: analyzing logic output and input ports and output and input signals of each functional module, establishing a signal corresponding circulation relationship, and filling in input and output signal tables of each functional unit of the system after appropriate simplification;

step3, filling a fault mode cross-linking relation and fault rate information table: analyzing fault modes of all function levels of the system from bottom to top, establishing corresponding fault mode cross-linking relations, collecting statistical fault rate information, and filling corresponding fault mode cross-linking relations and fault rate information tables;

step4, filling out the signal table of each failure mode assignment: defining signals distributed by each fault mode, and filling a corresponding signal table;

step5, establishing a test signal correlation table of testable points: the establishment of the test points gives a list of all the testable points according to the feasible and effective test point layout considered in the system design, establishes the dependency relationship between the test and the fault mode, classifies the test points according to the requirement of the testability index on the maintenance level, defines the fault mode which can be detected by each test, sets different tests for each test point, and designs and fills in the test signal association table of the testable points;

step6, establishing a system testability model: after the information is obtained, a testability modeling and analyzing module in a testability design tool is applied to establish a directed graph, test points and tests are added, and fault rate information of a fault mode is added.

In the technical scheme, the provided engineering method for acquiring the testability modeling test information has clear and simple flow and complete and accurate information, can establish an effective information transmission channel between designers and modelers, and meets the operation requirement of the testability modeling engineering flow.

Drawings

FIG. 1 is a flow chart of testability modeling test information acquisition.

FIG. 2 is a diagram of a system hierarchy.

FIG. 3 is a table of external interfaces of training datalink interfaces in a system.

Fig. 4 is a table diagram of the failure mode cross-linking relationship and failure rate information of the if processing unit of the functional circuit stage of the training data link end machine in a certain system.

Fig. 5 is a signal diagram of the assignment of failure modes in a system.

Fig. 6 is a table showing the correlation of test signals at testable points of an if processing unit of a functional circuit stage of a training data link termination in a system.

Fig. 7 is a multi-signal flow model of a field replaceable unit (SRU) terminal module within a system.

Fig. 8 is a multi-signal flow model of a failure mode of an intermediate frequency processing unit in a functional circuit stage of a system.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to fig. 1 to 6, and it is obvious that the described embodiment is only a specific embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, testability modeling test information acquisition is performed on a certain system according to the flow.

As shown in fig. 2, a system is composed of a plurality of Line Replaceable Units (LRUs), such as a training data link terminal, a parameter collector, a multifunctional display, etc.; each Line Replaceable Unit (LRU) is further divided into a plurality of line replaceable units (SRUs), such as a front panel module, a terminal module, a data storage module, etc.; each infield replaceable unit (SRU) then functionally divides the functional modules, such as a clock management unit, a signal processing unit, an intermediate frequency processing unit, etc.

Because the signal input and output ports of each component in the system are many, the modeling can be properly simplified so as to indicate that the signal flow relation among the components is proper. Taking the training data link end machine as an example, the interface relationship is as shown in fig. 3.

The model is modeled by adopting a four-layer structure of a Line Replaceable Unit (LRU), a line replaceable unit (SRU), a function module and a fault mode, so that the fault mode of the function module at the level is only required to be obtained. The project analyzes the fault mode and the influence of each Line Replaceable Unit (LRU) from the component level to obtain the more comprehensive fault mode of the functional circuit level of each Line Replaceable Unit (LRU) and obtain the fault rate information of each fault mode. Taking the intermediate frequency processing unit of the functional circuit stage of the training data link end machine as an example, the failure mode cross-linking relationship and the failure rate information are shown in fig. 4.

Taking the partial failure modes in fig. 3 as an example, the signals assigned to the respective failure modes are clarified, and corresponding forms are filled, as shown in fig. 5.

By presenting a signal detectable by the test, a dependency relationship between the test and the failure mode is established, and the establishment of the test points in the model is based on a feasible and effective test point layout considered when designing the system. According to the requirement of the testability index on the maintenance level, the test points need to be classified: such as BIT detection, manual detection, etc. Defining the failure mode that each test can detect, each test point can set different tests, taking the intermediate frequency processing unit of the functional circuit stage of the training data link terminal as an example, and filling out the test signal association table of the testable points as shown in fig. 6.

Through the above engineering method, a multi-signal flow model of the infield replaceable unit (SRU) terminal module is obtained as shown in fig. 7, and a multi-signal flow model of the failure mode of the functional circuit level intermediate frequency processing unit is obtained as shown in fig. 8.

Claims (1)

1. An engineering method for testability modeling test information acquisition is characterized in that: the method mainly comprises the following steps:

step1, defining the hierarchy of the system: according to the system function and structure, the system is divided into module units by layers step by step, and a tree-shaped hierarchical structure is established;

step2, filling the input and output signal tables of each functional unit of the system: analyzing logic output and input ports and output and input signals of each functional module, establishing a signal corresponding circulation relationship, and filling in input and output signal tables of each functional unit of the system after appropriate simplification;

step3, filling a fault mode cross-linking relation and fault rate information table: analyzing fault modes of all function levels of the system from bottom to top, establishing corresponding fault mode cross-linking relations, collecting statistical fault rate information, and filling corresponding fault mode cross-linking relations and fault rate information tables;

step4, filling out the signal table of each failure mode assignment: defining signals distributed by each fault mode, and filling a corresponding signal table;

step5, establishing a test signal correlation table of testable points: the establishment of the test points gives a list of all the testable points according to the feasible and effective test point layout considered in the system design, establishes the dependency relationship between the test and the fault mode, classifies the test points according to the requirement of the testability index on the maintenance level, defines the fault mode which can be detected by each test, sets different tests for each test point, and designs and fills in the test signal association table of the testable points;

step6, establishing a system testability model: after the information is obtained, a testability modeling and analyzing module in a testability design tool is applied to establish a directed graph, test points and tests are added, and fault rate information of a fault mode is added.

Images