CN112528583B - Multithreading comprehensive method and comprehensive system for FPGA development - Google Patents
Multithreading comprehensive method and comprehensive system for FPGA development Download PDFInfo
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Abstract
The invention relates to a multithreading synthesis method and a synthesis system developed by FPGA, wherein at least one flow is set as a multithreading flow, the utilization rate of a processor can be improved and the synthesis time can be shortened compared with the single-thread flow, and for any one multithreading flow, the operation result corresponding to each thread is written back to a net list according to the specified sequence irrelevant to the time sequence of finishing each thread, so that the unstable phenomenon of the output result caused by different sequences of writing back the net list can be avoided, the result after the multiple operation synthesis in different environments is the same, and the stability of the output result can be improved. When the comprehensive system carries out logic synthesis of the FPGA module, the multithreading comprehensive method is utilized, and therefore system stability is improved.
Description
Technical Field
The invention relates to the field of EDA tool development, in particular to a multithreading comprehensive method and a comprehensive system for FPGA development.
Background
EDA (electronic Design Automation) is a Design method for completing the flow of functional Design, integration, verification, physical Design (including layout, wiring, layout, Design rule check, etc.) and the like of a Very Large Scale Integration (VLSI) chip by using Computer Aided Design (CAD). In the electronics industry, EDA plays an increasingly important role due to the increasing scale of the semiconductor industry, and EDA tools are also used in the development of various circuits.
In the EDA tool, a synthesis tool is used to convert a module written in a hardware description language (such as Verilog HDL) into a Netlist (Netlist, or Netlist file, Netlist), and the synthesis process can also be regarded as a Netlist conversion process. Using the netlist, it is further possible to fabricate specific application specific integrated circuits or other circuits, such as those of an FPGA (field programmable Gate Array).
The logic synthesis and the output of the logic netlist file are carried out by utilizing a synthesis tool, and the method is an important step for FPGA development. Currently, in the FPGA development, a commonly used synthesis mode is synchronous synthesis, i.e., single-thread synthesis. The "thread" refers to the smallest unit capable of performing operation scheduling by the operating system, and is included in the process (or flow), which is the actual operation unit in the process. For the single-thread synthesis mode, only one thread is executed at the same time, after the current thread is finished, the running result is written back to the netlist, and then the system redistributes the task of the next thread. However, in the existing environment, if a plurality of concurrent threads are set to execute tasks in parallel, after each thread is finished, the operation result is automatically written back to the netlist, and after a plurality of synthesis processes, the output netlist is operated, the results are often different, that is, the multithreading operation has uncertainty.
Disclosure of Invention
The inventor of the present application finds that, when a multi-thread execution logic synthesis process is adopted at present, the output result of multiple synthesis processes has uncertainty mainly because, for the multi-thread process, the time required for starting or executing different threads is not necessarily the same, if the threads are written back to the netlist in sequence according to the end sequence of the threads, the write-back sequence of each synthesis process is different, and when the results of multiple threads are combined into a whole synthesis result, the output content of the netlist after multiple synthesis operations are different, thereby causing uncertainty of multi-thread synthesis.
In order to shorten the time of comprehensive operation and improve the stability of the output result of the comprehensive operation, the invention provides a multithreading comprehensive method. An integrated system for FPGA development is also provided.
In one aspect, the present invention provides a multithreading synthesis method, including two or more processes executed in sequence, where at least one of the processes is a multithreading process, and the multithreading process includes multiple threads running in parallel, where, for any one of the multithreading processes, a running result corresponding to each thread is written back to a netlist according to a specified order, and the specified order is independent of a time order in which each thread ends.
Optionally, during the execution of the multithreading process, it is counted whether each thread is finished, and only after all threads are finished, the running results of each thread are sequentially written back to the netlist according to the specified order.
Optionally, when two or more of the flows are multi-threaded flows, each of the multi-threaded flows corresponds to one of the designated sequences.
Optionally, all the flows are multi-thread flows.
Optionally, the multi-thread process includes more than three threads running in parallel.
Optionally, the two or more processes sequentially executed include a netlist parsing process, a logic reasoning process, a logic optimization process, and a technology mapping process.
In one aspect, the invention provides an integrated system for FPGA development, where the integrated system includes a flow management module and a thread management module, the flow management module is configured to configure two or more flows corresponding to different integrated tasks and enable the flows to be executed in sequence, at least one of the flows is configured as a multi-thread flow, the multi-thread flow includes multiple threads running in parallel, and the thread management module is configured to enable a running result corresponding to each thread to be written back to a netlist according to a specified sequence for any one of the multi-thread flows, where the specified sequence is independent of a time sequence in which each thread ends.
Optionally, the thread management module includes a thread monitoring unit, and the thread monitoring unit is configured to count whether each thread is finished in the execution process of the multithreading process, and write back the running result of each thread to the netlist in sequence according to the specified order only after all threads are finished.
Optionally, the thread management module includes a thread selection unit, and the thread selection unit is configured to, during the execution of the multithreading process, determine whether a thread that is executed first is a thread that can currently write back to the netlist according to the corresponding specified order, if so, write back the thread that is executed first to the netlist, if not, put the thread that is executed first aside, and process the thread until it turns to write back to the netlist according to the corresponding specified order.
Optionally, the thread management module is further configured to: and in the case that more than two of the flows are all multi-threaded flows, configuring each multi-threaded flow to correspond to one specified sequence.
The multithreading synthesis method provided by the invention comprises more than two flows which are executed in sequence, wherein at least one flow is set as a multithreading flow, the utilization rate of a processor can be improved and the time consumed by the synthesis process can be shortened compared with the single-thread flow, in addition, in the multithreading synthesis method, for any one multithreading flow, the operation result corresponding to each thread is written back to a net list according to the specified sequence which is irrelevant to the time sequence of finishing each thread, so that the unstable output result phenomenon caused by different sequences of writing back the net list can be avoided, the results after multiple times of operation synthesis in different environments are the same, and the stability of the output result can be improved.
The comprehensive system for FPGA development provided by the invention comprises a flow management module and a thread management module, wherein when the logic synthesis of the FPGA module is carried out, at least one flow can be configured into a multi-thread flow by using the flow management module, so that the utilization rate of a processor is improved, the time consumed by the synthesis process is shortened, in addition, after each thread of the multi-thread flow is finished, the thread management module is used for writing back the corresponding running result to a netlist according to a specified sequence irrelevant to the finishing time sequence of each thread, the instability caused by different sequences of writing back the netlist is favorably avoided, the result after the multiple running synthesis in different environments is identical, and the stability of the system can be improved.
Drawings
FIG. 1 is a flow chart of a multithread synthesis method according to an embodiment of the invention.
FIG. 2 is a flowchart illustrating a multithread synthesis method according to an embodiment of the invention.
Fig. 3 is a schematic flow chart of FPGA development.
Fig. 4 is a block diagram of an integrated system for FPGA development according to an embodiment of the present invention.
Detailed Description
The multithreading integration method and the FPGA integration system of the present invention are further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
A thread is the smallest unit that an operating system can perform operation scheduling, is included in a process (i.e., a flow), and is the actual unit of operation in the process. One thread refers to a single sequential control flow in a process, one process can concurrently execute a plurality of threads, and each thread executes different tasks in parallel, so that the utilization rate of the processor can be improved, and the running time of comprehensive operation can be reduced. In the prior multithreading synthesis process, the result of multithreading parallel operation output for multiple times is often different due to some uncertainties in multithreading synthesis, so that the stability and reliability of the synthesis tool are reduced. In order to shorten the synthesis time and ensure the stability and reliability of the synthesis tool, the invention provides a multithreading synthesis method and an FPGA synthesis system.
The embodiment of the invention firstly relates to a multithreading synthesis method, which can be implemented by various EDA synthesis tools, such as an FPGA synthesis tool, a CPLD (Complex Programmable Logic Device) synthesis tool and the like, through synthesis, a module written by a hardware description language (such as Verilog HDL) can be converted into a netlist, and a specific FPGA circuit or a CPLD circuit can be further manufactured by utilizing the netlist. By "multi-threaded synthesis method" is meant herein that at least part of the flow is done by multi-threaded operations in the synthesis process. A "flow" herein refers to a process in an integrated process that has a specific purpose. For example, in one embodiment, the synthesis process may include netlist parsing (flow 1), logic inference (flow 2), logic optimization (flow 3), and technology mapping (flow 4) performed in sequence. The invention is not limited in this regard and the flow that the integrated operation needs to execute can be designed in accordance with the disclosed method.
The multithreading synthesis method comprises more than two processes which are executed in sequence, wherein at least one process is a multithreading process, the multithreading process comprises a plurality of threads which run in parallel, for any multithreading process, the running result corresponding to each thread is written back to a netlist according to a specified sequence, and the specified sequence is irrelevant to the time sequence of finishing each thread.
FIG. 1 is a flow chart of a multithread synthesis method according to an embodiment of the invention. The multithreading synthesis method of the embodiment of the present invention is further described below with reference to fig. 1.
Referring to fig. 1, in an embodiment, the integrated process includes a flow a and a flow B that are executed sequentially, where the flow a is completed by multiple threads, and the flow B is completed by a single thread, for example.
First, flow a is executed, which includes thread 1, thread 2, and thread 3 concurrently, i.e., thread 1, thread 2, and thread 3 are running simultaneously for at least part of the time period (the start-up time may be slightly different). The resources allocated to the thread 1, the thread 2 and the thread 3 by the processor can be different, and the tasks executed by the thread 1, the thread 2 and the thread 3 can be different, so that the time taken by each thread to finish executing is not necessarily the same, if each thread is about to write the operation result into the netlist after the operation is finished without paying attention to whether other threads finish, and under the condition that the finishing sequence of each thread can be different during multiple times of synthesis, the netlist optimization sequence or the final printing sequence can be changed (the sequence of allocating subsequent tasks by the processor is related to the sequence of writing back by each thread), so that the netlist output is unstable. In particular, if the thread continuously executes the following processes after writing back the netlist, for example, thread 1 writes the netlist first after finishing the netlist, and thread 1 then executes the following tasks when thread 2 and thread 3 have not finished or written the netlist, the specific process of the synthesis operation is further complicated, and multiple times of performing synthesis generate large differences, so that the results of multiple times of synthesis are very unstable.
Therefore, in the embodiment of the present application, after thread 1, thread 2, and thread 3 end, the operation results corresponding to the respective threads are written back to the netlist in a specified order, which is independent of the time sequence of thread 1, thread 2, and thread 3 end. Furthermore, even if the threads (e.g., thread 1, thread 2, and thread 3) of the multi-threaded flow do not start to run simultaneously, but start to run in a chronological order, the designated order used when the threads finish writing back to the netlist is independent of the chronological order in which the threads start to run. Here, the "specified order" may be an order set at the time of setting the synthesis parameters or at the time of flow configuration. Under the condition that the comprehensive parameters and the comprehensive flow are not changed, when the comprehensive operation is carried out for multiple times, because the sequence of the operation result write-back netlist of each thread is the specified sequence, the problem that the sequence is inconsistent and the output of the comprehensive result is unstable due to the fact that the operation result is directly written-back netlist after each thread is finished in multiple times of execution can be avoided.
Referring to fig. 1, for flow a, the specified order of writing the running results of the three threads back to the netlist is the order of thread 1 first, thread 2 second, and thread 3 last in one embodiment, but in other embodiments, the specified order may be different from the order shown in fig. 1. The specified sequence may be, for example, the sequence of creating threads or other sequences, as long as the sequence is not changed by multithreading, so as to ensure that the netlist is fixed after multithreading is performed for multiple times. Depending on the specific task and processor conditions, a single multi-threaded flow may include one, two, or more than three threads running in parallel in an integrated process.
Referring to fig. 1, in the execution process of the multi-thread flow (such as flow a), before all threads write back to the netlist, a step of determining whether the threads end may be added, in which whether each thread ends is counted, and only after all the threads end, the operation results of each thread are sequentially written back to the netlist according to the specified sequence set corresponding to the current multi-thread flow (flow a). And when the requirement that all threads finish is not met, the thread which finishes first waits until all threads finish execution is confirmed, and then the running results are sequentially written back to the netlist according to the corresponding specified sequence, so that the process A finishes. In an embodiment, in the execution process of the multi-thread flow (for example, flow a), it is not necessary that the thread that is executed first waits for the other threads to end, but it may be determined first whether the thread that is executed first is a thread that can currently write back to the netlist according to a specified order, if so, the running result of the thread may be written back first, and if the thread that is executed first is not a thread that can currently write back to the netlist according to the specified order, the thread that is executed first needs to wait until the thread that is executed first writes back to the netlist according to the specified order. For example, for thread 1, thread 2 and thread 3 in fig. 1, if the specified write-back order is thread 1, thread 2 and thread 3 in turn, after thread 1 is executed, even if thread 2 and thread 3 are not executed, the operation result of thread 1 can be written back to the netlist first, but if thread 2 is executed first among the three threads, thread 2 needs to wait until thread 1 is executed and written back to the netlist, then the operation result of thread 2 is written back to the netlist, and in case both thread 1 and thread 2 are written back to the netlist, thread 3 can be written back to the netlist directly after execution is completed.
After the execution of the flow a is completed, the subsequent flows in the synthesis operation are continuously executed, as in the flow B in fig. 1, where the flow B may operate according to a single thread, one thread is executed at the same time, after the previous thread is finished and the operation result is written back to the netlist, the next thread is executed, after all the flows are finished, the netlist is output, and the synthesis operation is finished. Because the netlist is written back according to the specified sequence after the execution of the threads is finished when the process A is executed, even if the process A is executed for multiple times, the netlist which is finally output is fixed before the process B is executed by the same netlist.
FIG. 2 is a flowchart illustrating a multithread synthesis method according to an embodiment of the invention. Referring to fig. 2, in another embodiment, the flow a and the flow B both operate according to multiple threads, that is, two multi-thread flows executed in sequence are included, the flow a includes three threads executed simultaneously by the thread 1, the thread 2 and the thread 3 (the start and end times of the three threads may be different), and the flow B includes two threads executed simultaneously by the thread 4 and the thread 5 (the start and end times of the two threads may be different). For any of the multi-threaded flows, after each thread is finished, the corresponding run results are written back to the netlist in a specified order corresponding to the multi-threaded flow, the specified order being independent of the chronological order in which each of the threads was finished. The specified order in which the parallel multithreaded writeback netlist of flow B is taken (e.g., the second specified order in fig. 2) may be different from the specified order in which the parallel threaded writeback netlist of flow a is taken (e.g., the first specified order in fig. 2). By using the multithreading synthesis method, in the synthesis process, if more than two flows are multithreading flows, a specified sequence for writing the running result of each thread back to the netlist can be set for each multithreading flow. In one embodiment, the two multithreading flows use the same thread, and the specified order of writing the results of the thread operations back to the netlist in the two multithreading flows may be the same or different.
By adopting the multithreading comprehensive method provided by the embodiment of the invention, multithreading can be used in the whole comprehensive process or a certain flow in the comprehensive process, and a plurality of multithreading flows can adopt the same designated sequence or can be respectively set with different designated sequences to correspond to the multithreading flows. Specifically, in a multi-thread process, each thread may be allocated with resources by the same processor, and the processor may allocate more than three threads to run in parallel to execute a corresponding process, specifically, set according to the processor capability and task requirements. In the multithreading synthesis method, multithreading is usually required to be started once or for multiple times in the synthesis process, and after multithreading is started each time, the operation result of each thread is written back to the netlist according to the specified sequence of each time. Therefore, the netlist is fixed after each multithreading is executed, the netlist written back according to the sequence is unique, the multithreading operation can be guaranteed, the comprehensive results under different environments are also the same, and the output stability of the comprehensive operation can be improved compared with a mode of writing back the netlist according to the ending sequence.
The embodiment of the invention also comprises a comprehensive system for FPGA development. FPGA development is understood herein as designing the circuitry of an FPGA chip. Fig. 3 is a schematic flow chart of FPGA development. Referring to fig. 3, FPGA development generally includes several steps of module design (also called RTL (register transfer level) design), functional simulation (pre-simulation), logic synthesis, place and route, timing simulation (post-simulation), and board level verification. Specifically, in the module design step, the design target is divided into a plurality of functional modules according to requirements, and a program is written by adopting a hardware description language (such as Verilog HDL) to realize the functions of each functional module (if a certain module is universal, the existing IP (intellectual property) core can be called for use, so that the design efficiency can be improved); in the functional simulation step, a simulation tool (such as ModelSim) is used for verifying the logic function of each functional module, and whether the design requirements are met is judged; in the logic synthesis step, under the compiling environment, gate-level optimization is performed on the functional module described by the hardware description language through the processes of netlist parsing, logic reasoning, logic optimization, technical mapping and the like, and a logic netlist file (netlist for short) is output; in the step of layout and wiring, configuring hardware resources of the FPGA by using the logical relation provided by the netlist to form a circuit formed by hardware units existing in the FPGA; in the time sequence simulation step, time delay information of a device and wiring is considered, and the time sequence relation of a program in a target device is mainly verified; in the board-level verification step, the internal function of the FPGA and the function of the interface between the FPGA and an external device are verified.
The comprehensive system for FPGA development is used for carrying out logic synthesis (synthesis for short) on a designed FPGA functional module and outputting a corresponding netlist. Fig. 4 is a block diagram of an integrated system for FPGA development according to an embodiment of the present invention. Referring to fig. 4, in an embodiment, the integrated system for FPGA development includes a flow management module and a thread management module, the flow management module is configured to configure two or more flows corresponding to different integrated tasks and enable the flows to be executed in sequence, at least one of the flows is configured as a multi-thread flow, the multi-thread flow includes multiple threads running in parallel, and the thread management module is configured to enable a running result corresponding to each thread to be written back to a netlist according to a specified sequence for any one of the multi-thread flows, where the specified sequence is independent of a time sequence in which each thread ends.
Specifically, the process management module sets each process according to the configuration condition of the processor and arranges the processes to be executed in sequence, wherein, in order to improve the utilization rate of the processor and shorten the time consumed by the comprehensive operation, at least part of the processes are set as multi-thread processes, that is, tasks of at least part of the processes are completed through a plurality of threads executed in parallel, so as to replace a mode that a single thread is executed in sequence. In one embodiment, the flow set by the flow management module may include flows of netlist parsing, logic reasoning, logic optimization, and technology mapping. The invention is not limited in this regard and the flow that the integrated operation needs to execute can be designed in accordance with the disclosed method.
In addition, in order to ensure the uniqueness of the multiple comprehensive results in different environments of multi-thread operation, improve the stability of the comprehensive system and facilitate the comparison and debugging of the comprehensive operation performed by the user in different environments and multiple times, the comprehensive system further comprises a thread management module, wherein the thread management module is used for writing the corresponding operation results back to the netlist according to a specified sequence after each thread of the multi-thread flow is finished, and the specified sequence is unrelated to the time sequence of finishing each thread. Here, the "specified order" may be an order set at the time of setting the synthesis parameters or at the time of flow configuration. Under the condition that the comprehensive parameters and the comprehensive flow are not set, when the comprehensive operation is carried out for multiple times, the specified sequence is not changed, namely the sequence of writing back the netlist by each thread is not changed, so that the problem of unstable output of the comprehensive result caused by different sequences of writing back the netlist by the operation result after each thread is finished in multiple times of execution can be solved. In addition, the thread management module is further configured to, in a case where two or more of the flows are multi-threaded flows, configure each of the multi-threaded flows to correspond to one of the specified orders, and then control each of the threads to write back the running result to the netlist according to a fixed order for the different multi-threaded flows.
In a preferred embodiment, in the integrated system for FPGA development according to the embodiment of the present invention, the thread management module may include a thread monitoring unit, where the thread monitoring unit is configured to count whether each thread is finished during execution of the multithread process, and write back the running results of each thread to the netlist in sequence according to the specified sequence only after all the threads are finished. That is, when a multi-thread flow is executed and the requirement that all threads finish is not met, the thread that finishes first needs to wait until all threads finish execution is confirmed, and then write back the netlist according to the specified sequence, so that all threads can be ensured to write back the netlist according to the fixed sequence during each integration.
In the integrated system for FPGA development according to an embodiment of the present invention, the thread management module is not provided with the thread monitoring unit, but includes a thread selecting unit (not shown), where the thread selecting unit is configured to determine, during the execution of the multithread process, whether a thread that is executed first is a thread that can currently write back to the netlist according to the corresponding specified order, if so, write back the thread that is executed first to the netlist to reduce storage resources, and if not (that is, the thread that is executed first is not a thread that can currently write back to the netlist according to the specified order), put the thread that is executed first (that is, put the thread that is executed first to a waiting state) until the thread that is executed first is written back to the netlist according to the corresponding specified order, and then run the resulting netlist.
The comprehensive system for FPGA development of the embodiment of the invention can execute the flow tasks in a multithread parallel mode during comprehensive operation, and write the multithread executed in parallel back to the netlist according to the specified sequence, thereby ensuring that the comprehensive results of each time are the same when the multithread runs and is integrated for many times, ensuring that a user can still obtain the same results when the user integrates the same FPGA functional module under different operating systems and different compiling environments, and facilitating the comparison and debugging of the user.
The processing and execution of the methods and/or apparatuses in the above embodiments are generally implemented by means of software programs, and the apparatuses or devices, however, all (or a part of) them may also be implemented by means of electronic hardware. Whether implemented in software or hardware, the details of which are not repeated in this specification since those skilled in the electronic and software arts can implement them.
The method and structure in this embodiment are described in a progressive manner, and the following method and structure focus on illustrating the differences from the previous method and structure, and the relevant points can be understood by reference.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A multithreading synthesis method is characterized by comprising more than two processes which are executed in sequence, wherein at least one process is a multithreading process, the multithreading process comprises a plurality of threads which run in parallel, the running result corresponding to each thread is written back to a netlist according to a specified sequence for any multithreading process, the specified sequence is irrelevant to the time sequence of the ending of each thread, and in the process of carrying out synthesis operation for multiple times, the sequence of the running result of each thread written back to the netlist in the same multithreading process adopts the same specified sequence, so that the output results of the synthesis operation for multiple times are stable.
2. The multithread synthesis method according to claim 1, wherein during execution of the multithread flow, it is counted whether each thread is finished, and only after all the threads are finished, the running results of each thread are sequentially written back to a netlist according to the specified order.
3. The method of claim 1, wherein, in the case where two or more of said flows are multi-threaded flows, each of said multi-threaded flows corresponds to one of said specified orders.
4. The multi-threaded synthesis method of claim 1, wherein all of the flows are multi-threaded flows.
5. The multi-threaded synthesis method of claim 1, wherein the multi-threaded flow comprises more than three of the threads running in parallel.
6. The multi-threaded synthesis method of claim 1, wherein the two or more processes performed in sequence include a netlist parsing process, a logic reasoning process, a logic optimization process, and a technology mapping process.
7. An integrated system for FPGA development, the integrated system comprising:
the flow management module is used for configuring more than two flows corresponding to different comprehensive tasks and enabling the flows to be executed in sequence, wherein at least one flow is configured to be a multi-thread flow, and the multi-thread flow comprises a plurality of threads which run in parallel; and the number of the first and second groups,
and the thread management module is used for enabling the running result corresponding to each thread to be written back to the netlist according to a specified sequence aiming at any one multithreading process, wherein the specified sequence is irrelevant to the time sequence of finishing each thread, and when the multi-thread process is carried out for multiple times, the sequence of the running results of each thread written back to the netlist in the same multithreading process adopts the same specified sequence, so that the output results of the multi-time comprehensive operation are stable.
8. The integrated system according to claim 7, wherein the thread management module includes a thread monitoring unit, and the thread monitoring unit is configured to count whether each of the threads is finished during execution of the multi-threaded flow, and write back the running results of each of the threads to the netlist in sequence according to the specified order only after all of the threads are finished.
9. The integrated system of claim 7, wherein the thread management module comprises a thread selection unit, and the thread selection unit is configured to determine, during execution of the multi-threaded flow, whether a thread that has been executed first is a thread that can currently write back to a netlist according to the corresponding specified order, if so, write back the thread that has been executed first to the netlist, and if not, put the thread that has been executed first aside until it comes to write back to the netlist according to the corresponding specified order, and then process the thread that has been executed first.
10. The integrated system of claim 7, wherein the thread management module is further to: and in the case that more than two of the flows are all multi-threaded flows, configuring each multi-threaded flow to correspond to one specified sequence.
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