CN112527086A - Hardware delay reset circuit - Google Patents
Hardware delay reset circuit Download PDFInfo
- Publication number
- CN112527086A CN112527086A CN202011413269.4A CN202011413269A CN112527086A CN 112527086 A CN112527086 A CN 112527086A CN 202011413269 A CN202011413269 A CN 202011413269A CN 112527086 A CN112527086 A CN 112527086A
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- hardware
- power supply
- module
- pin
- interface module
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- 239000003990 capacitor Substances 0.000 claims description 23
- 238000010586 diagram Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
Abstract
The invention discloses a hardware delay reset circuit which comprises a key interface module, a hardware reset module, a power panel power supply interface module and a power switch control module; the hardware reset module is connected with the key interface module and the power supply board power supply interface module; the key interface module is connected with a key; the power supply board power supply interface module is connected with the power switch control module; and the hardware reset module controls the power supply board power supply interface module and the power switch control module to realize power-off control. The hardware delay reset circuit provided by the invention realizes that the power supply is turned off by pressing the key for a long time through adding the hardware delay reset circuit on the normal key of the equipment so as to achieve the purpose of restarting the equipment, does not influence the normal use of short pressing of the key during normal work, is convenient to realize, and solves the problem of quick reset and restart after the equipment is halted due to software problems.
Description
Technical Field
The invention relates to the technical field of hardware delay reset, in particular to a hardware delay reset circuit.
Background
For electronic equipment, when the equipment has a crash problem caused by a software problem, the equipment can be restarted only by pulling out a power line for the equipment without a hardware power switch, and when the equipment is made into wall hanging, for example, a display device, if the crash problem caused by the software occurs, the equipment is difficult to restart in case of power failure through the operation.
Disclosure of Invention
The invention provides a hardware delay reset circuit, aiming at solving the problem of power-off reset restart of the existing electronic equipment.
In order to achieve the above object, the present invention provides a hardware delay reset circuit, which includes a key interface module, a hardware reset module, a power board power supply interface module and a power switch control module; the hardware reset module is connected with the key interface module and the power supply board power supply interface module; the key interface module is connected with a key; the power supply board power supply interface module is connected with the power switch control module; and the hardware reset module controls the power supply board power supply interface module and the power switch control module to realize power-off control.
Preferably, the hardware reset module comprises a chip UW1 and a hardware reset control circuit, and pin 3 and pin 7 of the chip UW1 are respectively connected to the key interface module; pin 8 of the chip UW1 is connected to the operating voltage through diode DW1, to ground through capacitor CW1, and to pin 1 and the hardware reset control circuit through resistor RW 4.
Preferably, the hardware reset control circuit comprises a transistor QW2 and a transistor QW1, wherein the 1 end of the transistor QW2 is connected with the 1 end of the chip UW1 and the 3 end of the chip UW1 through a resistor RW5, the +5V _ SB voltage is connected through a resistor RW3, and the 2 end of the transistor QW1 is grounded; the 2 end of the triode QW1 is connected with +5V _ SB voltage through a resistor RW1, the 3 end is connected with the power supply board power supply interface module and is grounded through a resistor RW 7.
Preferably, the pin 5 of the chip UW1 is grounded after being connected in parallel through the capacitors CW2 and CW3, and the pin 6 is grounded through the capacitor CW 4.
Preferably, the power board power supply interface module comprises a connector CONW1, and the connector CONW1 is used for connecting a power supply, the hardware reset module and the power switch control module.
Preferably, the power switch control module comprises a MOS tube QW3 and a triode QW4, wherein the pin 1-pin 3 of the MOS tube QW3 are connected with +5V _ SB voltage, and are connected with a resistor RW9 in parallel after being connected with a capacitor CW6 and a resistor RW10 in series, and then are connected with the end 3 of the triode QW 4; a pin 4 of the MOS tube QW3 is connected between a capacitor CW6 and a resistor RW 10; the pins 5-8 of the MOS tube QW3 are connected with +5V _ Standby voltage and grounded through a capacitor CW 5.
Preferably, the 1 end of the transistor QW4 is connected to the hardware reset module, and the 2 end is grounded.
Preferably, the key interface module comprises a connector CONL1, pin 2 of the CONL1 is connected to the hardware reset module, pin 3 is connected to the key, and pin 1 is grounded.
The hardware delay reset circuit provided by the invention realizes that the power supply is turned off by pressing the key for a long time through adding the hardware delay reset circuit on the normal key of the equipment so as to achieve the purpose of restarting the equipment, does not influence the normal use of short pressing of the key during normal work, is convenient to realize, and solves the problem of quick reset and restart after the equipment is halted due to software problems.
Drawings
Fig. 1 is a schematic structural diagram of a hardware delay reset circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of the key interface module of FIG. 1;
FIG. 3 is a circuit schematic of the hardware reset module of FIG. 1;
FIG. 4 is a circuit diagram of the power interface module of the power strip of FIG. 1;
FIG. 5 is a circuit diagram of the power switch control module of FIG. 1;
FIG. 6 is a diagram illustrating the relationship between the SR0 and SR1 pins being pulled low simultaneously to trigger the RST pin to be at a low level according to the hardware delay reset circuit of the present invention;
FIG. 7 shows a circuit diagram of a hardware delay reset circuit according to an embodiment of the present inventionSRCThe corresponding relation between the capacitor CW2 and the capacitor CW3 is shown schematically;
FIG. 8 is a block diagram of a hardware delay complex according to an embodiment of the present inventionT of bit circuitRECThe corresponding relation with the capacitance CW4 is shown schematically.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a hardware delay reset circuit, where a key on a normal key panel has a conventional key function under normal conditions, a hardware delay reset circuit is added on the normal key panel, and the hardware delay reset circuit performs on-off control through pulling down a level detection of a power board by long pressing of the key on the key panel, thereby implementing a restart operation of the power board and achieving a purpose of restarting a device when a system is powered off.
Referring to fig. 1, in an embodiment of the present invention, the hardware delay reset circuit includes a key interface module 10, a hardware reset module 20, a power board power supply interface module 30, and a power switch control module 40; the hardware reset module 20 is connected with the key interface module 10 and the power panel power supply interface module 30; the key interface module 10 is connected with keys; the power panel power supply interface module 30 is connected with the power switch control module 40; the hardware reset module 20 controls the power board power supply interface module 30 and the power switch control module 40 to realize power-off control.
Referring to fig. 2, specifically, the key interface module 10 includes a connector CONL1, pin 2 of the CONL1 is connected to the hardware reset module, pin 3 is connected to the key, and pin 1 is grounded.
Referring to fig. 3, the hardware reset module 20 includes a chip UW1 and a hardware reset control circuit, and pin 3 and pin 7 of the chip UW1 are respectively connected to the key interface module; pin 8 of the chip UW1 is connected to the operating voltage through diode DW1, to ground through capacitor CW1, and to pin 1 and the hardware reset control circuit through resistor RW 4. The hardware reset control circuit comprises a triode QW2 and a triode QW1, wherein the 1 end of the triode QW2 is connected with the 1 end of the chip UW1 and the 3 end of the triode QW1 through a resistor RW5, the +5V _ SB voltage is connected through a resistor RW3, and the 2 end of the triode QW1 is grounded; the 2 end of the triode QW1 is connected with +5V _ SB voltage through a resistor RW1, the 3 end is connected with the power supply board power supply interface module and is grounded through a resistor RW 7. Pin 5 of the chip UW1 is grounded after being connected in parallel through capacitors CW2 and CW3, and pin 6 is grounded through capacitor CW 4.
Referring to fig. 4, the power board power supply interface module includes a connector CONW1, and the connector CONW1 is used for connecting a power supply, the hardware reset module, and a power switch control module. Specifically, pins 1 and 3 of the connector CONW1 are connected to +5V _ SB voltage, pins 5, 7 and 9 are connected to a power supply, pins 11 and 12 are connected to a device power supply, pin 13 is connected to the 3 terminal of the transistor QW2 of the hardware reset module, and pin 14 is connected to the 3 terminal of the transistor QW1 of the hardware reset module.
Referring to fig. 5, the power switch control module includes a MOS transistor QW3 and a transistor QW4, where pin 1-pin 3 of the MOS transistor QW3 are connected to +5V _ SB voltage, and are connected in parallel with a resistor RW9 through a series connection of a capacitor CW6 and a resistor RW10, and then are connected to the 3-terminal of the transistor QW 4; a pin 4 of the MOS tube QW3 is connected between a capacitor CW6 and a resistor RW 10; the pins 5-8 of the MOS tube QW3 are connected with +5V _ Standby voltage and grounded through a capacitor CW 5. And the 1 end of the triode QW4 is connected with the hardware reset module, and the 2 end is grounded.
Specifically, in an embodiment of the present invention, the chip UW1 of the hardware reset module is implemented by an STM6510, pin 3 of the chip UW1 is an SR0 pin, pin 7 is an SR1 pin, pin 1 is an RST pin, and pin 5 is an SRC pin; the pin 3 and the pin 7 are respectively connected with the key interface module, when a key is pressed for a long time, the SR0 and SR1 pins are simultaneously pulled down for a period of time, and when the SR0 and SR1 pins are simultaneously pulled down, t is setSRCAt time, triggering RST pin to output tRECThe power supply board is powered by the power supply board interface module at low time level through a hardware reset control circuit consisting of two-stage triodes QW2 and triodesThe STANDBY pin of the connector CONW1 is pulled low, so that the power board is powered off, and the purpose of hardware reset is achieved. Where t isSRCAnd tRECThe length of time may be preconfigured.
Referring to FIGS. 6, 7 and 8 in combination, FIG. 6 shows that when the SR0 and SR1 pins are pulled low at the same time, tSRCAt time, triggering RST pin to output tRECLow level of time. FIG. 7 shows that when the SR0 and SR1 pins are pulled low at the same time, tSRCThe capacitance values of the capacitor CW2 and the capacitor CW3 and t are measured in timeSRCThe relationship between time; FIG. 8 shows the result when the RST pin outputs tRECTime, capacitors CW4 and tRECThe relationship between time; therefore, the hardware delay reset circuit can accurately realize power-off reset of the equipment, thereby achieving the purpose of restarting the equipment.
Compared with the prior art, the hardware delay reset circuit provided by the invention has the advantages that the purpose of restarting the equipment is achieved by turning off the power supply by pressing the key for a long time through adding the hardware delay reset circuit on the normal key of the equipment, the normal use of the key for a short time is not influenced during normal work, the realization is convenient, and the problem of quick reset and restart after the equipment is halted due to software problems of the equipment is solved.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A hardware delay reset circuit is characterized by comprising a key interface module, a hardware reset module, a power board power supply interface module and a power switch control module; the hardware reset module is connected with the key interface module and the power supply board power supply interface module; the key interface module is connected with a key; the power supply board power supply interface module is connected with the power switch control module; and the hardware reset module controls the power supply board power supply interface module and the power switch control module to realize power-off control.
2. The hardware delay reset circuit of claim 1, wherein the hardware reset module comprises a UW1 chip and a hardware reset control circuit, and pin 3 and pin 7 of the UW1 chip are respectively connected to the key interface module; pin 8 of the chip UW1 is connected to the operating voltage through diode DW1, to ground through capacitor CW1, and to pin 1 and the hardware reset control circuit through resistor RW 4.
3. The hardware delay reset circuit of claim 2, wherein the hardware reset control circuit comprises a transistor QW2 and a transistor QW1, wherein the terminal 1 of the transistor QW2 is connected to the terminal 1 of the chip UW1, the terminal 3 of the transistor QW1 through a resistor RW5, and the terminal 2 of the transistor QW is connected to the voltage +5V _ SB through a resistor RW 3; the 2 end of the triode QW1 is connected with +5V _ SB voltage through a resistor RW1, the 3 end is connected with the power supply board power supply interface module and is grounded through a resistor RW 7.
4. The hardware delay reset circuit of claim 3, wherein pin 5 of the UW1 is grounded after being connected in parallel by capacitors CW2 and CW3, and pin 6 is grounded by capacitor CW 4.
5. The hardware delay reset circuit of claim 1, wherein the power board power interface module comprises a connector CONW1, the connector CONW1 is used for connecting a power supply, the hardware reset module and a power switch control module.
6. The hardware delay reset circuit of claim 1, wherein the power switch control module comprises a MOS transistor QW3 and a transistor QW4, the MOS transistor QW3 has a +5V _ SB voltage connected to pin 1-pin 3, and is connected to the terminal 3 of the transistor QW4 after being connected in parallel with a resistor RW9 after being connected in series with a capacitor CW6 and a resistor RW 10; a pin 4 of the MOS tube QW3 is connected between a capacitor CW6 and a resistor RW 10; the pins 5-8 of the MOS tube QW3 are connected with +5V _ Standby voltage and grounded through a capacitor CW 5.
7. The hardware delay reset circuit of claim 6, wherein the transistor QW4 has a terminal 1 connected to the hardware reset module and a terminal 2 connected to ground.
8. The hardware delay reset circuit of claim 1, wherein the key interface module comprises a connector CONL1, pin 2 of the CONL1 is connected to the hardware reset module, pin 3 is connected to a key, and pin 1 is connected to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011413269.4A CN112527086A (en) | 2020-12-02 | 2020-12-02 | Hardware delay reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011413269.4A CN112527086A (en) | 2020-12-02 | 2020-12-02 | Hardware delay reset circuit |
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| Publication Number | Publication Date |
|---|---|
| CN112527086A true CN112527086A (en) | 2021-03-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011413269.4A Pending CN112527086A (en) | 2020-12-02 | 2020-12-02 | Hardware delay reset circuit |
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| CN (1) | CN112527086A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080070617A1 (en) * | 2006-09-15 | 2008-03-20 | Samsung Electronics Co., Ltd. | Reset circuit and method of mobile phone |
| CN101197979A (en) * | 2007-12-05 | 2008-06-11 | 深圳创维数字技术股份有限公司 | Energy-saving standby system of digital television receiver |
| CN101990226A (en) * | 2009-07-31 | 2011-03-23 | 大唐移动通信设备有限公司 | Automatic restart method, system and device for power failure |
| CN202218293U (en) * | 2011-07-22 | 2012-05-09 | 深圳市华域无线技术有限公司 | Mobile phone hardware reset system |
| CN103905756A (en) * | 2014-03-26 | 2014-07-02 | 深圳创维－Rgb电子有限公司 | Television set failure processing device and television set |
| CN110221671A (en) * | 2019-04-25 | 2019-09-10 | 维灵（杭州）信息技术有限公司 | A kind of false-touch prevention bill key hardware reset method, chip and wearable device |
| CN111900792A (en) * | 2020-07-27 | 2020-11-06 | 深圳市优锁科技有限公司 | Intelligent lock reset circuit and method for replacing physical keys |
-
2020
- 2020-12-02 CN CN202011413269.4A patent/CN112527086A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080070617A1 (en) * | 2006-09-15 | 2008-03-20 | Samsung Electronics Co., Ltd. | Reset circuit and method of mobile phone |
| CN101197979A (en) * | 2007-12-05 | 2008-06-11 | 深圳创维数字技术股份有限公司 | Energy-saving standby system of digital television receiver |
| CN101990226A (en) * | 2009-07-31 | 2011-03-23 | 大唐移动通信设备有限公司 | Automatic restart method, system and device for power failure |
| CN202218293U (en) * | 2011-07-22 | 2012-05-09 | 深圳市华域无线技术有限公司 | Mobile phone hardware reset system |
| CN103905756A (en) * | 2014-03-26 | 2014-07-02 | 深圳创维－Rgb电子有限公司 | Television set failure processing device and television set |
| CN110221671A (en) * | 2019-04-25 | 2019-09-10 | 维灵（杭州）信息技术有限公司 | A kind of false-touch prevention bill key hardware reset method, chip and wearable device |
| CN111900792A (en) * | 2020-07-27 | 2020-11-06 | 深圳市优锁科技有限公司 | Intelligent lock reset circuit and method for replacing physical keys |
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Address after: Room 238, room 406, 1 Yichuang street, Huangpu District, Guangzhou, Guangdong 510700 Applicant after: Guangzhou langguo Electronic Technology Co.,Ltd. Address before: Room 238, room 406, 1 Yichuang street, Huangpu District, Guangzhou, Guangdong 510700 Applicant before: GUANGZHOU LANGO ELECTRONIC SCIENCE & TECHNOLOGY Co.,Ltd. |
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