CN112506838A - SPI clock synchronization method applied to IR46 electric meter calibrating device - Google Patents
SPI clock synchronization method applied to IR46 electric meter calibrating device Download PDFInfo
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- CN112506838A CN112506838A CN202011167230.9A CN202011167230A CN112506838A CN 112506838 A CN112506838 A CN 112506838A CN 202011167230 A CN202011167230 A CN 202011167230A CN 112506838 A CN112506838 A CN 112506838A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
An SPI clock synchronization method applied to an IR46 electric meter calibration device is used for solving the problem of communication abnormity caused by clock synchronization abnormity in SPI slave computer communication. The invention utilizes the time interval between the communication data frames to actively switch the CS signal by carrying out hardware configuration, forbidding CS, setting DMA transmission mode, configuring SPI and enabling, configuring Timer and enabling, detecting the clock signal SCLK and the synchronization sequence for forbidding re-enabling the CS signal, thereby achieving the purpose of clock synchronization. Through the interval synchronous clock, the successful communication between the SPI master and the SPI slave is realized, the clock loss problem is solved, the data dislocation is avoided, and the data integrity and the normal operation of the communication are ensured.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to an SPI clock synchronization method applied to an IR46 electric meter calibrating device.
Background
SPI is a serial synchronous communication means. The system is mainly used for communication between chips on a board, and has a master-slave division, a master machine bears the responsibility provided by a clock, and a slave machine interacts with the master machine according to the clock provided by the master machine. The slave generally has a cs (chip select) signal for clock synchronization with the master to prevent data skew.
If the host does not control the CS signal, the slave cannot determine the start of the clock, and only starts counting from the nearest clock signal, which may cause the clock signal to be misaligned, thereby causing data misalignment and affecting the normal interaction of data. There is currently no mature method of dealing with this situation on the market.
Disclosure of Invention
In order to solve the problems, the invention provides an SPI clock synchronization method applied to an IR46 electric meter verification device, which is used for solving the problem of communication abnormity caused by clock synchronization abnormity during communication of an SPI slave machine.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the CS signals are actively switched by using the time interval between communication data frames and the synchronization sequence for forbidding re-enabling of the CS signals, so as to achieve clock synchronization.
The specific working process is as follows:
step 1: when in wiring, a GPIO (General-purpose input/output) is connected to a signal of a CS (Chip Select) slave of an SPI (Serial Peripheral Interface) so as to control the switching of the CS;
step 2: switching the CS to a forbidden state through GPIO to prevent abnormal receiving of data caused by the initial uncertain state of the CS;
and step 3: configuring a receiving and transmitting mode of the SPI master and slave machine as DMA transmission;
and 4, step 4: configuring a CS signal of the SPI slave machine as hardware control and enabling the SPI;
and 5: a clock signal SCLK (SPI clock) of the SPI is connected to a Timer input and used for detecting the clock signal SCLK and determining a Timer period according to a frame interval to enable the Timer;
step 6: detecting a clock signal SCLK, if a clock edge (rising edge or falling edge) is detected on the Timer input pin, clearing 0 in a counting register of the Timer, and repeating the step 6 until the overflow interruption of the Timer is triggered; if the clock signal SCLK is not received within the designated time, triggering the overflow interruption of the Timer, and entering step 7;
and 7: performing the synchronization sequence of the CS: and forbidding and re-enabling the CS signal, realizing clock synchronization, and returning to the step 6 for repeated operation.
Wherein, the step 1 is hardware configuration, and the steps 2, 3, 4 and 5 are software configuration.
Further, in step 6, the detection clock signal SCLK needs to have a certain time interval, which is greater than the clock period.
Further, the repeated operation in step 7 may also be specified according to actual needs.
Further, the specified time in step 6 is determined according to the frame interval and the clock cycle, and the time is greater than the clock cycle and less than the frame interval, and meanwhile, the CS synchronization sequence can be guaranteed to be completed within the frame interval.
The invention has the beneficial effects that:
through the interval synchronous clock, the successful communication of the SPI master and the SPI slave is realized, the clock loss problem is solved, the data dislocation is avoided, and the data integrity and the normal operation of the communication are ensured.
Drawings
Fig. 1 is a graph of CS signal enable versus clock signal for a general SPI clock synchronization method applied to an IR46 meter verification device.
Fig. 2 is a flow chart of the SPI clock synchronization method applied to the IR46 electric meter verification device according to the present invention.
Fig. 3 is a CS synchronization sequence diagram of the SPI clock synchronization method applied to the IR46 electric meter verification apparatus according to the present invention.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The technical solution in the embodiments of the present invention is clearly and completely described below with reference to the drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention actively switches the CS signals by utilizing the time interval between communication data frames and through the synchronization sequence for prohibiting the CS signals from being re-enabled, thereby achieving the clock synchronization.
As shown in fig. 1, the specific working process of the present invention is as follows:
step 1: hardware configuration: when in wiring, a GPIO (General-purpose input/output) is connected to a signal of a CS (Chip Select) slave of an SPI (Serial Peripheral Interface) so as to control the switching of the CS;
step 2: switching the CS to a forbidden state through GPIO to prevent abnormal receiving of data caused by the initial uncertain state of the CS;
and step 3: configuring a receiving and transmitting mode of the SPI master and slave machine as DMA transmission;
and 4, step 4: configuring a CS signal of the SPI slave machine as hardware control and enabling the SPI;
and 5: a clock signal SCLK (SPI clock) of the SPI is connected to a Timer input and used for detecting the clock signal SCLK and determining a Timer period according to a frame interval to enable the Timer;
step 6: detecting a clock signal SCLK, if a clock edge (rising edge or falling edge) is detected on the Timer input pin, clearing 0 in a counting register of the Timer, and repeating the step 6 until the overflow interruption of the Timer is triggered; if the clock signal SCLK is not received within the designated time, triggering the overflow interruption of the Timer, and entering step 7;
and 7: performing the synchronization sequence of the CS: and forbidding and re-enabling the CS signal, realizing clock synchronization, and returning to the step 6 for repeated operation.
Wherein, the step 1 is hardware configuration, and the steps 2, 3, 4 and 5 are software configuration.
Further, in step 6, the detection of the clock signal SCLK requires a time interval greater than the clock period.
Further, the repeated operation in step 7 may also be specified according to actual needs.
Further, the designated time in step 6 is determined by the CPU according to the frame interval and the clock cycle, and the time is greater than the clock cycle and smaller than the frame interval, and meanwhile, the CS synchronization sequence can be guaranteed to be completed within the frame interval.
Finally, it should be noted that: the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person of ordinary skill in the art can make modifications or equivalents to the specific embodiments of the present invention with reference to the above embodiments, and such modifications or equivalents without departing from the spirit and scope of the present invention are within the scope of the claims of the present invention as set forth in the claims.
Claims (5)
1. An SPI clock synchronization method applied to an IR46 electric meter verification device is characterized in that time intervals between communication data frames are utilized, and CS signals are actively switched through a synchronization sequence for inhibiting re-enabling of the CS signals, so that clock synchronization is achieved.
2. The SPI clock synchronization method applied to an IR46 electric meter verification device according to claim 1, comprising the following steps:
step 1: hardware configuration: when in wiring, a GPIO (General-purpose input/output) is connected to a signal of a CS (Chip Select) slave of an SPI (Serial Peripheral Interface) so as to control the switching of the CS;
step 2: switching the CS to a forbidden state through GPIO to prevent abnormal receiving of data caused by the initial uncertain state of the CS;
and step 3: configuring a receiving and transmitting mode of the SPI master and slave machine as DMA transmission;
and 4, step 4: configuring a CS signal of the SPI slave machine as hardware control and enabling the SPI;
and 5: a clock signal SCLK (SPI clock) of the SPI is connected to a Timer input and used for detecting the clock signal SCLK and determining a Timer period according to a frame interval to enable the Timer;
step 6: detecting a clock signal SCLK, if a clock edge (rising edge or falling edge) is detected on the Timer input pin, clearing 0 in a counting register of the Timer, and repeating the step 6 until the overflow interruption of the Timer is triggered; if the clock signal SCLK is not received within the designated time, triggering the overflow interruption of the Timer, and entering step 7;
and 7: performing the synchronization sequence of the CS: and forbidding and re-enabling the CS signal, realizing clock synchronization, and returning to the step 6 for repeated operation.
3. The SPI clock synchronization method applied to the IR46 electric meter verification device according to claim 2, wherein in the step 6, the detection clock signal SCLK needs to have a certain time interval, and the time interval is greater than a clock period.
4. The SPI clock synchronization method applied to the IR46 electric meter verification device is characterized in that the repeated operation in the step 6 can be specified according to actual needs.
5. The SPI clock synchronization method applied to an IR46 meter verification device according to claim 2, wherein the specified time in step 6 is determined according to a frame interval and a clock period, and the time is greater than the clock period and less than the frame interval, and the CS synchronization sequence is guaranteed to be completed within the frame interval.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011167230.9A CN112506838A (en) | 2021-02-03 | 2021-02-03 | SPI clock synchronization method applied to IR46 electric meter calibrating device |
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| CN202011167230.9A CN112506838A (en) | 2021-02-03 | 2021-02-03 | SPI clock synchronization method applied to IR46 electric meter calibrating device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113132047A (en) * | 2021-04-16 | 2021-07-16 | 中国电力科学研究院有限公司 | Communication synchronization method and system of protocol consistency testing device of double-core electric energy meter |
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Application publication date: 20210316 |