CN112466372B - Small-size Latch unit circuit and Flash chip - Google Patents
Small-size Latch unit circuit and Flash chip Download PDFInfo
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- CN112466372B CN112466372B CN202011535598.6A CN202011535598A CN112466372B CN 112466372 B CN112466372 B CN 112466372B CN 202011535598 A CN202011535598 A CN 202011535598A CN 112466372 B CN112466372 B CN 112466372B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
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Abstract
Compared with the traditional Latch unit, the number of mos tubes used by the circuit is greatly reduced, and the whole circuit not only meets the basic functions of configurable information bits of a config configuration module: the default value and the updatable data are electrified; meanwhile, the size of the whole Latch unit circuit is reduced, and the consumption of the Flash chip area is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a small-size Latch unit circuit and a Flash chip.
Background
A config configuration module is arranged in the Flash circuit and used for configuring information such as voltage parameters, establishing time, function selection and the like in the Flash. The configuration information bit of the config configuration module needs to satisfy the condition that the default value is electrified and the configuration information can be updated. The configuration information bits of the config configuration module include 32 bits as a few bits and 256 bits or more as many bits, each bit of the configuration information bits needs a latch unit circuit for storage, and 256 bits need 256 latch units.
The common digital library Latch unit has more MOS tubes and larger area, and the config configuration module uses the digital library Latch unit, thereby occupying excessive area resources and being not beneficial to reducing the requirement of the whole area of the Flash. As shown in FIG. 1, the basic latch function of a latch unit of a common digital library can be realized by using 19 MOS transistors in total, the latch has no address selection signal, the periphery of the latch needs to be subjected to address selection processing, at least one AND gate needs to be added to process the address selection signal and then send the signal to a CK end, and at least 23 MOS transistors are actually used.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a small-size Latch unit circuit and a Flash chip, and aims to solve the problems that the existing Latch unit uses a large number of MOS (metal oxide semiconductor) tubes and has a large area.
The technical scheme of the invention is as follows: a small-sized Latch cell circuit, comprising:
a default value writing module for writing default value data into the configuration information bit when the Flash chip is powered on;
the data writing module writes data into the configuration information bits when the configuration information bits need to update the data;
the data latch module is used for latching the data in the configuration information bits;
the data output module is used for outputting the data in the configuration information bits;
the default value writing module is connected with the data latch module, the data latch module is connected with the data writing module, and the data latch module is connected with the data output module.
The small-size Latch unit circuit comprises a data write module and a data write module, wherein the data write module comprises a first mos tube nm1, a second mos tube nm2 and a third mos tube nm3, a drain of the first mos tube nm1 is connected with the data Latch module, a gate of the first mos tube nm1 is connected with a write enable DUMP _ EN, a source of the first mos tube nm1 is connected with a drain of the second mos tube nm2, a source of the second mos tube nm2 is connected with a drain of the third mos tube nm3, a source of the third mos tube nm3 is used for inputting a data signal Din, a gate of the second mos tube nm2 is connected with a first address selection signal YA, and a gate of the third mos tube nm3 is connected with a second address selection signal YB.
The small-size Latch unit circuit is characterized in that the first mos tube nm1, the second mos tube nm2 and the third mos tube nm3 are nmos tubes.
The small-size Latch unit circuit is characterized in that the data Latch module comprises a fourth mos tube pm1, a fifth mos tube nm4, a sixth mos tube pm2, a seventh mos tube pm3, an eighth mos tube nm5 and a ninth mos tube nm6, the source of the fourth mos tube pm1 is connected with a power supply voltage VDD, the drain of the fourth mos tube pm1 is connected with the drain of the fifth mos tube nm4, the source of the fifth mos tube nm4 is grounded, the gate of the fifth mos tube nm4 is connected with the gate of the fourth mos tube pm1 and then connected with the default value writing module, and the gate of the fifth mos tube nm4 is connected with the gate of the fourth mos tube pm1 and then connected with the data output module 2 (in the embodiment, the gate of the fifth mos tube 4 is connected with the gate of the fourth mos tube pm1 and then connected with the drain of the first mos tube 1); the source of the sixth mos tube pm2 is connected with the power supply voltage VDD, the drain of the sixth mos tube pm2 is connected with the source of the seventh mos tube pm3, the drain of the seventh mos tube pm3 is connected with the drain of the eighth mos tube nm5, the source of the eighth mos tube nm5 is connected with the drain of the ninth mos tube nm6, the source of the ninth mos tube nm6 is grounded, the gate of the sixth mos tube pm2 is connected with the gate of the ninth mos tube nm6 and then connected with the drain of the fourth mos tube pm1, the gate of the seventh mos tube pm3 is connected with the first LATCH signal LATCH, the gate of the eighth mos tube nm5 is connected with the second LATCH signal LATCH _ B, and the second LATCH signal LATCH _ B is the inverse of the first LATCH signal LATCH; and the grid electrode of the fifth mos transistor nm4 is connected with the grid electrode of the fourth mos transistor pm1 and then connected with the drain electrode of the seventh mos transistor pm3, and the grid electrode of the sixth mos transistor pm2 is connected with the grid electrode of the ninth mos transistor nm6 and then connected with the data output module.
The small-size Latch unit circuit is characterized in that pmos tubes are adopted as the fourth mos tube pm1, the sixth mos tube pm2 and the seventh mos tube pm3, and nmos tubes are adopted as the fifth mos tube nm4, the eighth mos tube nm5 and the ninth mos tube nm 6.
The small-size Latch unit circuit comprises a tenth mos tube pm4 and an eleventh mos tube nm7, wherein a source of the tenth mos tube pm4 is connected with a power supply voltage VDD, a gate of the tenth mos tube pm4 is connected with a gate of the eleventh mos tube nm7 and then connected with a data Latch module (in the embodiment, a gate of the tenth mos tube pm4 is connected with a gate of the eleventh mos tube nm7 and then connected with a gate of the sixth mos tube pm2 and a gate connection point of the ninth mos tube nm 6), a drain of the tenth mos tube pm4 is connected with a drain of the eleventh mos tube nm7, a source of the eleventh mos tube nm7 is grounded, and a drain of the tenth mos tube pm4 serves as a data output end, so that data in configuration information bits are output.
The Latch unit circuit with small size is characterized in that a pmos tube is adopted as the tenth mos tube pm4, and an nmos tube is adopted as the eleventh mos tube nm 7.
The small-size Latch unit circuit comprises a first Latch unit and a second Latch unit, wherein when the default value is 1, the default value writing module comprises a twelfth mos tube pm5, the source electrode of the twelfth mos tube pm5 is connected with a power supply voltage VDD, the drain electrode of the twelfth mos tube pm5 is connected with the data writing module, the drain electrode of the twelfth mos tube pm5 is connected with the data Latch module, and the grid electrode of the twelfth mos tube pm5 is connected with a first power-on control signal PRECHB.
The small-size Latch unit circuit comprises a logic circuit, wherein when the default value is 0, the default value writing module comprises a thirteenth mos transistor nm8, the drain of the thirteenth mos transistor nm8 is connected with the data writing module, the source of the thirteenth mos transistor nm8 is connected with the power ground, and the gate of the thirteenth mos transistor nm8 is connected with the second power-on control signal DISCH.
A Flash chip, comprising the small-sized Latch unit circuit as described in any one of the above.
The invention has the beneficial effects that: compared with the traditional Latch unit, the number of mos tubes used by the circuit is greatly reduced, and the whole circuit not only meets the basic functions of configurable information bits of a config configuration module: the default value and the updatable data are electrified; meanwhile, the size of the whole Latch unit circuit is reduced, and the consumption of the Flash chip area is reduced.
Drawings
FIG. 1 shows a latch cell with a default value of 1 in a prior art digital library.
FIG. 2 is a schematic diagram of a small Latch unit circuit with a default value of 1 according to the present invention.
FIG. 3 is a schematic diagram of a small Latch unit circuit with default value of 0 according to the present invention.
Fig. 4 is a timing diagram of the small Latch unit circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 2 and 3, a small-sized Latch unit circuit includes:
a default value writing module 1 writes default value data into the configuration information bit when the Flash chip is powered on;
the data writing module 2 writes data into the configuration information bits when the configuration information bits need to update the data;
the data latch module 3 is used for latching the data in the configuration information bits;
the data output module 4 is used for outputting the data in the configuration information bits;
the default value writing module 1 is connected with the data latch module 3, the data latch module 3 is connected with the data writing module 2, and the data latch module 3 is connected with the data output module 4.
In some embodiments, the data writing module 2 includes a first mos transistor nm1, a second mos transistor nm2, and a third mos transistor nm3, a drain of the first mos transistor nm1 is connected to the data latch module 3, a gate of the first mos transistor nm1 is connected to the write enable DUMP _ EN, a source of the first mos transistor nm1 is connected to a drain of the second mos transistor nm2, a source of the second mos transistor nm2 is connected to a drain of the third mos transistor nm3, a source of the third mos transistor nm3 is input with the data signal Din, a gate of the second mos transistor nm2 is connected to the first address selection signal YA, and a gate of the third mos transistor nm3 is connected to the second address selection signal YB.
In certain embodiments, the first mos tube nm1, the second mos tube nm2, and the third mos tube nm3 are all nmos tubes.
In some embodiments, the data latch module 3 includes a fourth mos tube pm1, a fifth mos tube nm4, a sixth mos tube pm2, a seventh mos tube pm3, an eighth mos tube nm5 and a ninth mos tube nm6, a source of the fourth mos tube pm1 is connected to the power supply voltage VDD, a drain of the fourth mos tube pm1 is connected to a drain of the fifth mos tube nm4, a source of the fifth mos tube nm4 is grounded, a gate of the fifth mos tube nm4 is connected to a gate of the fourth mos tube pm1 and then to the default value writing module 1, and a gate of the fifth mos tube nm4 is connected to a gate of the fourth mos tube pm1 and then to the data output module 2 (in this embodiment, a gate of the fifth mos tube nm4 is connected to a gate of the fourth mos tube pm1 and then to a drain of the first mos tube 1 nm); the source of the sixth mos tube pm2 is connected with the power supply voltage VDD, the drain of the sixth mos tube pm2 is connected with the source of the seventh mos tube pm3, the drain of the seventh mos tube pm3 is connected with the drain of the eighth mos tube nm5, the source of the eighth mos tube nm5 is connected with the drain of the ninth mos tube nm6, the source of the ninth mos tube nm6 is grounded, the gate of the sixth mos tube pm2 is connected with the gate of the ninth mos tube nm6 and then connected with the drain of the fourth mos tube pm1, the gate of the seventh mos tube pm3 is connected with the first LATCH signal LATCH, the gate of the eighth mos tube nm5 is connected with the second LATCH signal LATCH _ B, and the second LATCH signal LATCH _ B is the inverse of the first LATCH signal LATCH; the grid electrode of the fifth mos transistor nm4 is connected with the grid electrode of the fourth mos transistor pm1 and then connected with the drain electrode of the seventh mos transistor pm3, and the grid electrode of the sixth mos transistor pm2 is connected with the grid electrode of the ninth mos transistor nm6 and then connected with the data output module 4.
In certain embodiments, the fourth mos tube pm1, sixth mos tube pm2, and seventh mos tube pm3 are pmos tubes, and the fifth mos tube nm4, eighth mos tube nm5, and ninth mos tube nm6 are nmos tubes.
In some embodiments, the data output module 4 includes a tenth mos transistor pm4 and an eleventh mos transistor nm7, a source of the tenth mos transistor pm4 is connected to the power supply voltage VDD, a gate of the tenth mos transistor pm4 and a gate of the eleventh mos transistor nm7 are connected together and then connected to the data latch module 3 (in this embodiment, a gate of the tenth mos transistor pm4 and a gate of the eleventh mos transistor nm7 are connected together and then connected to a gate of the sixth mos transistor pm2 and a gate connection point of the ninth mos transistor nm 6), a drain of the tenth mos transistor pm4 is connected to a drain of the eleventh mos transistor nm7, a source of the eleventh mos transistor nm7 is grounded, and a drain of the tenth mos transistor pm4 serves as a data output terminal, and data in the configuration information bits are output.
In certain embodiments, the tenth mos tube pm4 is a pmos tube and the eleventh mos tube nm7 is an nmos tube.
In some embodiments, the default value writing module 1 is configured as follows:
example 1
As shown in fig. 2, when the default value is 1, the default value writing module includes a twelfth mos tube pm5, a source of the twelfth mos tube pm5 is connected to the power supply voltage VDD, a drain of the twelfth mos tube pm5 is connected to the data writing module 2 (in this embodiment, the drain of the twelfth mos tube pm5 is connected to the drain of the first mos tube nm 1), a drain of the twelfth mos tube pm5 is connected to the data latch module, and a gate of the twelfth mos tube 5 is connected to the first power-on control signal PRECHB.
In certain embodiments, the twelfth mos tube pm5 is a pmos tube.
Example 2
As shown in fig. 3, when the default value is 0, the default value writing module includes a thirteenth mos transistor nm8, a drain of the thirteenth mos transistor nm8 is connected to the data writing module 2 (in this embodiment, a drain of the thirteenth mos transistor nm8 is connected to a drain of the first mos transistor nm 1), a source of the thirteenth mos transistor nm8 is connected to the power ground, and a gate of the thirteenth mos transistor nm8 is connected to the second power-on control signal DISCH.
In certain embodiments, the thirteenth mos tube nm8 is an nmos tube.
In the technical scheme, the mos tubes are all the mos tubes with the minimum size.
As shown in fig. 4, it is a control timing diagram of the small Latch unit circuit, which not only satisfies the basic function of configurable information bits of the config module, but also is powered on with default value and updatable data; meanwhile, the size of the whole Latch unit circuit is reduced, and the consumption of the Flash chip area is reduced.
The technical scheme also protects a Flash chip which comprises the small-size Latch unit circuit.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. A small-sized Latch unit circuit, comprising:
a default value writing module for writing default value data into the configuration information bit when the Flash chip is powered on;
the data writing module writes an input data signal Din into the configuration information bit when the configuration information bit needs to update data;
the data writing module comprises a first mos tube nm1, a second mos tube nm2 and a third mos tube nm3, the drain of the first mos tube nm1 is connected with the data latch module, the gate of the first mos tube nm1 is connected with a write enable DUMP _ EN, the source of the first mos tube nm1 is connected with the drain of the second mos tube nm2, the source of the second mos tube nm2 is connected with the drain of the third mos tube nm3, the source of the third mos tube nm3 is connected with an input data signal Din, the gate of the second mos tube nm2 is connected with a first address selection signal YA, and the gate of the third mos tube nm3 is connected with a second address selection signal YB;
the data latch module is used for latching the data in the configuration information bits;
the data output module is used for outputting the data in the configuration information bits;
the default value writing module is connected with the data latch module, the data latch module is connected with the data writing module, and the data latch module is connected with the data output module.
2. The small-scale Latch unit circuit according to claim 1, wherein the first mos transistor nm1, the second mos transistor nm2, and the third mos transistor nm3 are nmos transistors.
3. The small-sized Latch unit circuit according to claim 1, wherein the data Latch module comprises a fourth mos tube pm1, a fifth mos tube nm4, a sixth mos tube pm2, a seventh mos tube pm3, an eighth mos tube nm5 and a ninth mos tube nm6, a source of the fourth mos tube pm1 is connected to the power supply voltage VDD, a drain of the fourth mos tube pm1 is connected to a drain of the fifth mos tube nm4, a source of the fifth mos tube nm4 is grounded, a gate of the fifth mos tube nm4 is connected to a gate of the fourth mos tube pm1 and then connected to the default value writing module, and a gate of the fifth mos tube 46nm 4 is connected to a gate of the fourth mos tube pm1 and then connected to the data output module 2; the source of the sixth mos tube pm2 is connected with the power supply voltage VDD, the drain of the sixth mos tube pm2 is connected with the source of the seventh mos tube pm3, the drain of the seventh mos tube pm3 is connected with the drain of the eighth mos tube nm5, the source of the eighth mos tube nm5 is connected with the drain of the ninth mos tube nm6, the source of the ninth mos tube nm6 is grounded, the gate of the sixth mos tube pm2 is connected with the gate of the ninth mos tube nm6 and then connected with the drain of the fourth mos tube pm1, the gate of the seventh mos tube pm3 is connected with the first LATCH signal LATCH, the gate of the eighth mos tube nm5 is connected with the second LATCH signal LATCH _ B, and the second LATCH signal LATCH _ B is the inverse of the first LATCH signal LATCH; and the grid electrode of the fifth mos transistor nm4 is connected with the grid electrode of the fourth mos transistor pm1 and then connected with the drain electrode of the seventh mos transistor pm3, and the grid electrode of the sixth mos transistor pm2 is connected with the grid electrode of the ninth mos transistor nm6 and then connected with the data output module.
4. The small-sized Latch unit circuit according to claim 3, wherein pmos transistor is used for the fourth mos transistor pm1, the sixth mos transistor pm2, and the seventh mos transistor pm3, and nmos transistor is used for the fifth mos transistor nm4, the eighth mos transistor nm5, and the ninth mos transistor nm 6.
5. The small-sized Latch unit circuit of claim 1, wherein the data output module comprises a tenth mos transistor pm4 and an eleventh mos transistor nm7, a source of the tenth mos transistor pm4 is connected to the power supply voltage VDD, a gate of the tenth mos transistor pm4 and a gate of the eleventh mos transistor nm7 are connected together and then connected to the data Latch module, a drain of the tenth mos transistor pm4 is connected to a drain of the eleventh mos transistor nm7, a source of the eleventh mos transistor nm7 is grounded, and a drain of the tenth mos transistor pm4 is used as a data output terminal to output data in configuration information bits.
6. The small-sized Latch unit circuit according to claim 5, wherein the tenth mos tube pm4 is a pmos tube, and the eleventh mos tube nm7 is an nmos tube.
7. The small-sized Latch unit circuit of claim 1, wherein the default value write module comprises a twelfth mos transistor pm5, a source of the twelfth mos transistor pm5 is connected to the power voltage VDD, a drain of the twelfth mos transistor pm5 is connected to the data Latch module, a gate of the twelfth mos transistor pm5 is connected to the first power-on control signal PRECHB, and a drain of the twelfth mos transistor pm5 is connected to the data write module when the default value is 1.
8. The small-scale Latch unit circuit of claim 1, wherein the default value write module comprises a thirteenth mos transistor nm8, a source of the thirteenth mos transistor nm8 is grounded, a gate of the thirteenth mos transistor nm8 is connected to the second power-on control signal DISCH, and a drain of the thirteenth mos transistor nm8 is connected to the data write module when the default value is 0.
9. A Flash chip comprising the small-sized Latch unit circuit according to any one of claims 1 to 8.
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| CN202011535598.6A CN112466372B (en) | 2020-12-23 | 2020-12-23 | Small-size Latch unit circuit and Flash chip |
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| CN202011535598.6A CN112466372B (en) | 2020-12-23 | 2020-12-23 | Small-size Latch unit circuit and Flash chip |
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| CN112466372B true CN112466372B (en) | 2021-12-21 |
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| US7206230B2 (en) * | 2005-04-01 | 2007-04-17 | Sandisk Corporation | Use of data latches in cache operations of non-volatile memories |
| KR101139133B1 (en) * | 2010-07-09 | 2012-04-30 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
| KR20170075886A (en) * | 2015-12-23 | 2017-07-04 | 에스케이하이닉스 주식회사 | Sensing control signal generation circuit and semiconductor memory device |
| US10020809B2 (en) * | 2016-09-19 | 2018-07-10 | Globalfoundries Inc. | Integrated level translator and latch for fence architecture |
| KR20180057431A (en) * | 2016-11-22 | 2018-05-30 | 삼성전자주식회사 | Nonvolatile memory device |
| CN110164498A (en) * | 2019-05-28 | 2019-08-23 | 长江存储科技有限责任公司 | A kind of nonvolatile memory and its programmed method |
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