CN112462121A - Eye pattern wave filter system and eye pattern testing method - Google Patents
Eye pattern wave filter system and eye pattern testing method Download PDFInfo
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Abstract
The invention discloses an eye pattern wave device system and an eye pattern testing method, wherein the system comprises: the device comprises an equalizer, a clock data recovery circuit and an eye pattern oscilloscope; after the input signal is regulated by the equalizer, the input clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope; the eye chart oscilloscope comprises an algorithm logic module, a first phase interpolator and a first sampler; and the algorithm logic module controls the first phase interpolator to output a clock to traverse N phases and controls the threshold voltage of the first sampler to traverse M voltage values, so that the error rate of each phase and each voltage value is tested, and the eye diagram of M x N test points is obtained. The system and the method provided by the invention are used for solving the technical problem of high signal testing cost in the prior art. A low-cost eye pattern oscilloscope system and an eye pattern testing method are provided.
Description
Technical Field
The present disclosure relates to the field of testing, and in particular, to an eye pattern oscilloscope system and an eye pattern testing method.
Background
In the field of high-speed serial interfaces, signals from a transmitter to a receiver need to pass through a package, a connector, a through hole, a circuit board copper wire and the like, the whole path is low-pass, and meanwhile, the problem of reflection is caused due to impedance discontinuity. These non-ideal factors can introduce intersymbol interference and degrade signal quality.
The quality of the current test signal mainly adopts a high-speed real-time oscilloscope, the price of the oscilloscope is higher, and meanwhile, other configuration supports such as a circuit board are also needed. And the test effect is to be improved.
Disclosure of Invention
It is an object of the present disclosure, at least in part, to provide an eye chart filter system and an eye chart testing method.
In a first aspect, an embodiment of the present disclosure provides the following technical solutions:
an eye diagram waver system, comprising:
the device comprises an equalizer, a clock data recovery circuit and an eye pattern oscilloscope;
the input signal of the eye pattern oscilloscope system is input, and is input into the clock data recovery circuit after being regulated by the equalizer; the clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope;
the eye chart oscilloscope comprises an algorithm logic module, a first phase interpolator and a first sampler;
after receiving the clock information and the input signal, the arithmetic logic module controls the first phase interpolator to output a clock to traverse N phases, and controls the threshold voltage of the first sampler to traverse M voltage values, so that the error rate of the input signal sampled by the first sampler at each phase and each voltage value is tested, and an eye diagram of M test points is obtained, wherein N and M are positive integers.
Optionally, the eye chart oscilloscope system further comprises: the external interface is connected with the arithmetic logic module and receives the eye pattern output by the arithmetic logic module; the external interface is also used for adjusting the values of N and M.
Optionally, N is 16 and M is 8.
Optionally, the eye chart oscilloscope system further comprises: and the phase-locked loop provides initial clocks for the clock recovery circuit and the eye pattern oscilloscope.
In a second aspect, there is also provided an eye diagram testing method, which is applied to the system of the first aspect, and includes:
after the equalizer adjusts the input signal, the input signal is input into the clock data recovery circuit;
the clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope;
and after receiving the clock information and the input signal, the arithmetic logic module in the eye chart oscilloscope controls an output clock of the first phase interpolator to traverse N phases and controls the threshold voltage of the first sampler to traverse M voltage values, so that the error rate of the input signal sampled by the first sampler at each phase and each voltage value is tested, and the eye charts of M test points are obtained, wherein N and M are positive integers.
Optionally, the test points in the eye pattern represent that the error rate meets the requirement for hollow dots, and the test points in the eye pattern represent that the error rate does not meet the requirement for solid dots.
Optionally, before the clock information and the input signal are input into the eye chart oscilloscope, the method further includes: the clock data recovery circuit removes jitter components that can be tracked within a portion of the loop bandwidth.
Optionally, the method further includes: setting the equalizer to a plurality of equalization coefficients, and executing the method of claim 5 under each equalization coefficient to obtain an eye diagram of a corresponding plurality of M x N test points; and determining a target equalization coefficient of the equalizer according to the eye pattern of the M x N test points.
Optionally, the determining a target equalization coefficient of the equalizer according to the eye pattern of the M × N test points includes: and determining the equalization coefficient corresponding to the eye pattern with the maximum eye opening degree of the eye patterns of the M x N test points as the target equalization coefficient.
Optionally, the method further includes: setting the dithering frequency to a plurality of dithering frequency values; maintaining each of the dither frequency values and gradually increasing the dither amplitude of the input signal;
recording the exceeding jitter amplitude at the moment until the eye chart oscilloscope detects that the error rate of the input signal does not meet the preset requirement; and obtaining a jitter tolerance curve representing a receiver connected with the eye pattern oscilloscope according to the superscript jitter amplitude values corresponding to the jitter frequency values.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
according to the eye pattern oscilloscope system and the eye pattern testing method, an input signal of the eye pattern oscilloscope system is set and is input into the clock data recovery circuit after being adjusted by the equalizer; the clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope; and after receiving the clock information and the input signal, the algorithm logic module controls the first phase interpolator to output a clock to traverse N phases and controls the threshold voltage of the first sampler to traverse M voltage values, so that the error rate of the input signal sampled by the first sampler at each phase and each voltage value is tested, and an eye diagram of M test points is obtained. On one hand, the output of the clock data recovery circuit contains clock information, and the information is input into the eye pattern oscilloscope so as to be used for removing jitter components which can be tracked in part of loop bandwidth when the eye pattern is tested, thereby obtaining more real eye pattern information. On the other hand, the algorithm logic module is arranged to perform traversal to obtain multipoint distribution eye diagrams with different phases and different threshold voltages, so that the signal quality is more comprehensively represented. Expensive high-speed real-time oscilloscopes and error code instruments are not needed, the requirement on the test environment is low, and therefore the cost is low and the flexibility is high. Compared with a real-time oscilloscope, the invention is more economical, convenient and flexible and has higher precision.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only examples of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of an eye oscilloscope system according to one or more embodiments of the present disclosure;
FIG. 2 is a flow diagram of an eye diagram testing method according to one or more embodiments of the present disclosure;
fig. 3 is a schematic eye diagram in accordance with one or more embodiments of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to specific embodiments, and it should be understood that the specific features in the examples and examples of the present disclosure are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application, and the technical features in the examples and examples of the present application may be combined with each other without conflict.
According to an aspect of the present disclosure, there is provided an eye diagram filter system, as shown in fig. 1, comprising:
the device comprises an equalizer 1, a clock data recovery circuit 2 and an eye pattern oscilloscope 3;
wherein, the input signal of the eye pattern oscilloscope system is input, and is input into the clock data recovery circuit 2 after being adjusted by the equalizer 1; the clock data recovery circuit 2 recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope 3;
the eye diagram oscilloscope 3 comprises an arithmetic logic module 31, a first phase interpolator 32 and a first sampler 33;
after receiving the clock information and the input signal, the arithmetic logic module 31 controls the first phase interpolator 32 to output a clock to traverse N phases, and controls the threshold voltage of the first sampler 33 to traverse M voltage values, so as to test the error rate of the input signal sampled by the first sampler 33 at each phase and each voltage value, and obtain eye diagrams of M × N test points, where N and M are both positive integers.
In a specific implementation process, the eye diagram oscilloscope system is a system on a chip, and is used for testing the quality of an eye diagram corresponding to an input signal of a transmitter after passing through a channel, and also can be used for testing the overall performance of a receiver (by adding non-ideal factors such as jitter and voltage noise to input data to obtain a pressure eye diagram, testing the error rate of the receiver, and obtaining a jitter tolerance curve of the receiver), and can also adjust the equalizer coefficient through the feedback of an eye diagram test result to improve the error rate performance of the receiver. The on-chip eye pattern oscilloscope is suitable for a wide data rate range, the bandwidth of a clock data recovery circuit can be adjusted, and the on-chip eye pattern oscilloscope is compatible with various serial protocols. The arithmetic logic module 31 may be configured to adjust a phase and a threshold voltage of data sampling, test an error rate, record eye diagram information, and adjust equalizer coefficients. The first phase interpolator 32 performs phase interpolation on the output clock of the phase-locked loop, and preferably, 16 equal-divided sampling clocks can be obtained through interpolation. The first sampler 33 samples data, and the threshold voltage of the decision can be adjusted. The eye pattern oscilloscope system utilizes the clock information of the clock data recovery circuit 2, when data are sampled, the sampling clock of the first phase interpolator 32 is transversely adjusted, the decision threshold voltage of the first sampler 33 is longitudinally adjusted, the whole eye pattern is scanned, the error rate of each point is recorded, all points meeting the requirement of the error rate are counted, the eye pattern of input data is constructed, eye opening information is obtained, the performance of a transmitter and a receiver can be determined according to the eye opening information, and the equalization coefficient of an equalizer can be adjusted.
The eye diagram oscilloscope system can be independent of the receiver system, and is operated when testing the eye diagram or finding the best equalizer coefficient, and can be powered off under other conditions to reduce power consumption.
The eye chart oscilloscope system further comprises: and the phase-locked loop provides initial clocks for the clock recovery circuit 2 and the eye pattern oscilloscope 3.
Further, the jitter that part of the clock data loop can track can be removed through the clock information of the clock data recovery circuit 2, which is closer to the data eye pattern seen when the receiver samples in practical application, and meanwhile, the bandwidth of the clock data recovery loop can be adjusted. Of course, when the eye pattern of the input signal is tested, clock data recovery may not be adopted, and the complete jitter information of the input data is kept in the eye pattern test result. I.e. clock recovery with or without incoming data can be achieved by whether the use of clock recovery information in the clock data recovery circuit 2 is selected.
The eye chart oscilloscope system, further comprising: the external interface is connected with the arithmetic logic module and receives the eye pattern output by the arithmetic logic module; the external interface is also used for adjusting the values of N and M.
Preferably, N is 16 and M is 8. During sampling, a clock with 16 phases is scanned transversely, 8 sampling threshold voltages are scanned longitudinally, whether eyes of each sampling point are opened or not is judged through the error rate, the whole two-dimensional eye pattern lattice is traversed, and eye pattern information is constructed. In which the 16-phase horizontal clock at the time of sampling is generated by the first phase interpolator 32, which functions as the phase interpolator in the clock data recovery circuit 2, and the number of interpolated phases can also be configured to 32 or 64 through the external interface, which requires a trade-off between test time and test accuracy. The 8 sampling threshold voltages during sampling are generated by the first sampler 33, the differential threshold voltage of the sampler itself may not be 0 due to the non-ideal factors of circuit design and processing, the mismatch can be eliminated by the sampler mismatch correction circuit before the eye diagram test, and then the test is performed, the number of the sampling threshold voltages can be configured to 32, 64 or 128 through an external interface, which requires a trade-off between test time and test precision.
According to an aspect of the present disclosure, there is also provided an eye pattern testing method, which is applied to the eye pattern oscilloscope system, as shown in fig. 2, and includes:
step S201, after the equalizer 1 adjusts the input signal, the input signal is input to the clock data recovery circuit 2;
step S202, the clock data recovery circuit 2 recovers the clock information of the input signal, and inputs the clock information and the input signal to the eye chart oscilloscope 3;
step S203, after receiving the clock information and the input signal, the arithmetic logic module in the eye chart oscilloscope 3 controls the output clock of the first phase interpolator to traverse N phases, and controls the threshold voltage of the first sampler to traverse M voltage values, so as to test the error rate of the input signal sampled by the first sampler at each phase and each voltage value, and obtain eye charts of M × N test points, where N and M are both positive integers.
Preferably, the test points in the eye pattern represent that the error rate meets the requirement for hollow dots, and the test points in the eye pattern represent that the error rate does not meet the requirement for solid dots. Preferably, the bit error rate is set to be less than 10-12Other values may be set to meet the requirements, and are not limited herein.
Specifically, when the system is used to determine the transmitter performance, or to determine whether the equalization coefficient set by the equalizer 1 is reasonable, the following is used: and testing the eye pattern of the output signal of the transmitter, if the transmitter and the on-chip eye pattern oscilloscope system are on the same chip, signal connection can be performed in a chip, and certainly, signal connection can also be performed on an off-chip circuit board through a channel, which is not limited herein. After a signal of a transmitter enters a receiver, the signal quality is improved through an equalizer 1, and then the signal enters a clock data recovery circuit 2, and a proper clock is recovered to carry out sampling in the center of an eye pattern. The output of the digital filter in the clock data recovery circuit 2 contains clock information, and the information is simultaneously input into the eye pattern oscilloscope so as to be used for clock recovery when testing the eye pattern, remove jitter components which can be tracked in part of loop bandwidth and obtain more real eye pattern information. After the clock recovery information of the filter is input to the arithmetic logic block 31, the arithmetic logic block 31 performs a mathematical operation, and then controls the first phase interpolator 32 to make the phase of the output clock thereof be at the phase 1. The threshold voltage of the first sampler 33 is adjusted simultaneously, traversing all 8 threshold voltage values. The arithmetic logic module 31 receives the data output by the first sampler 33, and at the same time, detects, records the number of bit errors, and calculates the bit error rate. And counting the bit error rate at each voltage while traversing all the voltage thresholds. And then adjusting the output clock of the phase interpolator to the 2 nd phase, continuously traversing 8 threshold voltages, and recording the error rate under each voltage. Repeating the previous operations until all 16 phases are traversed, thus testing the error rates of all two-dimensional lattices in the eye diagram to obtain the eye diagram shown in fig. 3, wherein the points meeting the error rate requirement are hollow circles, and the points not meeting the error rate requirement are solid circles, thus obtaining the eye diagram of the input signal, the middle hollow circle pattern is an eye opening, and the eye opening and the eye width of the eye diagram can be compared with corresponding eye diagram templates, so that the performance of the transmitter can be determined, or whether the equalization coefficient set by the equalizer 1 is reasonable or not can be judged.
Specifically, when the system is used for adaptively adjusting the equalization coefficient of the equalizer, the following method is adopted: setting the equalizer as a plurality of equalization coefficients, executing steps S201-S203 under each equalization coefficient to obtain eye diagrams of a plurality of corresponding M x N test points, and determining a target equalization coefficient of the equalizer according to the eye diagrams of the plurality of M x N test points. Adjusting different equalization coefficients, testing the eye opening and the eye width of the eye pattern under the coefficients, and determining the equalization coefficient corresponding to the eye pattern with the maximum eye opening degree of the eye patterns of the M × N test points as the target equalization coefficient.
In the implementation process, the eye pattern with the maximum eye openness can be the eye pattern with the maximum product of the eye height and the eye width, and can also be the eye pattern with the maximum product of the eye height and the eye width. The corresponding determined target equalization coefficient is the optimal coefficient adapted to the current channel environment, and the eye pattern oscilloscope can be closed to reduce power consumption after the equalization coefficient of the equalizer 1 is set as the target equalization coefficient.
Specifically, when the system is used to test receiver performance, the following is used: setting the jitter frequency as a plurality of jitter frequency values, keeping each jitter frequency value and gradually increasing the jitter amplitude of the input signal until the eye chart oscilloscope 3 detects that the error rate of the input signal does not meet the preset requirement, and recording the exceeding jitter amplitude at the moment. And obtaining a jitter tolerance curve representing a receiver connected with the eye pattern oscilloscope according to the superscript jitter amplitude values corresponding to the jitter frequency values. Namely, the function of testing the error rate of the system is utilized, and the phase and the threshold voltage of sampling are not adjusted. And gradually increasing the jitter amplitude of the input signal by fixing the jitter frequency until the receiver does not meet the requirement of the error rate, and recording the amplitude of the jitter value. The dither frequency is changed and the previous operation is continued. This results in a jitter tolerance curve for the receiver.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
according to the eye pattern oscilloscope system and the eye pattern testing method provided by the embodiment of the application, on one hand, the output of the clock data recovery circuit contains clock information, and the information is input into the eye pattern oscilloscope so as to be used for adopting the clock information when testing the eye pattern, so that jitter components which can be tracked in part of loop bandwidth are removed, and more real eye pattern information is obtained. On the other hand, the algorithm logic module is arranged to perform traversal to obtain multipoint distribution eye diagrams with different phases and different threshold voltages, so that the signal quality is more comprehensively represented. Expensive high-speed real-time oscilloscopes and error code instruments are not needed, the requirement on the test environment is low, and therefore the cost is low and the flexibility is high. Compared with a real-time oscilloscope, the invention is more economical, convenient and flexible and has higher precision.
In the above description, technical details of patterning, designing, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
It will be apparent to those skilled in the art that various changes and modifications can be made in the present disclosure without departing from the spirit and scope of the disclosure. Thus, if such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.
Claims (10)
1. An eye diagram filter system, comprising:
the device comprises an equalizer, a clock data recovery circuit and an eye pattern oscilloscope;
the input signal of the eye pattern oscilloscope system is input, and is input into the clock data recovery circuit after being regulated by the equalizer; the clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope;
the eye chart oscilloscope comprises an algorithm logic module, a first phase interpolator and a first sampler;
after receiving the clock information and the input signal, the arithmetic logic module controls the first phase interpolator to output a clock to traverse N phases, and controls the threshold voltage of the first sampler to traverse M voltage values, so that the error rate of the input signal sampled by the first sampler at each phase and each voltage value is tested, and an eye diagram of M test points is obtained, wherein N and M are positive integers.
2. The eye oscilloscope system according to claim 1, further comprising:
the external interface is connected with the arithmetic logic module and receives the eye pattern output by the arithmetic logic module; the external interface is also used for adjusting the values of N and M.
3. The eye oscilloscope system according to claim 1, wherein N is 16 and M is 8.
4. The eye oscilloscope system according to claim 1, further comprising:
and the phase-locked loop provides initial clocks for the clock recovery circuit and the eye pattern oscilloscope.
5. An eye diagram testing method, applied to the system of any one of claims 1-4, comprising:
after the equalizer adjusts the input signal, the input signal is input into the clock data recovery circuit;
the clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye pattern oscilloscope;
and after receiving the clock information and the input signal, the arithmetic logic module in the eye chart oscilloscope controls an output clock of the first phase interpolator to traverse N phases and controls the threshold voltage of the first sampler to traverse M voltage values, so that the error rate of the input signal sampled by the first sampler at each phase and each voltage value is tested, and the eye charts of M test points are obtained, wherein N and M are positive integers.
6. The method of claim 5, wherein the test points in the eye pattern are open dots to indicate that the bit error rate is satisfactory, and wherein the test points in the eye pattern are filled dots to indicate that the bit error rate is unsatisfactory.
7. The method of claim 5, prior to inputting the clock information and the input signal into the eye oscilloscope, further comprising:
the clock data recovery circuit removes jitter components that can be tracked within a portion of the loop bandwidth.
8. The method of claim 5, further comprising:
setting the equalizer to a plurality of equalization coefficients, and executing the method of claim 5 under each equalization coefficient to obtain an eye diagram of a corresponding plurality of M x N test points;
and determining a target equalization coefficient of the equalizer according to the eye pattern of the M x N test points.
9. The method of claim 8, wherein determining the target equalization coefficient for the equalizer based on the eye pattern of the plurality of M x N test points comprises:
and determining the equalization coefficient corresponding to the eye pattern with the maximum eye opening degree of the eye patterns of the M x N test points as the target equalization coefficient.
10. The method of claim 5, further comprising:
setting the dithering frequency to a plurality of dithering frequency values;
maintaining each of the dither frequency values and gradually increasing the dither amplitude of the input signal;
recording the exceeding jitter amplitude at the moment until the eye chart oscilloscope detects that the error rate of the input signal does not meet the preset requirement;
and obtaining a jitter tolerance curve representing a receiver connected with the eye pattern oscilloscope according to the superscript jitter amplitude values corresponding to the jitter frequency values.
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| CN202011092482.XA CN112462121B (en) | 2020-10-13 | 2020-10-13 | Eye pattern wave filter system and eye pattern testing method |
| PCT/CN2020/140579 WO2022077775A1 (en) | 2020-10-13 | 2020-12-29 | Eye diagram oscilloscope system and an eye diagram testing method |
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