CN112422771B

CN112422771B - Resource resetting system

Info

Publication number: CN112422771B
Application number: CN201910774950.2A
Authority: CN
Inventors: 魏巍; 殷建东
Original assignee: Suzhou HYC Technology Co Ltd
Current assignee: Suzhou HYC Technology Co Ltd
Priority date: 2019-08-21
Filing date: 2019-08-21
Publication date: 2023-01-13
Anticipated expiration: 2039-08-21
Also published as: CN112422771A

Abstract

The invention discloses a resource resetting system, which comprises: the system comprises a first control module, a second control module and a resource resetting module, wherein the second control module is respectively connected with the first control module and the resource resetting module; the first control module is used for initiating a resource resetting request; the second control module is configured to generate a resource resetting signaling according to the resource resetting request, and send the resource resetting signaling to the resource resetting module according to a preset message structure, where the preset message structure includes a physical layer channel number indication field and a link state parameter indication field; the resource resetting module is used for resetting resources according to the resource resetting signaling and generating first feedback information aiming at the resource resetting signaling. The technical scheme indicates the resource resetting according to the preset message structure, standardizes the signaling interaction among all modules of the system, and improves the signaling interaction efficiency, thereby improving the resource resetting efficiency and the link performance.

Description

Resource resetting system

Technical Field

The embodiment of the invention relates to the technical field of data communication, in particular to a resource resetting system.

Background

Video or image processing systems are increasingly used in a wide variety of fields, such as device inspection/detection, security monitoring, industrial vision, and artificial intelligence. With the increasing resolution of video or image processing systems, the number of lanes (Lane) used in a terminal device for video display increases, and the Link Rate (LR) on each Lane also increases, which makes higher and higher requirements on the real-time performance, coordination, and the like of hardware platforms of the video or image processing systems, and the video or image processing systems need to rapidly allocate or reset resources according to the number of lanes and the Link Rate used in the systems, for example, adjust the grouping of bit transceivers and lanes, and reset Link state parameters.

The existing resource resetting system lacks a clear and efficient message structure to define a specific process of signaling interaction, especially for the conditions of different Lane numbers and link rates, system resources cannot be effectively grouped and the mapping relation between the system resources and a physical layer cannot be determined, and reasonable organizational structures and interaction specifications are lacked among modules, so that the time delay of each link is higher, the resource resetting efficiency is low, and the link performance is poorer.

Disclosure of Invention

The invention provides a resource resetting system, which is used for improving the efficiency of resource resetting and the performance of a link.

An embodiment of the present invention provides a resource resetting system, including: the system comprises a first control module, a second control module and a resource resetting module, wherein the second control module is respectively connected with the first control module and the resource resetting module;

the first control module is used for initiating a resource resetting request;

the second control module is used for generating a resource resetting signaling according to the resource resetting request and sending the resource resetting signaling to the resource resetting module according to a preset message structure, wherein the preset message structure comprises a physical layer channel number indication field and a link state parameter indication field;

the resource resetting module is used for resetting resources according to the resource resetting signaling and generating first feedback information aiming at the resource resetting signaling.

Further, the resource resetting module includes:

the transceiver resetting submodule is used for determining the matching relation between the high-speed bit transceiver and the channel output port differential signal according to the maximum channel number indicated by the physical layer channel number indication field;

and the link state parameter resetting module is used for resetting link state parameters according to the link state parameter indication field, wherein the link state parameters comprise link rate, link state cache, frame polarity, voltage swing amplitude, phase-locked loop state parameters, sampling point front interference and sampling point rear interference.

Further, the resource resetting module further includes:

and the phase-locked loop resetting submodule is used for determining the phase-locked loop type of the channel output differential pair port according to the maximum channel number indicated by the physical layer channel number indication field and the link rate indicated by the link state parameter indication field and resetting the phase-locked loop according to the channel serial number.

Further, the preset message structure further includes: a register map indication field;

the resource resetting module further comprises:

and the mapping submodule is used for grouping the channels according to the maximum channel number indicated by the physical layer channel number indication field and the link rate indicated by the link state parameter indication field, and establishing the mapping relation between the physical layer register and the channel grouping according to the register mapping indication field.

Further, the preset message structure further includes: a physical layer channel clock distribution indication field for indicating the distribution mode of the channel clock, wherein the distribution mode comprises external control and automatic distribution.

Further, the resource resetting module further includes:

and the clock distribution submodule is used for adjusting the clock of the channel output port in the physical layer according to the distribution mode indicated by the physical layer channel clock distribution indication field.

Further, the resource resetting module further includes:

a status information reading submodule, configured to read status information of a physical layer, where the status information includes: the method comprises the steps of receiving and sending reconfiguration information, phase-locked loop resetting information, mapping information of a physical layer register and a channel packet and clock distribution information;

and the feedback information generation submodule is used for generating first feedback information according to the state information.

Further, the preset message structure further includes: a master-slave module definition field and a feedback field;

the master-slave module definition field is used for defining a master module and a slave module in the resource resetting module;

the feedback field is used for defining a module status after the resource resetting signaling interaction is completed, and the module status includes an Acknowledgement (ACK) status and a non-Acknowledgement (NACK) status.

Further, the preset message structure further includes: checking the field;

and the check field is used for checking the resource resetting signaling according to a preset specification and indicating the interaction failure of the resource resetting signaling when the checking fails.

Further, the master module is configured to receive a resource resetting signaling sent by the second control module according to a preset message structure, where the resource resetting signaling is forwarded to the slave module through the master module;

the slave module is used for resetting resources according to the resource resetting signaling, generating first feedback information aiming at the resource resetting signaling and sending the first feedback information to the master module.

An embodiment of the present invention provides a resource resetting system, including: the system comprises a first control module, a second control module and a resource resetting module, wherein the second control module is respectively connected with the first control module and the resource resetting module; the first control module is used for initiating a resource resetting request; the second control module is configured to generate a resource resetting signaling according to the resource resetting request, and send the resource resetting signaling to the resource resetting module according to a preset message structure, where the preset message structure includes a physical layer channel number indication field and a physical layer link rate indication field; the resource resetting module is used for resetting resources according to the resource resetting signaling and generating first feedback information aiming at the resource resetting signaling. The technical scheme indicates resource resetting according to the preset message structure, standardizes signaling interaction among modules of the system, and improves signaling interaction efficiency, thereby improving resource resetting efficiency and link performance.

Drawings

Fig. 1 is a schematic structural diagram of a resource resetting system according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a resource resetting system according to a second embodiment of the present invention;

fig. 3 is a schematic diagram of signaling interaction of a resource resetting system according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a video processing system for resource resetting according to a second embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Example one

Fig. 1 is a schematic structural diagram of a resource resetting system according to an embodiment of the present invention. The present embodiment is applicable to a video or image processing system, and is suitable for a situation where resources are quickly reset according to the number of lanes and link status parameters used in the system when an Intellectual Property (IP) kernel parameter is changed, a bit width of a video stream, a display mode, a control register feature bit, and the like are changed.

Specifically, as shown in fig. 1, the system includes: the system comprises a first control module 10, a second control module 20 and a resource resetting module 30, wherein the second control module 20 is respectively connected with the first control module 10 and the resource resetting module 30; the first control module 10 is configured to initiate a resource reset request; the second control module 20 is configured to send a resource resetting signaling generated according to the resource resetting request to the resource resetting module 30 according to a preset message structure; the resource resetting module 30 is configured to reset resources according to the resource resetting signaling, and generate the first feedback information for the resource resetting signaling, where the preset message structure includes a physical layer channel number indication field and a link state parameter indication field.

The number of Lanes indication field is used to indicate the number of Lanes that need to be supported after resource reset, for example, N Lanes, where N is a positive integer and represents that the number of Lanes that can be supported by the physical layer is N. In the process of resource resetting, resetting is carried out according to the supported maximum Lane number, under the condition, all Lanes smaller than the supported maximum Lane number can be compatible, so that the hardware platform can support the total Lane number, the number and the distribution method of the high-speed bit transceivers (GTX) used in the system are determined, and the reconfiguration is carried out to adapt to the Lane number.

The link state parameter indication field is used to indicate a link state parameter, and the link state parameter may include link state buffer, link rate configuration, frame polarity, voltage Swing (Voltage Swing), phase Locked Loop (PLL) state detection and reset, pre-sampling point interference (presursor), post-sampling point interference (POSTCURSOR), and the like.

Further, the resource resetting module 30 determines the type of phase-locked loop, such as Quad PLL, CPLL, etc., used by the Lane output differential pair port according to the link rate. The method for determining the type of the phase-locked loop can be automatically allocated for the system or specified by a user. On the basis, the resource resetting module 30 resets the PLL according to the Lane serial number and returns status information, and the system determines the operating status of the PLL according to the returned status information.

Further, the resource resetting module 30 determines the type or number of link state parameters in the Physical Layer (PHY) through the Lane number supported in the video image processing system, for example, link state buffer, link rate configuration, frame polarity, voltage swing, PLL (state detection and reset, interference before sampling point, interference after sampling point, etc., thereby realizing the allocation and reset of Lane number adaptive and extensible high-speed bit transceiver resources and drivers used in the video image processing system, clock resources, link state detection and reset, interference before sampling point, interference after sampling point, physical Layer reset state bits, etc.

Further, the resource resetting module 30 determines the physical layer reset status bit according to the Lane number supported in the video image processing system, so as to determine the actual status information of the physical layer according to the maximum Lane number actually used in the system, and complete the status information transmission and confirmation between the system and the physical layer through an Auxiliary transport mechanism (Auxiliary transport) and the like.

Further, the resource resetting module 30 includes at least one of: the device comprises an external storage module, a quick storage module, a peripheral module and a video interface physical layer implementation module. The external storage module is used for storing original data streams of videos or images needing to be displayed in the system. For example, the external storage module may employ a Flash memory (e.g., nand Flash), a Solid State Drive (SSD), or other storage media. The fast storage module is a module for temporarily storing Data in order to further reduce the latency when a large amount of Data processing and low round trip delay (latency) signaling are required inside the second control module 20, and may use a fast and low latency Physical device, such as a Double Data Rate SDRAM (DDR), etc. the peripheral module may be a General-purpose input/output (GPIO), a Universal Asynchronous Receiver/Transmitter (UART), a Universal Serial Bus (USB), a network Port, etc. the video Interface Physical Layer implementation module is used to drive a Physical Layer implementation of a Display module, such as a Physical Layer (PHY) of a transceiver/Receiver (TX/RX) Port of a Display Interface (Display Interface, DP), and a Physical Layer (PHY) of a Mobile transceiver/Receiver (MIPI) Port of a Mobile Interface (mipd, etc.

Further, the first control module 10 is an embedded control module or an FPGA module; correspondingly, the second control module 20 is an FPGA module or an embedded control module.

Specifically, the embedded control module may adopt any embedded chip and system, and is used for resource resetting requests, such as requesting to read/write register data, requesting to enable/close a video display unit or module, requesting to control a peripheral device or requesting to modify parameter settings of the video display module, and the like. The FPGA module is used for implementing or executing operations which need a large amount of data processing and low round-trip delay (latency) such as storage control, peripheral control, video interface IP core implementation and the like.

An embodiment of the present invention provides a resource resetting system, including: the system comprises a first control module, a second control module and a resource resetting module, wherein the first control module is used for initiating a resource resetting request; and the second control module generates a resource resetting signaling according to the resource resetting request, sends the resource resetting signaling to the resource resetting module according to a preset message structure, resets the resource by the resource resetting module and generates first feedback information. By carrying out signaling interaction according to a preset message structure, the interaction structure and the specification of each module are defined, and the signaling interaction efficiency is improved, so that the resource resetting efficiency and the link performance are improved according to the Lane number and the link state parameters used in the system.

Example two

The present embodiment is optimized based on the above embodiments, and the interaction process between the second control module 20 and the resource resetting module 30 is specifically described. The present embodiment is applicable to a Video image processing system based on a Field Programmable Gate Array (FPGA) and an embedded system, and particularly relates to a Video image processing system with a digital Video Interface standard (DP) of Video Electronics Standards Association (VESA), a Mobile Industry Processor Interface standard (MIPI), and a High Definition Multimedia Interface standard (HDMI). Technical details that are not elaborated in this embodiment may be referred to any of the embodiments described above.

Fig. 2 is a schematic structural diagram of a resource resetting system according to a second embodiment of the present invention. As shown in fig. 2, the resource resetting module 30 includes a transceiver resetting submodule 31, configured to determine a matching relationship between the high-speed bit transceiver and the lane output port differential signal according to the maximum lane number indicated by the physical layer lane number indication field; the link state parameter resetting module 32 is configured to reset link state parameters according to the link state parameter indication field, where the link state parameters include a link rate, a link state buffer, a frame polarity, a voltage swing, a phase-locked loop state parameter, a pre-sampling point interference, and a post-sampling point interference.

Specifically, the transceiver resetting sub-module 31 determines the number and the allocation method of the high-speed bit transceivers used in the system, and performs the reconfiguration to adapt to Lane number; the Lane output ports are typically very high rate differential pair signals that match the link rate, and during resource reset, all Lane output port differential pair signals must be matched to the high speed bit transceiver to ensure the link performance of Lane output signals. The link state parameter reset module 32 is used to determine the link state parameters in the physical layer.

Further, the resource resetting module 30 further includes: a phase-locked loop resetting sub-module 33, configured to determine, according to the maximum number of channels indicated by the physical layer Channel number indication field and the link rate indicated by the link state parameter indication field, the phase-locked loop type of the Channel output differential pair port, for example, QPLL (Quad PLL), CPLL (Channel PLL), and the like, where the determination method may be automatically allocated by a system or manually specified; and resetting the phase-locked loop according to the channel serial number, resetting the PLL according to the Lane serial number and returning state information, and determining the working state of the PLL by the system according to the returned state information.

Further, the preset message structure further includes: and the register mapping indication field is used for indicating that corresponding registers are distributed to all the state parameters to complete register mapping between the system and the physical layer, meanwhile, the system can complete reassignment of each link state parameter by configuring the corresponding registers, and the physical layer resets the corresponding link state parameters by reading the corresponding link state parameter registers to complete modification of the link state parameters.

Further, the resource resetting module further includes: and the mapping submodule 34 is configured to group channels according to the maximum number of channels indicated by the physical layer channel number indication field and the link rate indicated by the link state parameter indication field, and establish a mapping relationship between a physical layer register and a channel group according to the register mapping indication field. Illustratively, a plurality of lanes are used as one group, and the group is used as a basic unit of mapping, so that resources in the system, particularly register resources of a physical layer, are saved. If the grouping mode is adopted, lane grouping information confirmation is needed between the system and the physical layer. And according to the Lane number and the determined link state parameters, completing the mapping of the state register between the system and the physical layer.

Further, the preset message structure further includes: and the physical layer channel clock distribution indication field is used for indicating the distribution mode of the channel clock, and the distribution mode comprises external control and automatic distribution.

Further, the resource resetting module 30 further includes: and the clock distribution submodule 35 is configured to adjust the clock of the channel output port in the physical layer according to the distribution manner indicated by the physical layer channel clock distribution indication field.

For example, the system adjusts the clock used by a Lane output port in the physical layer according to the determined type of the high-speed bit transceiver to be used, and the adjustment method includes: external control and automatic dispensing. The automatic distribution means that the system automatically adjusts the distribution and routing of the output ports of the clocks according to the conditions of layout and wiring, and the mode has simple principle and easy operation, but is not suitable for processing the complicated clock distribution condition; the external control refers to adjusting the distribution of clock ports according to the analysis of manual clock layout and wiring in the system, and the mode can be freely distributed to different regions for adjusting bit transceivers according to the condition of a system hardware platform, for example, the mode is distributed to a south bridge region or a north bridge region, and the like, and the mode needs to prejudge the clock wiring and the complexity degree in the system

Further, the resource resetting module 30 further includes: a status information reading submodule 36, configured to read status information of the physical layer, where the status information includes: the method comprises the following steps of receiving and sending reconfiguration information, phase-locked loop reset information, mapping information of a physical layer register and a channel group and clock distribution information; and a feedback information generating submodule 37, configured to generate first feedback information according to the state information.

Specifically, the Lane number supported in the video image processing system is determined, the reset state bit of the physical layer is determined, the actual state information of the physical layer is determined according to the maximum Lane number actually used in the system, and the state information transmission and confirmation between the system and the physical layer are completed through an AUX mechanism, for example. Wherein, for the transmission and confirmation of the state information, the method comprises the following steps: confirming the reconstruction information of the high-speed bit transceiver and a transceiver matched with Lane and feeding back; confirming mapping information of each Lane (or Lane grouping) of the physical layer and feeding back, and reading the mapping information in a corresponding register through AUX to confirm the working state of the physical Lane; confirming the distribution information of the clock resources and the reset information of the PLL resources and feeding back, and reading the corresponding mapping register information through the AUX to confirm that the clock and the PLL resources are distributed to the correct positions. In this embodiment, the number of link state parameters is determined, and corresponding registers are allocated to all the parameters, so as to complete register mapping between the system and the physical layer, meanwhile, the system can complete re-assignment of each link state parameter by configuring the corresponding registers, and complete modification of the link state parameters by reading the corresponding link state parameter registers and resetting the corresponding link state parameters, so as to implement resource resetting. And generating first feedback information according to the read state information of the physical layer.

Further, the preset message structure further includes: the master-slave module defines fields and feedback fields.

Specifically, the master-slave module definition field is used to define the master and slave modules in resource resetting module 30. The master module and the slave module are defined according to the initiator and the receiver of the command, and the master-slave relationship between the modules corresponding to different signaling interaction processes may be different. For example, the embedded module may initiate a resource reset signaling as a master module, and the FPGA module receives the signaling as a slave module and executes the signaling; the FPGA module may also serve as a master module to initiate a resource reset signaling to the embedded module, which is a slave module at this time. For another example, the resource resetting signaling of the second control module 20 is forwarded by the master module in the resource resetting module 30 to the slave module, the slave module completes resource resetting and feeds back to the master module, and the master module feeds back to the second control module 20. In the above example, the resource resetting signaling and the first feedback information are transmitted according to a master-slave structure, but not in a step-by-step transmission, and each group of modules having a master-slave relationship performs hierarchical forwarding and interaction of signaling in respective links, so that the organization structure of the system is standardized, and the reliability and efficiency of interaction are improved.

The feedback field is used for defining the module state after the resource resetting signaling interaction is completed, wherein the module state comprises an ACK state and a NACK state, and the confirmation operation of the signaling interaction is completed.

Further, the preset message structure further comprises a check field; the check field is used for checking the resource resetting signaling according to a preset specification and indicating the interaction failure of the resource resetting signaling when the checking fails, so that the interactive signaling and message structure are checked under the condition that the quality of a signaling transmission channel cannot be ensured, and the quality of the transmitted signaling and message structure is ensured. Communication specifications are established through interaction among the modules through the preset message structure, and resource resetting can be realized only under the condition that interactive signaling conforms to the preset specifications.

Further, the master module is configured to receive a resource resetting signaling sent by the second control module according to a preset message structure, where the resource resetting signaling is forwarded to the slave module through the master module; the slave module is used for resetting the resource according to the resource resetting signaling, generating first feedback information aiming at the resource resetting signaling and sending the first feedback information to the master module.

On the basis of the foregoing embodiment, the second control module 20 is further configured to send the initialization signaling to the master module in the first control module 10 and the resource resetting module 30 before receiving the resource resetting request, so that the master module forwards the initialization signaling to the slave module to initialize each module; the second control module 20 is further configured to receive second feedback information of the master module of the resource resetting module 30, where the second feedback information is obtained by the master module through the slave module, and the second feedback information is used to indicate that the slave module is initialized. The master module and the slave module are determined according to the master-slave module definition field in the initialization signaling. The initialization signaling is transmitted layer by layer according to a master-slave relationship. After all the slave modules are initialized, the first feedback information is fed back to the master module until the second control module 20 receives the second feedback information.

Fig. 3 is a schematic diagram of signaling interaction of a resource resetting system according to a second embodiment of the present invention. As shown in fig. 3, the signaling interaction process specifically includes:

s1, the FPGA module sends the initialization signaling to the embedded control module.

Specifically, the FPGA module determines a master-slave module definition field according to a hardware condition of video or image processing, where the field is compatible with all modules and can uniquely identify each module; and determining a physical layer channel number indication field, a physical layer link state parameter indication field, a physical layer channel clock distribution indication field and a feedback field according to the physical process of resource resetting. Optionally, the method further includes determining a signaling checking mechanism and determining a checking field, when the master/slave module sends/receives the signaling, first determining whether the signaling to be interacted meets the requirement according to the signaling checking mechanism, and if so, indicating that the signaling transmission is correct; otherwise, indicating that the signaling transmission fails, a predefined retransmission or signaling feedback mechanism is started.

And S2, the FPGA module sends the initialization signaling to a main module in the resource resetting module 30.

It should be noted that the FPGA module is the second control module 20, the embedded control module is the first control module 10, and S1 and S2 are preferably performed synchronously.

And S3, the master module forwards the initialization signaling to the slave module.

And S4, the slave module finishes preparation and feeds back second feedback information to the master module.

And S5, the main module feeds back second feedback information to the FPGA module.

Specifically, the second feedback information is used to indicate that the slave module has already been prepared according to the initialization signaling, and can identify the signaling of the preset message structure sent by the corresponding master module in the subsequent communication process.

And S6, the embedded control module initiates a resource resetting request to the FPGA module.

S7, the FPGA module sends a resource resetting signaling generated based on the resource resetting request to the main module,

and S8, the master module forwards the resource resetting signaling to the slave module.

And S9, resetting the resource by the slave module and feeding back the first feedback information to the master module.

S10, the main module feeds back the first feedback information to the second control module 20.

Specifically, the master module receives and confirms the signaling feedback field, and performs, for example, retransmission, reset or other operations preset by the system according to the information in the signaling feedback field, and feeds back the first feedback information to the second control module 20, so as to indicate the implementation of resource reset.

Further, the main module feeds back the resource resetting implementation condition to the FPGA module through the first feedback information, and after receiving the first feedback information, the FPGA module may implement a process preset by the system, such as retransmission, retry, waiting, and the like, so as to complete a request initiated by the embedded control module in the current interaction process as much as possible, thereby improving the implementation efficiency of each signaling interaction process.

And S11, the FPGA module feeds back a resource resetting result to the embedded control module.

Specifically, each time the first control module 10 initiates a request, the second control module 20 will respond, and will try to complete signaling interaction several times until the request is successful. And adopting preset strategies including retransmission, retry, waiting and the like in the process of the attempt. If all the preset strategies fail, the information of interaction failure is fed back to the first control module 10.

In the signaling interaction process, the first control module 10 is an embedded control module, the second control module 20 is an FPGA module, the resource resetting module 30 includes an external storage module, a fast storage module, a peripheral module and a video interface physical layer implementation module, the FPGA further includes a plurality of modules, and the modules and the external related modules may have a master-slave relationship.

Fig. 4 is a schematic structural diagram of a video processing system for resource reconfiguration according to a second embodiment of the present invention. As shown in fig. 4, the first control module 10 may be an embedded control module, the second control module 20 may be an FPGA module, and the physical layer resource resetting module 30 may include an external storage module, a fast storage module, a peripheral module, a video interface physical layer implementation module, and the like. The FPGA module comprises at least one of the following components: the device comprises a bus interaction module, a Micro Control Unit (MCU) video stream preprocessing Unit, a video data stream transmission control module, a clock control module, an embedded soft core control module, a bus controller module, a video pattern processing module, an internal storage controller module, an external control module, a display clock generator module, a video time schedule controller module and a video interface IP core module.

Illustratively, the bus interaction module is used for selecting or deciding all modules connected with the bus interaction module; the MCU video stream preprocessing unit is used for preprocessing and converting the video data stream input from the external storage module according to the format and the parameter type set by the system so as to facilitate subsequent processing; the video data stream transmission control module is used for controlling the time sequence and parameters of the data stream after the data stream is preprocessed and converted; the clock control module is responsible for generating and controlling a global clock in the video or image processing process; the embedded soft core control module is a control core of the FPGA module, is used for realizing core functions of time sequence control, parameter configuration, physical process realization and the like of all modules in the FPGA module, and can adopt Xilinx soft sum processor (MicroBlaze) and the like; the bus controller module is used for controlling all modules connected with the bus interaction module; the video pattern processing module is responsible for adapting to mode conversion and time sequence control of a video image data stream corresponding to the video interface IP core module; the internal storage controller module is used for realizing the control of the fast storage module, including the writing/reading of data stream, frame control and the like; the peripheral control module is used for controlling all peripheral modules, including starting/closing of the peripheral, working mode control and the like; the display clock generator module is used for realizing the time sequence control of all modules on the video interface IP core module and the video interface physical layer; and the video time sequence controller module is responsible for data conversion, time sequence control and the like in the process of transmitting the data input from the video pattern processing module to the video interface IP core module.

It should be noted that, when the second control module 20 is an FPGA module, it may further include a plurality of modules having a master-slave relationship therein, at this time, the embedded soft core control module is a control center, and other modules are controlled by the embedded soft core control module and are all slave modules of the embedded soft core control module, and further master-slave relationships exist among other modules.

The resource resetting system of the second embodiment of the invention is optimized on the basis of the above embodiments, a perfect signaling interaction mechanism is established by defining preset message structures, each group of modules with master-slave relation performs signaling forwarding and interaction in respective links, the interaction structure and the specification of each module are defined, organized and precise signaling interaction between the master module and the slave module is realized, resource resetting is completed under the condition of ensuring seamless, smooth and non-halt of a hardware system and a platform, the minimum effective system time delay is ensured on the premise of ensuring the system to be driven by events, and the interaction reliability and efficiency are improved.

It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. Those skilled in the art will appreciate that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now be apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in some detail by the above embodiments, the invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the invention, and the scope of the invention is determined by the scope of the appended claims.

Claims

1. A resource resetting system, comprising: the system comprises a first control module, a second control module and a resource resetting module, wherein the second control module is respectively connected with the first control module and the resource resetting module;

the first control module is used for initiating a resource resetting request;

the second control module is configured to generate a resource resetting signaling according to the resource resetting request, and send the resource resetting signaling to the resource resetting module according to a preset message structure, where the preset message structure includes a physical layer channel number indication field and a link state parameter indication field, and the physical layer channel number indication field is used to indicate a channel number that needs to be supported after resource resetting;

2. The system of claim 1, wherein the resource reset module comprises:

and the link state parameter resetting module is used for resetting the link state parameters according to the link state parameter indication field, wherein the link state parameters comprise link rate, link state cache, frame polarity, voltage swing amplitude, phase-locked loop state parameters, sampling point front interference and sampling point rear interference.

3. The system of claim 2, wherein the resource reset module further comprises:

and the phase-locked loop resetting submodule is used for determining the phase-locked loop type of the port of the channel output differential pair according to the maximum channel number indicated by the physical layer channel number indication field and the link rate indicated by the link state parameter indication field, and resetting the phase-locked loop according to the channel serial number.

4. The system of claim 2, wherein the predetermined message structure further comprises: a register map indication field;

the resource resetting module further comprises:

5. The system of claim 2, wherein the predetermined message structure further comprises: and the physical layer channel clock distribution indication field is used for indicating the distribution mode of the channel clock, and the distribution mode comprises external control and automatic distribution.

6. The system of claim 5, wherein the resource reset module further comprises:

7. The system of claim 2, wherein the resource reset module further comprises:

a status information reading submodule, configured to read status information of a physical layer, where the status information includes: the method comprises the following steps of receiving and sending reconfiguration information, phase-locked loop reset information, mapping information of a physical layer register and a channel group and clock distribution information;

8. The system according to any one of claims 1 to 7, wherein the preset message structure further comprises: a master-slave module definition field and a feedback field;

the feedback field is used for defining the module state after the resource resetting signaling interaction is completed, and the module state comprises an affirmed state and a non-affirmed state.

9. The system of claim 8, wherein the predetermined message structure further comprises: checking the field;

the check field is used for checking the resource resetting signaling according to a preset specification and indicating that the interaction of the resource resetting signaling fails when the checking fails.

10. The system according to claim 8, wherein the master module is configured to receive a resource reset signaling sent by the second control module according to a preset message structure, wherein the resource reset signaling is forwarded to the slave module by the master module;