CN112420754A - Image sensing device - Google Patents
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- CN112420754A CN112420754A CN201911233038.2A CN201911233038A CN112420754A CN 112420754 A CN112420754 A CN 112420754A CN 201911233038 A CN201911233038 A CN 201911233038A CN 112420754 A CN112420754 A CN 112420754A
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Abstract
An image sensing device. An image sensing device includes a semiconductor substrate and a metal line. The semiconductor substrate includes a first surface and a second surface on opposite sides of the semiconductor substrate, and includes a plurality of unit pixels each configured to generate a pixel signal based on light incident on the first surface. The metal line is disposed over the second surface of the semiconductor substrate, and carries a pixel signal generated from the semiconductor substrate and an electric signal for generating the pixel signal. At least one of the metal lines includes an antireflection structure having a shape that guides light propagating in the semiconductor substrate and reflected by the metal line to a direction other than a direction toward the semiconductor substrate.
Description
Technical Field
The technology and implementation disclosed in this patent document relate to an image sensing device for measuring a distance between the image sensing device and an object to be measured.
Background
With the development of computer and communication industry technologies, the demand for high-quality, high-performance image sensors is rapidly increasing in various devices such as digital cameras and smart phones.
Image sensors may be classified into Charge Coupled Device (CCD) image sensors and Complementary Metal Oxide Semiconductor (CMOS) image sensors. CMOS image sensors are now widely used because of their several advantages over CCD image sensors, including, for example, lower power consumption, lower production costs, and smaller size. This advantage of CMOS image sensors makes these sensors more suitable for implementation in mobile devices.
Disclosure of Invention
Embodiments of the disclosed technology relate to an image sensing device capable of preventing light propagating in a semiconductor substrate from being reflected by metal lines, thereby preventing reflected light from propagating to the semiconductor substrate.
According to one embodiment of the disclosed technology, an image sensing apparatus may include: a semiconductor substrate including a first surface and a second surface on opposite sides of the semiconductor substrate, and configured to include a plurality of unit pixels, each unit pixel configured to generate a pixel signal based on light incident on the first surface; and a metal line disposed over the second surface of the semiconductor substrate and configured to carry a pixel signal generated from the semiconductor substrate and an electrical signal for generating the pixel signal. At least one of the metal lines may include an anti-reflection structure having a shape that guides light propagating in the semiconductor substrate and reflected from the metal line to a direction other than a direction toward the semiconductor substrate.
According to another embodiment of the disclosed technology, an image sensing apparatus may include: a substrate layer comprising a plurality of unit pixels, each unit pixel configured to generate a pixel signal based on light incident on a first surface; and a metal line disposed over a second surface of the substrate layer disposed away from the first surface and coupled to the substrate layer. The metal lines may include a zigzag pattern formed on a surface facing the substrate layer.
It is to be understood that the foregoing general description, drawings, and the following detailed description in this patent document are exemplary and explanatory of the technical features and implementations of the disclosed technology.
Drawings
FIG. 1 illustrates an example of an image sensing device based on some implementations of the disclosed technology.
Fig. 2 is a sectional view illustrating an example of a unit pixel region of the pixel array shown in fig. 1.
Fig. 3A to 3F are sectional views illustrating a process for forming the structure of fig. 2.
Fig. 4 is a cross-sectional view illustrating another anti-reflective structure based on some implementations of the disclosed technology.
Fig. 5 is a cross-sectional view illustrating another anti-reflective structure based on some implementations of the disclosed technology.
Fig. 6 is a cross-sectional view illustrating another anti-reflective structure based on some implementations of the disclosed technology.
Detailed Description
Reference will now be made in detail to some embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Three-dimensional (3D) image sensors may be used for object scanning, measuring distance, 3D photography, and the like. When acquiring a 3D image using an image sensor, color information of the 3D image and a distance (or depth) between the image sensor and a measured object are generally used.
The distance between the object and the image sensor can be acquired in two ways: passive methods and active methods. The passive method can obtain the distance between the object and the image sensor using only image information of the object without irradiating light to the measured object. The passive method can be applied to a stereo camera.
On the other hand, the active method measures a distance by irradiating light to an object by a light source. Examples of active methods include triangulation methods and time of flight (TOF) methods. The triangulation method measures a distance based on light irradiated to an object and light reflected from the object. The TOF method measures distance by measuring the round trip time of illumination light.
Fig. 1 is a block diagram illustrating an example of an image sensing apparatus based on some implementations of the disclosed technology.
The image sensing device may use time-of-flight (TOF) techniques to measure the distance between the image sensing device and the object being measured. The image sensing device may include a light source 100, a lens module 200, a pixel array 300, and a control circuit 400.
The light source 100 can irradiate light to the object 1 upon receiving the clock signal MLS from the control circuit 400. Examples of the light source 100 may include a combination of a Laser Diode (LD), a Light Emitting Diode (LED) for emitting infrared light or visible light, a near infrared laser (NIR), a point light source, a monochromatic light source combined with a white lamp or a monochromator, and other laser sources. For example, the light source 100 may irradiate infrared light of a wavelength of 800nm to 1000 nm. Although fig. 1 shows only one light source 100 for convenience of description, it is noted that a plurality of light sources may be disposed in the vicinity of the lens module 200.
The lens module 200 may collect light reflected from the object 1 and may focus the collected light onto Pixels (PX) of the pixel array 300. The lens module 200 may include a focusing lens having a surface formed of glass or plastic, or other cylindrical optical element having a surface formed of glass or plastic material. The lens module 200 may include a focusing lens having a convex structure.
The pixel array 300 may include a plurality of unit Pixels (PX) arranged in a two-dimensional (2D) array. In one example, the unit pixels are arranged along a first direction and a second direction perpendicular to each other. The unit Pixels (PX) may be formed in the semiconductor substrate, and each unit pixel PX may convert light received through the lens module 200 into an electrical signal corresponding to the received light, so that each unit pixel may output a pixel signal. In some embodiments of the disclosed technology, the pixel signal may include information associated with a distance to the object 1. The unit Pixel (PX) may be a Current Assisted Photon Demodulator (CAPD) pixel for detecting electrons generated in the substrate by incident light based on the potential difference. In some cases, incident light may penetrate a substrate in which the pixel array 300 is formed, and light propagating in the substrate may be reflected from an interconnection disposed above the substrate. To reduce reflections within the pixel array 300, the pixel array 300 may further include an anti-reflection structure. In some implementations, the anti-reflective structure can include a saw-tooth structure formed on interconnects (e.g., metal lines) over the substrate to carry pixel signals and/or control signals. In one example, the anti-reflection structure may be formed by etching at least one side of the interconnection such that the at least one side of the interconnection includes a slope continuously arranged along the at least one side of the interconnection. The anti-reflection structure will be described in detail hereinafter.
The control circuit 400 may irradiate light to the object 1 by controlling the light source 100 and the associated optical device. The control circuit 400 may process each pixel signal corresponding to light reflected from the object 1 by operating the unit Pixels (PX) of the pixel array 300 to measure the distance to the surface of the object 1.
The control circuit 400 may include a row decoder 410, a light source driver 420, a timing controller 430, a photogate controller 440, and a logic circuit 450.
The row decoder 410 may be used to select a desired unit Pixel (PX) of the pixel array 300 in response to a timing signal generated by the timing controller 430. For example, row decoder 410 may generate control signals to select at least one of a plurality of row lines. The control signal may include a selection signal for controlling the selection transistor and a transmission (Tx) signal for controlling the transmission gate.
The light source driver 420 may generate a clock signal MLS that may be used to operate the light source 100 in response to a control signal from the timing controller 430. The light source driver 420 may provide at least one of the clock signal MLS or information about the clock signal MLS to the photogate controller 28.
The timing controller 430 may generate timing signals to control the row decoder 410, the light source driver 420, the photogate controller 440, and the logic circuit 450 at a desired timing.
The photogate controller 440 may generate a photogate control signal based on the control signal generated by the timing controller 430 to apply the photogate control signal to the pixel array 300 at a desired timing.
The logic circuit 450 may process pixel signals received from the pixel array 300 in response to timing signals and control signals of the timing controller 430. In some implementations, the logic 450 may be used to calculate the distance to the object 1. The logic circuit 450 may include a Correlated Double Sampling (CDS) circuit for performing a Correlated Double Sampling (CDS) on the pixel signals generated from the pixel array 300. In one example, the CDS circuit may be used to remove an offset value of a pixel by sampling the pixel twice to take the difference between the two samples. In addition, the logic circuit 450 may include an analog-to-digital converter (ADC) for converting an analog output signal of the CDS circuit into a digital signal.
Fig. 2 is a sectional view illustrating an example of a unit pixel region of the pixel array 300 shown in fig. 1.
As shown in fig. 2, the pixel array 300 may include a light receiving layer 310, a substrate layer 320, and an interconnection layer (e.g., a metal layer) 330.
The light receiving layer 310 may be used to guide the light beam reflected from the object 1 to the semiconductor substrate 321. The light receiving layer 310 may include a microlens 312 and an antireflection layer 314 sequentially stacked over a semiconductor substrate 321. The anti-reflection layer 314 may be formed of, for example, silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), or silicon oxycarbide (SiCO).
The substrate layer 320 may include a semiconductor substrate 321 having a first surface and a second surface. The light receiving layer 310 may be formed over a first surface of the semiconductor substrate 321, and the interconnect layer 330 may be formed over a second surface facing away from the first surface. The semiconductor substrate 321 may generate electron-hole pairs based on incident light received through the first surface. The device isolation layer 322 may be formed to electrically isolate the active region from adjacent active regions and other components. A device isolation layer 322 may be formed on the second surface. The device isolation layer 322 may be formed as a Shallow Trench Isolation (STI) structure. A pixel transistor 323 for reading out a pixel signal may be formed on the active region defined by the device isolation layer 322. Further, each of the active regions may include a control region 324 and a detection region 325 coupled to the metal layer 334 of the interconnect layer 330. The detection region 324 may generate a carrier current (e.g., a hole current) in the semiconductor substrate 321 based on the voltage at the metal line 334. In one example, when electrons generated by light incident on the semiconductor substrate 321 are moved by a carrier current, the detection region 325 may capture the moved electrons. The control region 324 may include a P-type impurity region. The control region 324 may include a P (+) diffusion region and a P well. The detection region 325 may include an N-type impurity region. The detection region 325 may include an N (+) diffusion region and an N well.
The interconnection layer 330 may include a plurality of stacked interlayer insulating layers 331 and a plurality of metal lines 334 and 337 stacked as a plurality of layers within the interlayer insulating layers 331. Each interlayer insulating layer 331 may include at least one of an oxide film or a nitride film. Each of the metal lines 334 and 337 may include at least one of aluminum (Al), copper (Cu), or tungsten (W). The metal lines 334 and 337 may be used to carry electrical signals (voltages) used to generate pixel signals and to carry pixel signals generated from the substrate layers. The metal lines 334 and 337 at different levels may be coupled to each other by a contact plug 336. In addition, the metal line 334 may be coupled to the control region 324, the detection region 325, and the pixel transistor 323 of the semiconductor substrate 321 (through the contact plug 333).
The interconnect layer 330 based on some embodiments of the disclosed technology may include an anti-reflective structure. In more detail, after light is first incident on the first surface of the semiconductor substrate 321 and transmitted through the semiconductor substrate 321, the anti-reflection structure may prevent the light traveling in the semiconductor substrate 321 from being reflected by the metal lines, thereby preventing the reflected light from traveling to the semiconductor substrate 321.
In some implementations, a time of flight (TOF) sensor utilizes light of a long wavelength. As a result, such light of long wavelength received by the light receiving layer 310 is more likely to propagate in the semiconductor substrate 321, and the light may be reflected from the metal lines of the interconnection layer 330 and directed toward the semiconductor substrate 321. In some implementations, the TOF sensor can calculate the distance between the image sensor and the measured object based on the signal difference for each phase. In this case, when the light beam reflected from the metal wire propagates to the semiconductor substrate, such a reflected light beam may be added to another phase of the light beam instead of the original phase, resulting in an error in the distance calculation.
Some embodiments of the disclosed technology can avoid such errors by preventing the light beam from reflecting at the metal lines and/or by preventing the reflected light beam from propagating to the semiconductor substrate 321.
In some implementations, to prevent the light beam from being reflected toward the semiconductor substrate 321, the metal line 334 may include a zigzag pattern at a surface thereof. In one example, the metal line 334 may include a zigzag pattern at a surface facing the semiconductor substrate 321. The zigzag pattern of the metal lines is configured to guide light reflected at the surface thereof to a direction other than the semiconductor substrate 321, and the reflected light may be guided to another direction, as shown by an arrow of fig. 2, instead of being redirected to the semiconductor substrate 321.
In some embodiments of the disclosed technology, the interconnect layer 330 may further include an optical delay film 332 for reducing the propagation speed of light in the semiconductor substrate 321. The light retardation film 332 may be disposed between the semiconductor substrate 321 and the metal line 334. The optical retardation film 332 may include at least one of a high dielectric constant material film or a high magnetic permeability material film. In this case, the high-permittivity material film may include alumina (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Hafnium silicate (HfSiO )4) Zirconium silicate (ZrSiO), yttrium oxide (Y)2O3) Tantalum oxide (Ta)2O5) Or titanium oxide (TiO)2) At least one of (1). The high permeability material film may include a ferromagnetic material.
In some embodiments of the disclosed technology, undesired reflection of light towards the semiconductor substrate 321 may be avoided by two steps: (1) the propagation speed of light that has penetrated the semiconductor substrate 321 is reduced due to the light retardation film 332; (2) the light that has passed through the optical retardation film 332 may be directed in a direction other than the direction toward the semiconductor substrate 321.
In some embodiments of the disclosed technology, an anti-reflection film 335 may be further formed over the surface of the zigzag pattern of the metal lines 334, so that the anti-reflection film 335 can effectively prevent reflection of light.
Fig. 3A to 3F are sectional views illustrating a process for forming the structure of fig. 2.
As shown in fig. 3A, after forming device isolation trenches by patterning and etching the second surface to a predetermined depth, an insulating layer may be formed to fill the trenches, thereby forming device isolation layers 322 defining active regions.
Subsequently, a pixel transistor 323 for reading out a pixel signal may be formed over the active region. In addition, a P-type impurity and an N-type impurity may be implanted into an active region formed at the center of each pixel, so that the control region 324 and the detection region 325 may be formed.
As shown in fig. 3B, a first interlayer insulating layer 331a may be formed over the substrate layer 320 including the pixel transistor 323, the control region 324, and the detection region 325, and an optical delay film 332 may be formed over the first interlayer insulating layer 331 a.
Subsequently, a second interlayer insulating layer 331b may be formed over the optical retardation film 332.
Each of the first and second interlayer insulating layers 331a and 331b may include at least one of an oxide film or a nitride film. The optical retardation film 332 may include at least one of a high dielectric constant material film or a high magnetic permeability material film.
As shown in fig. 3C, a specific region where the metal line 334 is to be formed may be formed by etching a portion of the second interlayer insulating layer 331b, so that a trench having a bottom surface formed in a zigzag pattern may be formed. In some implementations, diagonal line regions of the zigzag pattern in the trench may be formed in a stepped shape.
In some implementations, the zigzag pattern is not formed in the region to be used for forming the contact plug on the bottom surface of the trench.
Subsequently, an anti-reflection film 335 may be formed in some regions of the bottom surface of the trench.
For example, the anti-reflection film 335 may be formed on the bottom surface of the trench along the surface of the diagonal line region of the zigzag pattern.
As shown in fig. 3D, a contact hole may be formed by etching the bottom surface of the trench to form a specific region to be used for forming the contact plug. For example, a region without the zigzag pattern may be etched from the bottom surface of the trench, thereby forming a contact hole.
Subsequently, a conductive material film may be formed to fill the contact hole, thereby forming a contact plug 333 coupled to each of the control region 324, the detection region 325, and the pixel transistor 323. In one example, the conductive material film may include a metal film (e.g., tungsten W).
As shown in fig. 3E, after forming a metal film over the second interlayer insulating layer 331b and the anti-reflection film 335 to fill the trench, the metal film may be patterned to form a metal line 334.
Subsequently, an interlayer insulating layer 331c may be formed over the metal line 334 and the second interlayer insulating layer 331 b. Subsequently, the interlayer insulating layer 331c may be etched in such a manner that contact holes are formed to expose the metal lines 334, and a conductive material film may be formed in such a manner that the contact holes 336 are formed in the interlayer insulating layer 331c to fill the contact holes.
After a metal film is formed over the interlayer insulating layer 331c, the metal film is patterned, thereby forming a metal line 337. Subsequently, an interlayer insulating layer 331d may be formed over the metal line 337 and the interlayer insulating layer 331 c.
As shown in fig. 3F, an antireflection film 314 and a microlens 312 may be sequentially formed over a first surface of a semiconductor substrate 321.
The zigzag pattern is shown by way of example in fig. 2, and thus, the metal line may have any shape capable of directing a light beam reflected from the surface of the metal line in a direction other than a direction toward the semiconductor substrate.
Fig. 4 is a cross-sectional view illustrating another example of an antireflective structure based on some implementations of the disclosed technology.
As shown in fig. 4, in addition to the zigzag pattern formed over the metal line 334, another zigzag pattern may be formed over another metal line 337 disposed over the metal line 334.
The example shown in fig. 2 includes a zigzag pattern formed only at a surface of the metal line 334 located adjacent to the substrate layer 320.
However, some of the light beams penetrating the semiconductor substrate 321 may propagate through spaces between adjacent metal lines 334, and the light beams may be reflected from the metal lines 337 arranged at different levels so that the reflected light may reach the semiconductor substrate 321.
In some embodiments of the disclosed technology, the zigzag pattern may also be formed in a particular region (e.g., a region overlapping with a space between consecutive metal lines 334) where light escaping from the zigzag pattern of metal lines 334 can reach (e.g., metal lines 337 as discussed above).
Fig. 5 is a cross-sectional view illustrating another example of an antireflective structure based on some implementations of the disclosed technology.
As shown in fig. 5, the zigzag pattern formed in different positions within the pixel array 300 may have different shapes.
For example, zigzag patterns each having an inverted pyramid shape may be formed at the central portion (C) of the pixel array 300. In other words, the surface of the metal line 334 formed at the central portion (C) of the pixel array 300 may be etched along oblique lines in 4 directions, so that the metal line 334 may be formed in a zigzag pattern having an inverted pyramid shape.
In other words, each of the metal lines 334 located in the upper region (U) of the pixel array 300 and each of the other metal lines 334 located in the lower region (D) of the pixel array 300 may have a zigzag pattern etched in only one direction (i.e., a zigzag pattern etched in an oblique line direction) as shown in fig. 2. The zigzag pattern formed in the upper region (U) and the zigzag pattern formed in the lower region (D) may be symmetrical to each other in the diagonal direction.
In addition, each of the metal lines 334 located in the left region (L) of the pixel array 300 and each of the other metal lines 334 located in the right region (R) of the pixel array 300 may have a zigzag pattern etched in only one direction (i.e., a zigzag pattern etched in an oblique line direction) as shown in fig. 2. The zigzag pattern formed in the left region (L) and the zigzag pattern formed in the right region (R) may be symmetrical to each other in an oblique line direction.
That is, the oblique line direction of the zigzag pattern of the unit pixels can be changed according to the incident beam direction.
Fig. 6 is a cross-sectional view illustrating another example of an antireflective structure based on some implementations of the disclosed technology.
The embodiment of fig. 5 has disclosed that the oblique lines of the zigzag pattern formed in the regions C, U, D, R and L of the pixel array 300, respectively, have the same slope.
As shown in fig. 6, the oblique lines of the zigzag pattern may have different slopes according to their positions within the pixel array 300.
For example, the metal line 334 located at the central portion (C) of the pixel array 300 may have a zigzag pattern of an inverted pyramid shape as shown in fig. 4.
The metal lines 334 positioned in the upper region (U), the lower region (D), the left region (L), and the right region (R) of the pixel array 300 may have a zigzag pattern etched only in one direction (i.e., in a diagonal line direction). In this case, the slope of the oblique line may gradually increase as it gets closer to the edge area of the pixel array 300.
As is apparent from the above description, the image sensing device based on the embodiments of the disclosed technology can avoid distance calculation errors by preventing light beams propagating in a semiconductor substrate from being reflected by metal lines and by preventing the light beams from being directed to the semiconductor substrate.
While a number of exemplary embodiments have been described, it should be understood that numerous other modifications and embodiments can be devised based on the disclosure. In particular, within the scope of the disclosure of this patent document, many variations and modifications are possible in the component parts and/or arrangements. In addition to variations and modifications in the component parts and/or arrangements, alternative uses may also be apparent to those skilled in the art.
Cross Reference to Related Applications
This patent document claims priority and benefit from korean patent application No.10-2019-0103667, filed on 23.8.2019, the entire contents of which are incorporated herein by reference.
Claims (20)
1. An image sensing device, comprising:
a semiconductor substrate including a first surface and a second surface on opposite sides of the semiconductor substrate, and configured to include a plurality of unit pixels, each unit pixel configured to generate a pixel signal based on light incident on the first surface; and
a plurality of metal lines disposed over the second surface of the semiconductor substrate and configured to carry pixel signals generated from the semiconductor substrate and electrical signals for generating the pixel signals,
wherein at least one of the plurality of metal lines includes an antireflection structure having a shape that guides light propagating in the semiconductor substrate and reflected by the plurality of metal lines to a direction other than a direction toward the semiconductor substrate.
2. The image sensing device of claim 1, wherein the plurality of metal lines comprise:
a plurality of first metal lines coupled to the semiconductor substrate or a pixel transistor formed in the semiconductor substrate through a first contact plug and configured to have the anti-reflection structure; and
a plurality of second metal lines formed over the plurality of first metal lines and coupled to the plurality of first metal lines by second contact plugs.
3. The image sensing device according to claim 2, further comprising:
an optical retardation film disposed between the semiconductor substrate and the plurality of first metal lines and configured to reduce a propagation speed of light.
4. The image sensing device of claim 3, wherein the optical retardation film comprises at least one of a high dielectric constant material film and a high magnetic permeability material film.
5. The image sensing device of claim 4,
the high dielectric constant material film includes aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Hafnium silicate (HfSiO )4) Zirconium silicate (ZrSiO), yttrium oxide (Y)2O3) Tantalum oxide (Ta)2O5) Or titanium oxide (TiO)2) At least one of; and is
The high dielectric constant material film includes a ferromagnetic material.
6. The image sensing device of claim 1, wherein the anti-reflection structure comprises:
a sawtooth pattern configured to direct light reflected at a surface of the sawtooth pattern in a direction other than a direction toward the semiconductor substrate.
7. The image sensing device of claim 6, further comprising:
an anti-reflection film formed along diagonal regions of the zigzag pattern.
8. The image sensing device of claim 2, wherein the semiconductor substrate comprises:
a control region configured to generate a carrier current based on a voltage on one of the plurality of first metal lines; and
a detection region coupled to one of the plurality of first metal lines and configured to capture electrons flowing in the semiconductor substrate by the carrier current.
9. The image sensing device according to claim 8,
the control region includes a P-type impurity region; and is
The detection region includes an N-type impurity region.
10. The image sensing device according to claim 2, wherein the antireflection structure is further formed in a region of the plurality of second metal lines to which light escaping from the zigzag pattern of the plurality of first metal lines reaches.
11. The image sensing device according to claim 1, wherein, in a pixel array in which the plurality of unit pixels are arranged in a first direction and a second direction perpendicular to the first direction, the antireflection structure includes:
a first zigzag pattern formed in a metal line positioned at a central portion of the pixel array and etched along oblique lines in a first direction, a second direction, a third direction, and a fourth direction;
a second zigzag pattern formed in the metal line in the first region of the central portion and etched along an oblique line only in the first direction;
a third zigzag pattern formed in a metal line in a second region of the central portion and etched along oblique lines only in the second direction symmetrical to the first direction;
a fourth zigzag pattern formed in the metal line in a third region of the central portion and etched along oblique lines only in the third direction; and
a fifth zigzag pattern formed in a metal line in a fourth region of the central portion and etched along oblique lines only in the fourth direction symmetrical to the third direction.
12. The image sensing device according to claim 11, wherein a slope of an oblique line of the second to fifth zigzag patterns gradually increases as closer to an edge region of the pixel array.
13. An image sensing device, comprising:
a substrate layer comprising a plurality of unit pixels, each unit pixel configured to generate a pixel signal based on light incident on a first surface; and
a plurality of metal lines disposed over a second surface of the substrate layer disposed away from the first surface and coupled to the substrate layer,
wherein the plurality of metal lines include a zigzag pattern formed on a surface facing the substrate layer.
14. The image sensing device of claim 13, wherein the substrate layer comprises a semiconductor substrate,
wherein the semiconductor substrate includes:
a control region configured to generate a carrier current based on a voltage at the plurality of metal lines; and
a detection region configured to capture electrons flowing in the semiconductor substrate by the carrier current.
15. The image sensing device of claim 13, wherein the sawtooth pattern comprises:
at least one sloped line region formed by etching at least one side of at least one of the plurality of metal lines such that the at least one side of the at least one of the plurality of metal lines includes a sloped portion continuously arranged along the at least one side of the at least one of the plurality of metal lines.
16. The image sensing device of claim 15, wherein the plurality of metal lines further comprises:
and an anti-reflection film formed along the zigzag diagonal regions.
17. The image sensing device according to claim 13, wherein, in a pixel array in which the plurality of unit pixels are arranged in a first direction and a second direction perpendicular to the first direction, the zigzag pattern includes:
a first zigzag pattern formed in a metal line located at a central portion of the pixel array and etched along oblique lines in a first direction, a second direction, a third direction, and a fourth direction;
a second zigzag pattern formed in the metal line in the first region of the central portion and etched along an oblique line only in the first direction;
a third zigzag pattern formed in a metal line in a second region of the central portion and etched along oblique lines only in the second direction symmetrical to the first direction;
a fourth zigzag pattern formed in the metal line in a third region of the central portion and etched along oblique lines only in the third direction; and
a fifth zigzag pattern formed in the metal line in a fourth region of the central portion and etched along oblique lines only in a fourth direction symmetrical to the third direction.
18. The image sensing device according to claim 17, wherein a slope of an oblique line of the second to fifth zigzag patterns gradually increases as closer to an edge region of the pixel array.
19. The image sensing device of claim 13, further comprising:
an optical retardation film disposed between the semiconductor substrate and the plurality of metal lines and configured to reduce a propagation speed of light.
20. The image sensing device of claim 19, wherein the optical retardation film comprises at least one of a high dielectric constant material film and a high magnetic permeability material film.
Applications Claiming Priority (2)
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KR10-2019-0103667 | 2019-08-23 | ||
KR1020190103667A KR20210023459A (en) | 2019-08-23 | 2019-08-23 | Image sensing device |
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KR (1) | KR20210023459A (en) |
CN (1) | CN112420754A (en) |
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