CN112416240B

CN112416240B - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN112416240B
Application number: CN201910778911.XA
Authority: CN
Inventors: 梁立群
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2019-08-22
Filing date: 2019-08-22
Publication date: 2022-10-21
Anticipated expiration: 2039-08-22
Also published as: CN112416240A

Abstract

The invention provides a data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: receiving first subdata in a plurality of subdata of the first data, and generating a first error check code corresponding to the first subdata; receiving second subdata of the plurality of subdata of the first data, and generating a second error check code corresponding to the second subdata; combining the first error check code and the second error check code to obtain a third error check code, wherein the third error check code is used for checking whether second data combined by the first subdata and the second subdata has errors; and storing the second data and the third error check code into the rewritable nonvolatile memory module.

Description

Data writing method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data writing method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Generally, to prevent errors during data transmission, when the memory management circuit writes a piece of data into the rewritable nonvolatile memory module, an error check code corresponding to the data is usually written together. When reading data, the error checking code can be used to check whether the read data has errors (e.g., contains error bits).

However, it should be noted that usually a data can be further divided into a plurality of sub-data. In some cases, the memory management circuit may only take a sub-data of a data and immediately write the obtained sub-data and the error check code corresponding to the sub-data into the rewritable nonvolatile memory module. Then, when the memory management circuit obtains another sub-data of the data, it is assumed that the memory management circuit writes the another sub-data and the error check code corresponding to the another sub-data into the rewritable nonvolatile memory module. Then, at a certain time point (for example, when the rewritable nonvolatile memory module is powered on again or is idle after being powered off), the memory management circuit may combine the first sub-data and the second sub-data in the rewritable nonvolatile memory module to generate combined data, generate an error check code corresponding to the combined data, and store the combined data and the error check code corresponding to the combined data in the rewritable nonvolatile memory module.

It should be noted that, in the process of generating the error checking code corresponding to the merged data, the memory management circuit usually needs to read the first sub-data and the second sub-data from the rewritable non-volatile memory module into the buffer memory to generate the merged data according to the read sub-data. After the merged data is generated, the memory management circuit generates an error check code corresponding to the merged data according to the merged data, and finally writes the merged data and the error check code corresponding to the merged data into the rewritable nonvolatile memory module. However, in the process of reading the sub-data from the rewritable nonvolatile memory module and writing the merged data back to the rewritable nonvolatile memory module, there is a possibility that an error bit may be generated in the merged data due to cosmic rays or other unexpected factors. One of the problems to be solved by those skilled in the art is how to avoid the generation of error bits in the merged data and efficiently generate the error check code corresponding to the merged data.

Disclosure of Invention

The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can avoid the problem of generating error bits in merged data in the prior art.

The invention provides a data writing method, which is used for a rewritable nonvolatile memory module and comprises the following steps: receiving a first subdata of a plurality of subdata of first data, and generating a first error check code corresponding to the first subdata; receiving a second subdata of the first data, and generating a second error check code corresponding to the second subdata; combining the first error check code and the second error check code to obtain a third error check code, wherein the third error check code is used for checking whether a second data combined by the first subdata and the second subdata has errors; and storing the second data and the third error check code in the rewritable nonvolatile memory module.

In an embodiment of the invention, the plurality of sub-data are arranged at a plurality of positions according to a sequence, the first sub-data is located at a first position in the plurality of positions, and the second sub-data is located at a second position in the plurality of positions. Wherein the step of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data comprises: configuring the first subdata at the first position, setting bits in other positions except the first position to be zero to generate first zero-padded data, and generating the first error check code according to the first zero-padded data. Wherein the step of receiving the second sub data of the plurality of sub data of the first data and generating the second error check code corresponding to the second sub data comprises: and configuring the second subdata at the second position, setting bits in other positions except the second position to be zero to generate second zero-padded data, and generating the second error check code according to the second zero-padded data.

In an embodiment of the present invention, the method further includes: recording a first bit sequence corresponding to the first zero-padded data, wherein bits corresponding to the first position in the first bit sequence are represented by a first numerical value and bits corresponding to positions other than the first position are represented by a second numerical value; and recording a second bit sequence corresponding to the second zero-padded data, wherein bits corresponding to the second position in the second bit sequence are represented by the first numerical value and bits corresponding to positions other than the second position are represented by the second numerical value.

In an embodiment of the present invention, the step of combining the first error check code and the second error check code to obtain the third error check code comprises: performing exclusive-OR (exclusive or) operation according to the first error check code and the second error check code to obtain the third error check code, and recording a third bit sequence corresponding to the second data. Wherein bits corresponding to the first and second positions in the third bit sequence are represented by the first numerical value and bits corresponding to positions other than the first and second positions are represented by the second numerical value.

In an embodiment of the invention, before the step of receiving the second sub data of the plurality of sub data of the first data and generating the second error check code corresponding to the second sub data, the method further includes: and storing the first subdata and the first error check code into the rewritable nonvolatile memory module. Wherein combining the first error check code and the second error check code to obtain the third error check code comprises: reading the first error check code from the rewritable nonvolatile memory module and combining the first error check code and the second error check code to obtain the third error check code.

In an embodiment of the invention, a size of the first data conforms to a size of an entity page, the plurality of sub-data of the first data are arranged at a plurality of positions according to an order, the first sub-data are located at a first position in the plurality of positions, and the second sub-data are located at a second position in the plurality of positions. Wherein the step of storing the second data and the third error checking code into the rewritable nonvolatile memory module comprises: and storing the second sub data to the entity page so that the first sub data and the second sub data in the entity page form the second data, wherein the first sub data is located at the first position and the second sub data is located at the second position in the entity page.

In an embodiment of the invention, the first sub-data is a first ciphertext generated by encrypting a first plaintext. Wherein the step of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data comprises: and generating a first plaintext error check code corresponding to the first plaintext, and storing the first ciphertext, the first plaintext error check code and the first error check code into the rewritable non-volatile memory module.

In an embodiment of the present invention, a size of the first data conforms to a size of an entity page, the sub-data of the first data are arranged at a plurality of positions according to a sequence, the first sub-data are located at a first position in the plurality of positions, the second sub-data are located at a second position in the plurality of positions, and the second sub-data are a second ciphertext generated by encrypting a second plaintext, and the method further includes: storing the second ciphertext to the physical page such that the first ciphertext and the second ciphertext in the physical page form the second data, wherein the first ciphertext is located at the first position and the second ciphertext is located at the second position in the physical page.

In an embodiment of the present invention, the method further includes: combining the first plaintext error checking code with a second plaintext error checking code corresponding to the second plaintext to obtain a third plaintext error checking code; and storing the third plaintext error check code in the rewritable non-volatile memory module.

In an embodiment of the present invention, the method further includes: reading the entity page to obtain read data, decrypting the read data to obtain decrypted data, and verifying the decrypted data according to the third plaintext error check code; when the decrypted data is verified to be failed according to the third plaintext error check code, encrypting the decrypted data to obtain encrypted data, and generating a new error check code according to the encrypted data; determining whether the new error check code is the same as the third error check code; when the new error check code is the same as the third error check code, judging that the decrypted data has no error; and when the new error check code is different from the third error check code, judging that the decrypted data has errors.

The invention provides a memory control circuit unit which is used for controlling a rewritable nonvolatile memory module. The memory control circuit unit includes: host interface, memory interface and memory management circuit. The host interface is used for coupling to a host system. The memory interface is used for being coupled to the rewritable nonvolatile memory module. The memory management circuit is coupled to the host interface and the memory interface and is configured to: receiving a first subdata of a plurality of subdata of first data, and generating a first error check code corresponding to the first subdata; receiving a second subdata of the first data, and generating a second error check code corresponding to the second subdata; combining the first error checking code and the second error checking code to obtain a third error checking code, wherein the third error checking code is used for checking whether a second data combined by the first sub-data and the second sub-data has an error; and storing the second data and the third error check code in the rewritable nonvolatile memory module.

In an embodiment of the invention, the plurality of sub-data are arranged at a plurality of positions according to a sequence, the first sub-data is located at a first position in the plurality of positions, and the second sub-data is located at a second position in the plurality of positions. In an operation of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data, the memory management circuit is further configured to configure the first sub-data at the first position and set bits in other positions than the first position to zero to generate a first zero-padded data, and generate the first error check code according to the first zero-padded data. In an operation of receiving the second sub-data of the plurality of sub-data of the first data and generating the second error checking code corresponding to the second sub-data, the memory management circuit is further configured to configure the second sub-data at the second position and set bits in other positions than the second position to zero to generate a second zero-padded data, and generate the second error checking code according to the second zero-padded data.

In an embodiment of the invention, the plurality of sub-data are arranged in a plurality of positions according to an order, the first sub-data are located at a first position in the plurality of positions, and the second sub-data are located at a second position in the plurality of positions. In an operation of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data, the memory management circuit is further configured to configure the first sub-data at the first position and set bits in other positions except the first position to zero to generate a first zero-padded data, and generate the first error check code according to the first zero-padded data. In an operation of receiving the second sub-data of the plurality of sub-data of the first data and generating the second error checking code corresponding to the second sub-data, the memory management circuit is further configured to configure the second sub-data at the second position and set bits in other positions than the second position to zero to generate a second zero-padded data, and generate the second error checking code according to the second zero-padded data.

In an embodiment of the invention, the memory management circuit is further configured to record a first bit sequence corresponding to the first zero-padded data, wherein bits corresponding to the first position in the first bit sequence are represented by a first numerical value and bits corresponding to positions other than the first position are represented by a second numerical value. The memory management circuit is further configured to record a second bit sequence corresponding to the second zero-padded data, wherein bits corresponding to the second position in the second bit sequence are represented by the first numerical value and bits corresponding to positions other than the second position are represented by the second numerical value.

In an embodiment of the invention, in the operation of combining the first error check code and the second error check code to obtain the third error check code, the memory management circuit is further configured to perform an exclusive or operation according to the first error check code and the second error check code to obtain the third error check code, and record a third bit sequence corresponding to the second data. Wherein bits corresponding to the first and second positions in the third bit sequence are represented by the first numerical value and bits corresponding to positions other than the first and second positions are represented by the second numerical value.

In an embodiment of the invention, before the operation of receiving the second sub-data of the plurality of sub-data of the first data and generating the second error check code corresponding to the second sub-data, the memory management circuit is further configured to store the first sub-data and the first error check code into the rewritable nonvolatile memory module. In an operation of combining the first error check code and the second error check code to obtain the third error check code, the memory management circuit is further configured to read the first error check code from the rewritable non-volatile memory module and combine the first error check code and the second error check code to obtain the third error check code.

In an embodiment of the invention, a size of the first data conforms to a size of an entity page, the plurality of sub-data of the first data are arranged at a plurality of positions according to an order, the first sub-data are located at a first position in the plurality of positions, and the second sub-data are located at a second position in the plurality of positions. In an operation of storing the second data and the third error checking code in the rewritable non-volatile memory module, the memory management circuit is further configured to store the second sub-data in the physical page, so that the first sub-data and the second sub-data in the physical page form the second data, where the first sub-data is located at the first position and the second sub-data is located at the second position in the physical page.

In an embodiment of the invention, the first sub-data is a first ciphertext generated by encrypting a first plaintext. In an operation of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error checking code corresponding to the first sub-data, the memory management circuit is further configured to generate a first plaintext error checking code corresponding to the first plaintext, and store the first ciphertext, the first plaintext error checking code, and the first error checking code into the rewritable non-volatile memory module.

In an embodiment of the present invention, the size of the first data conforms to the size of an entity page, the sub-data of the first data are arranged at a plurality of positions according to a sequence, the first sub-data are located at a first position in the plurality of positions, the second sub-data are located at a second position in the plurality of positions, and the second sub-data are a second ciphertext generated after encrypting a second plaintext. The memory management circuitry is also to store the second ciphertext to the physical page such that the first ciphertext and the second ciphertext in the physical page form the second data, wherein the first ciphertext is located at the first position and the second ciphertext is located at the second position in the physical page.

In an embodiment of the present invention, the memory management circuit is further configured to combine the first plaintext error check code with a second plaintext error check code corresponding to the second plaintext to obtain a third plaintext error check code. The memory management circuit is further configured to store the third plaintext error check code in the rewritable non-volatile memory module.

In an embodiment of the invention, the memory management circuit is further configured to read the physical page to obtain read data, decrypt the read data to obtain decrypted data, and verify the decrypted data according to the third plaintext error check code. When the decrypted data is verified to have failed according to the third plaintext error check code, the memory management circuit is further configured to encrypt the decrypted data to obtain an encrypted data, and generate a new error check code according to the encrypted data. The memory management circuit is further configured to determine whether the new error check code is the same as the third error check code. When the new error check code is the same as the third error check code, the memory management circuit is further configured to determine that no error exists in the decrypted data. When the new error check code is different from the third error check code, the memory management circuit is further configured to determine that the decrypted data has an error.

The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for being coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module and is used for executing the following operations: receiving a first subdata of a plurality of subdata of first data, and generating a first error check code corresponding to the first subdata; receiving a second subdata of the first data, and generating a second error check code corresponding to the second subdata; combining the first error check code and the second error check code to obtain a third error check code, wherein the third error check code is used for checking whether a second data combined by the first subdata and the second subdata has errors; and storing the second data and the third error check code in the rewritable nonvolatile memory module.

In an embodiment of the invention, the plurality of sub-data are arranged at a plurality of positions according to a sequence, the first sub-data is located at a first position in the plurality of positions, and the second sub-data is located at a second position in the plurality of positions. In an operation of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data, the memory control circuit unit is further configured to configure the first sub-data at the first position and set bits in other positions than the first position to zero to generate a first zero-padded data, and generate the first error check code according to the first zero-padded data. In an operation of receiving the second sub-data of the plurality of sub-data of the first data and generating the second error check code corresponding to the second sub-data, the memory control circuit unit is further configured to configure the second sub-data at the second position and set bits in other positions except the second position to zero to generate a second zero-padded data, and generate the second error check code according to the second zero-padded data.

In an embodiment of the invention, the memory control circuit unit is further configured to record a first bit sequence corresponding to the first zero-padded data, wherein a bit corresponding to the first position in the first bit sequence is represented by a first numerical value and bits corresponding to positions other than the first position are represented by a second numerical value. The memory control circuit unit is further configured to record a second bit sequence corresponding to the second zero-padded data, wherein bits corresponding to the second position in the second bit sequence are represented by the first numerical value and bits corresponding to positions other than the second position are represented by the second numerical value.

In an embodiment of the invention, in the operation of combining the first error check code and the second error check code to obtain the third error check code, the memory control circuit unit is further configured to perform an exclusive or (exclusive or) operation according to the first error check code and the second error check code to obtain the third error check code, and record a third bit sequence corresponding to the second data. Wherein bits corresponding to the first and second positions in the third bit sequence are represented by the first numerical value and bits corresponding to positions other than the first and second positions are represented by the second numerical value.

In an embodiment of the invention, before the operation of receiving the second sub-data of the plurality of sub-data of the first data and generating the second error check code corresponding to the second sub-data, the memory control circuit unit is further configured to store the first sub-data and the first error check code into the rewritable nonvolatile memory module. In an operation of combining the first error check code and the second error check code to obtain the third error check code, the memory control circuit unit is further configured to read the first error check code from the rewritable nonvolatile memory module and combine the first error check code and the second error check code to obtain the third error check code.

In an embodiment of the invention, a size of the first data conforms to a size of an entity page, the sub-data of the first data are arranged at a plurality of positions according to a sequence, the first sub-data are located at a first position in the plurality of positions, and the second sub-data are located at a second position in the plurality of positions. In an operation of storing the second data and the third error checking code in the rewritable nonvolatile memory module, the memory control circuit unit is further configured to store the second sub data in the physical page, so that the first sub data and the second sub data in the physical page form the second data, where the first sub data is located at the first position and the second sub data is located at the second position in the physical page.

In an embodiment of the invention, the first sub-data is a first ciphertext generated by encrypting a first plaintext. In an operation of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data, the memory control circuit unit is further configured to generate a first plaintext error check code corresponding to the first plaintext, and store the first ciphertext, the first plaintext error check code, and the first error check code into the rewritable nonvolatile memory module.

In an embodiment of the present invention, the size of the first data conforms to the size of an entity page, the sub-data of the first data are arranged at a plurality of positions according to a sequence, the first sub-data are located at a first position in the plurality of positions, the second sub-data are located at a second position in the plurality of positions, and the second sub-data are a second ciphertext generated after encrypting a second plaintext. In an operation of storing the second data and the third error checking code in the rewritable nonvolatile memory module, the memory control circuit unit is further configured to store the second sub data in the physical page, so that the first sub data and the second sub data in the physical page form the second data, where the first sub data is located at the first position and the second sub data is located at the second position in the physical page.

In an embodiment of the present invention, the memory control circuit unit is further configured to combine the first plaintext error check code with a second plaintext error check code corresponding to the second plaintext to obtain a third plaintext error check code. The memory control circuit unit is further used for storing the third plaintext error checking code into the rewritable nonvolatile memory module.

In an embodiment of the invention, the memory control circuit unit is further configured to read the physical page to obtain read data, decrypt the read data to obtain decrypted data, and verify the decrypted data according to the third plaintext error check code. When the decrypted data is failed to be verified according to the third plaintext error check code, the memory control circuit unit is further configured to encrypt the decrypted data to obtain encrypted data, and generate a new error check code according to the encrypted data. The memory control circuit unit is further configured to determine whether the new error check code is identical to the third error check code. When the new error check code is the same as the third error check code, the memory control circuit unit is further configured to determine that there is no error in the decrypted data. When the new error check code is different from the third error check code, the memory control circuit unit is further configured to determine that the decrypted data has an error.

In view of the above, the present invention provides a data writing method, a memory control circuit unit and a memory storage device, which can only read the error checking codes of the sub-data to be merged without reading the sub-data to be merged in the process of generating the merged data and the error checking codes corresponding to the merged data. Thereafter, an error check code corresponding to the merged data may be generated from the read error check code. In addition, in the process of generating the merged data, because the invention does not need to read the sub-data to be merged to the buffer memory but directly moves the sub-data in the rewritable nonvolatile memory module to generate the merged data, the problem of generating error bits in the merged data in the prior art can be avoided.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another example embodiment of the present invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIGS. 6A to 6C are schematic diagrams illustrating an example of a data writing method according to an example embodiment of the invention;

FIGS. 7A-7B are diagrams illustrating an example of applying a data writing method to encrypted data according to an example embodiment of the invention;

fig. 8 is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention.

Description of the reference numerals

30. 10: memory storage device

31. 11: host system

110: system bus

111: processor with a memory for storing a plurality of data

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: motherboard with a memory card

201: u disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: error checking and correcting circuit

510: buffer memory

512: power management circuit

DATA1, DATA2: data of

D0 to D3, PT0 to PT3: sub data

L0 to L3: position of

DATA1_0 to DATA1_3, DATA2_0 to DATA2_3, DATA2_0x to DATA2_3x: data after zero padding

P0 to P5, pr0 to Pr4, pr0x to Pr4x: error checking code

PX0 to PX3: cipher text

BS0 to BS5, BSr0 to BSr4: bit sequence

PG0 to PG6: entity page

PG0_ D to PG6_ D: data bit area

PG0_ R to PG6_ R: redundant bit area

MD0 to MD5, MDr0 to MDr4: metadata

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all coupled to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is coupled to the I/O devices 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless manner through the data transmission interface 114. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be coupled to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 may include embedded Multi Media Card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) memory device 342, which may be any type of embedded memory device that directly couples a memory module to a substrate of a host system.

Fig. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used for coupling the memory storage device 10 to the host system 11. In the exemplary embodiment, the connection interface unit 402 conforms to the Peripheral Component Interconnect Express (PCI Express) standard and is compatible with the NVM Express interface standard. In particular, the flash non-volatile memory interface standard is a protocol for communication between a host system and a memory device, which defines a temporary memory interface, an instruction set, and a function set between a controller of the memory storage device and an operating system of the host system, and facilitates data access speed and data transfer rate of the memory storage device based on a PCIe interface by optimizing the interface standard of the memory storage device. However, in other exemplary embodiments, the connection interface unit 402 may conform to other suitable standards. In addition, the connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the bottom-side physical programming cell is faster than that of the top-side physical programming cell, and/or the reliability of the bottom-side physical programming cell is higher than that of the top-side physical programming cell.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, a physically erased cell is the smallest unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is coupled to the memory management circuit 502 and is used for receiving and identifying commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for writing data, a read instruction sequence for reading data, an erase instruction sequence for erasing data, and corresponding instruction sequences for instructing various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequence of instructions may include one or more signals, or data, on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.

The error checking and correcting circuit 508 is coupled to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

The buffer memory 510 is coupled to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

It should be noted that the data writing method of the present invention can be applied to the rewritable nonvolatile memory module 406 that stores data in an encrypted or unencrypted manner. In the following, the first embodiment is described with respect to the rewritable nonvolatile memory module 406 storing non-encrypted data. In the second embodiment, the description is made with respect to the rewritable nonvolatile memory module 406 that stores encrypted data.

[ first embodiment ]

Fig. 6A to 6C are schematic diagrams illustrating an example of a data writing method according to an example embodiment of the invention. For convenience of illustration, it is assumed that a physical page in the rewritable non-volatile memory module 406 has four physical sectors.

Referring to FIG. 6A, it is assumed that a DATA DATA1 (also referred to as a first DATA) includes sub-DATA D0D 3. The size of the DATA1 just fits the size of the DATA bit area of an entity page, and each of the sub-DATA D0 to D3 just fits the size of an entity fan. In the example of FIG. 6A, the sub-data D0-D3 are arranged in a sequence. For example, the sub-data D0 (also referred to as first sub-data) is arranged at a position L0 (also referred to as a first position) in the sequence, the sub-data D1 (also referred to as second sub-data) is arranged at a position L1 (also referred to as a second position) in the sequence, the sub-data D2 is arranged at a position L2 in the sequence, and the sub-data D3 is arranged at a position L3 in the sequence.

Assume that the memory management circuit 502 first obtains the sub-data D0 from the host system 11. The memory management circuit 502 generates an error checking code P0 (also referred to as a first error checking code) corresponding to the sub-data D0 and stores the sub-data D0 and the error checking code P0 into the rewritable nonvolatile memory module 406.

More specifically, the memory management circuit 502 arranges the sub-DATA D0 at the position L0 in the original DATA1, sets a plurality of bits in positions other than the position L0 (i.e., positions L1 to L3) to zero to generate the zero-padded DATA1_0 (also referred to as first zero-padded DATA), and generates the error check code P0 according to the zero-padded DATA1_ 0. It should be noted that the present invention is not limited to the algorithm for generating the error checking code P0. In one embodiment, the error checking code P0 is generated, for example, via a Cyclic Redundancy Check (CRC) algorithm. It should be noted that, for simplicity, only one zero is used for each of the positions L1 to L3 in the zero-padded DATA1_0 in fig. 6A, but in practical cases, a plurality of bits are included in each of the positions L1 to L3 and are set to be zero. A similar representation applies to other zero-padded data.

In addition, the memory management circuit 502 records a bit sequence BS0 (also referred to as a first bit sequence). In the bit sequence BS0, each bit corresponds to one of positions L0 to L3 in the zero-padded DATA1_ 0. The first bit of the bit sequence BS0 corresponds to the position L0 in the DATA1_0 after zero padding, the second bit of the bit sequence BS0 corresponds to the position L1 in the DATA1_0 after zero padding, the third bit of the bit sequence BS0 corresponds to the position L2 in the DATA1_0 after zero padding, and the fourth bit of the bit sequence BS0 corresponds to the position L3 in the DATA1_0 after zero padding. In the present example, since only the position L0 of the zero-padded DATA DATA1_0 stores the DATA D0 and the bits in the positions L1-L3 are all zero, the memory management circuit 502 sets the first bit of the bit sequence BS0 to 1 and sets the second, third and fourth bits to 0.

After obtaining the zero-padded DATA DATA1_0, the error check code P0, and the bit sequence BS0, the memory management circuit 502 stores the zero-padded DATA DATA1_0, the error check code P0, and the bit sequence BS0 into the rewritable nonvolatile memory module 406. For example, the memory management circuit 502 stores the zero-padded DATA1_0 into the DATA bit region PG0_ D of the physical page PG0 and stores the metadata MD0 composed of the error check code P0 and the bit sequence BS0 into the redundant bit region PG0_ R of the physical page PG 0. In particular, in the data bit region PG0_ D of the physical page PG0, the 1 st physical sector is used to store the sub-data D0, and the 2 nd to 4 th physical sectors respectively store data with a value of zero.

After that, it is assumed that the memory management circuit 502 acquires the sub data D1 from the host system 11. The memory management circuit 502 generates an error checking code P1 (also referred to as a second error checking code) corresponding to the sub-data D1 and stores the sub-data D1 and the error checking code P1 into the rewritable nonvolatile memory module 406. Similarly, the memory management circuit 502 arranges the sub-DATA D1 at the position L1 in the original DATA1, sets a plurality of bits in other positions (i.e., the position L0, the positions L2 to L3) except the position L1 to zero to generate the zero-padded DATA1_1 (also referred to as the second zero-padded DATA), and generates the error check code P1 according to the zero-padded DATA1_ 1.

In addition, the memory management circuit 502 records a bit sequence BS1 (also referred to as a second bit sequence) corresponding to the error check code P1. In the bit sequence BS 1. In this example, since only the location L1 of the DATA DATA1_1 stores the DATA D1 after zero padding and the bits at the locations L0 and L2-L3 are all zero, the memory management circuit 502 sets the 2 nd bit of the bit sequence BS1 to 1 and sets the 1 st, 3 rd, and 4 th bits to 0.

After obtaining the zero-padded DATA1_1, the error check code P1, and the bit sequence BS1, the memory management circuit 502 stores the zero-padded DATA1_1, the error check code P1, and the bit sequence BS1 into the rewritable nonvolatile memory module 406. For example, the memory management circuit 502 stores the zero-padded DATA1_1 into the DATA bit region PG1_ D of the physical page PG1 and stores the metadata MD1 composed of the error check code P1 and the bit sequence BS1 into the redundant bit region PG1_ R of the physical page PG 1. In particular, in the data bit region PG1_ D of the physical page PG1, the 2 nd physical sector is used to store the sub data D1, and the 1 st, 3 rd and 4 th physical sectors respectively store data with a value of zero.

In one embodiment, it is assumed that the memory management circuit 502 needs to combine the sub data D0 in the physical page PG0 and the sub data D1 in the physical page PG 1. Referring to fig. 6B, the memory management circuit 502 can obtain the 1 st physical sector memory sub-data D0 in the physical page PG0 according to the bit sequence BS0 in the metadata MD 0. The memory management circuit 502 can know the 2 nd entity fan memory sub data D1 in the entity page PG1 according to the bit sequence BS1 in the metadata MD 1. Therefore, the memory management circuit 502 may copy the sub data D0 from the 1 st physical fan in the physical page PG0 to the 1 st physical fan in the physical page PG4 and copy the sub data D1 from the 2 nd physical fan in the physical page PG1 to the 2 nd physical fan in the physical page PG4, for example. And the 3 rd and 4 th entity sectors in the entity page PG4 respectively store data with a value of zero. It should be noted that, in the process of merging the sub-data D0 to D1, the data in the rewritable nonvolatile memory module 406 can be directly operated without reading the data from the rewritable nonvolatile memory module 406 to the buffer memory 510 and then writing the data back to the rewritable nonvolatile memory module 406. For convenience of explanation, the data stored in the data bit area PG1_ D of the entity page PG4 (i.e., the merged data generated after merging the sub data D0 to D1) may be referred to as "second data" herein.

In particular, in the present embodiment, the memory management circuit 502 also reads the error check codes P0 to P1 and the bit sequences BS0 to BS1 in the metadata MD0 to MD1 into the buffer memory 510. Thereafter, the memory management circuit 502 performs exclusive-or operation on the error check code P0 and the error check code P1 to obtain an error check code P4 (also referred to as a third error check code). Specifically, the error check code P4 is used to check whether there is an error bit in the aforementioned "second data".

In addition, the memory management circuit 502 may also perform exclusive or operation on the bit sequence BS0 and the bit sequence BS1 to obtain a bit sequence BS4 (also referred to as a third bit sequence). In the embodiment, after performing exclusive-or operation, the 1 st and 2 nd bits of the bit sequence BS4 are set to 1 and the 3 rd and 4 th bits are set to 0.

After obtaining the error check code P4 and the bit sequence BS4, the memory management circuit 502 stores the metadata MD4 composed of the error check code P4 and the bit sequence BS4 into the redundant bit region PG4_ R of the physical page PG 4.

Referring to FIG. 6A again, in another embodiment, it is assumed that the memory management circuit 502 writes the sub-data D0D 1 into the physical pages PG0 PG1 respectively before performing the data merging operation shown in FIG. 6B on the sub-data D0D 1. Assuming that the memory management circuit 502 obtains the sub-DATA D2 from the host system 11, the memory management circuit 502 generates the error check code P2 and the bit sequence BS2 corresponding to the zero-padded DATA1_2 of the sub-DATA D2 in a similar manner as described above. The memory management circuit 502 stores the zero-padded DATA1_2 into the DATA bit region PG2_ D of the physical page PG2 and stores the metadata MD2 composed of the error check code P2 and the bit sequence BS2 into the redundant bit region PG2_ R of the physical page PG 2.

Similarly, assuming that the memory management circuit 502 obtains the sub-DATA D3 from the host system 11, the memory management circuit 502 generates the error check code P3 and the bit sequence BS3 corresponding to the zero-padded DATA1_3 of the sub-DATA D3 in a similar manner as described above. The memory management circuit 502 stores the zero-padded DATA1_3 into the DATA bit region PG3_ D of the physical page PG3 and stores the metadata MD3 composed of the error check code P3 and the bit sequence BS3 into the redundant bit region PG3_ R of the physical page PG 3.

Then, referring to fig. 6A and fig. 6C, it is assumed that the memory management circuit 502 needs to combine the sub data D0 in the physical page PG0, the sub data D1 in the physical page PG1, the sub data D2 in the physical page PG2, and the sub data D3 in the physical page PG 3. The memory management circuit 502 may copy the sub data D0 from the 1 st entity fan in the entity page PG0 to the 1 st entity fan in the entity page PG5, copy the sub data D1 from the 2 nd entity fan in the entity page PG1 to the 2 nd entity fan in the entity page PG5, copy the sub data D2 from the 3 rd entity fan in the entity page PG2 to the 3 rd entity fan in the entity page PG5, and copy the sub data D3 from the 4 th entity fan in the entity page PG3 to the 4 th entity fan in the entity page PG5, in a manner similar to fig. 6B.

In particular, in the present embodiment, the memory management circuit 502 also reads the error check codes P0 to P3 and the bit sequences BS0 to BS3 from the metadata MD0 to MD3 into the buffer memory 510. Then, the memory management circuit 502 performs exclusive-OR operation on the error check codes P0-P3 to obtain the error check code P5. Specifically, the error check code P5 is used to check whether the stored data (i.e., the merged data of the sub-data D0 to D3) stored in the data bit area PG5_ D of the real page PG5 has an error bit.

In addition, the memory management circuit 502 performs exclusive-or operation on the bit sequences BS0 to BS3 to obtain the bit sequence BS5. After obtaining the error check code P5 and the bit sequence BS5, the memory management circuit 502 stores the metadata MD5 composed of the error check code P5 and the bit sequence BS5 into the redundant bit region PG4_ R of the physical page PG 5.

[ second embodiment ]

The second embodiment of the present invention is to apply the data writing method of the present invention to the rewritable nonvolatile memory module 406 that stores encrypted data.

Fig. 7A to 7B are schematic diagrams illustrating an example of applying a data writing method to encrypted data according to an example embodiment of the present invention.

Referring to FIG. 7A to FIG. 7B, it is assumed that a DATA DATA2 includes the sub-DATA PT0 PT3 that has not been encrypted. That is, the sub-data PT0 PT3 are all "plaintext". The size of the DATA2 exactly corresponds to the size of the DATA bit area of an entity page, and each of the sub-DATA PT0 to PT3 exactly corresponds to the size of an entity sector. In the example of FIG. 7A, the sub-data PT0 PT3 are arranged in an order. For example, the sub-data PT0 (also referred to as a first plaintext) is arranged at a position L0 (also referred to as a first position) in the order, the sub-data PT1 (also referred to as a second plaintext) is arranged at a position L1 (also referred to as a second position) in the order, the sub-data PT2 is arranged at a position L2 in the order, and the sub-data PT3 is arranged at a position L3 in the order.

It is assumed that the memory management circuit 502 first obtains the sub data PT0 from the host system 11. The memory management circuit 502 generates an error checking code Pr0 (also referred to as a first plaintext error checking code) corresponding to the sub-data PT0. In detail, similar to the first embodiment, the memory management circuit 502 configures the sub-DATA PT0 at the position L0 in the original DATA2, sets a plurality of bits in other positions (i.e., the positions L1 to L3) except the position L0 to zero to generate the zero-padded DATA2_0, and generates the error check code Pr0 according to the zero-padded DATA2_ 0. Specifically, the error check code Pr0 is used to check whether the DATA2_0 after zero padding contains an error bit.

In the embodiment of fig. 7A, the memory management circuit 502 encrypts the sub-DATA PT0 to generate a corresponding ciphertext PX0 (also referred to as a first ciphertext), the memory management circuit 502 configures the ciphertext PX0 at position L0, sets a plurality of bits in positions other than position L0 (i.e., positions L1-L3) to zero to generate the zero-padded DATA2_0x, and generates the error check code Pr0x (also referred to as a first error check code) according to the zero-padded DATA2_0 x. Specifically, the error check code Pr0x is used to check whether the DATA2_0x contains error bits after zero padding.

In addition, the memory management circuit 502 records a bit sequence BSr0 (also referred to as a first bit sequence). In the bit sequence BS0, the first bit of the bit sequence BS0 is set to 1 and the second, third and fourth bits are set to 0.

After obtaining the zero-padded DATA DATA2_0x, the error check code Pr0x, and the bit sequence BSr0, the memory management circuit 502 stores the zero-padded DATA DATA2_0x and the metadata MDr0 composed of the error check code Pr0, the error check code Pr0x, and the bit sequence BSr0 into the rewritable nonvolatile memory module 406.

It is assumed that in another embodiment, the memory management circuit 502 further retrieves the sub-data PT1 from the host system 11. Similarly to the above, the memory management circuit 502 arranges the sub-DATA PT1 (also referred to as the second plaintext) at the position L1 in the original DATA2, sets a plurality of bits in other positions (i.e., the position L0, the positions L2 to L3) except the position L1 to zero to generate the zero-padded DATA2_1, and generates the error check code Pr1 according to the zero-padded DATA2_ 1.

Then, the memory management circuit 502 encrypts the sub-DATA PT1 to generate a corresponding ciphertext PX1 (also referred to as a second ciphertext), and the memory management circuit 502 arranges the ciphertext PX0 at the position L1, sets a plurality of bits in positions other than the position L1 (i.e., the positions L0, L2 to L3) to zero to generate the zero-padded DATA2_1x, and generates the error check code Pr1x according to the zero-padded DATA2_ 1x. Specifically, the error check code Pr1x is used to check whether the DATA2_1x contains error bits after zero padding.

In addition, the memory management circuit 502 records a bit sequence BSr1. In the bit sequence BSr1, the 2 nd bit of the bit sequence BSr1 is set to 1 and the 1 st, 3 rd, and 4 th bits are set to 0.

After obtaining the zero-padded DATA DATA2_1x, the error check code Pr1x, and the bit sequence BSr1, the memory management circuit 502 stores the zero-padded DATA DATA2_1x and the metadata MDr1 composed of the error check code Pr1, the error check code Pr1x, and the bit sequence BSr1 into the rewritable nonvolatile memory module 406.

Then, it is assumed that the memory management circuit 502 sequentially obtains the sub-data PT2 and PT3 from the host system 11. The memory management circuit 502 can obtain the zero-padded DATA2_2x, the error check code Pr2x and the bit sequence BSr2 corresponding to the sub-DATA PT2 in a manner similar to that described above, and store the zero-padded DATA2_2x and the metadata MDr2 consisting of the error check code Pr2, the error check code Pr2x and the bit sequence BSr2 into the rewritable nonvolatile memory module 406. Similarly, the memory management circuit 502 obtains the zero-padded DATA2_3x, the error check code Pr3x and the bit sequence BSr3 corresponding to the sub-DATA PT3 in a manner similar to that described above, and stores the zero-padded DATA2_3x and the metadata MDr3 consisting of the error check code Pr3, the error check code Pr3x and the bit sequence BSr3 into the rewritable nonvolatile memory module 406.

Referring to fig. 7A and 7B, it is assumed that the memory management circuit 502 needs to merge the ciphertexts PX 0-PX 3 that have been stored in the rewritable nonvolatile memory module 406 in the example of fig. 7A. The memory management circuit 502 may copy the ciphertext PX0 from the physical page storing the zero-padded DATA2_0x to the 1 st physical sector in the physical page PG6, copy the ciphertext PX1 from the physical page storing the zero-padded DATA2_1x to the 2 nd physical sector in the physical page PG6, copy the ciphertext PX2 from the physical page storing the zero-padded DATA2_2x to the 3 rd physical sector in the physical page PG6, and copy the ciphertext PX3 from the physical page storing the zero-padded DATA2_3x to the 4 th physical sector in the physical page PG 6.

In particular, in the embodiment, the memory management circuit 502 also reads the error check codes Pr0 to Pr3, the error check codes Pr0x to Pr3x, and the bit sequences BSr0 to BSr3 from the metadata MDr0 to MDr3 into the buffer memory 510. Thereafter, the memory management circuit 502 performs exclusive-OR operation on the error checking codes Pr0 to Pr3 to obtain the error checking code Pr4, and performs exclusive-OR operation on the error checking codes Pr0x to Pr3x to obtain the error checking code Pr4x. In addition, the memory management circuit 502 performs exclusive or operation on the bit sequences BSr0 to BSr3 to obtain the bit sequence BSr4. After obtaining the error check code Pr4, the error check code Pr4x, and the bit sequence BSr4, the memory management circuit 502 stores the metadata MDr4 composed of the error check code Pr4, the error check code Pr4x, and the bit sequence BSr4 into the redundant bit region PG6_ R of the physical page PG 6.

It should be noted that, as can be seen from the contents of fig. 7A and 7B, the data stored in the rewritable nonvolatile memory module 406 can be divided into "data that is not merged" and "merged data". Taking fig. 7A as an example, the rewritable nonvolatile memory module 406 stores the ciphertexts PX0 to PX3 that have not been merged, and the ciphertexts PX0 to PX3 that are dispersedly stored in different physical pages are "data that have not been merged". Taking fig. 7B as an example, the entity page PG6 of the rewritable nonvolatile memory module 406 stores the merged ciphertext data PX0 to PX3, and the ciphertext data PX0 to PX3 that are merged and stored in the same entity page are "merged data".

In one embodiment, referring to FIG. 7A again, it is assumed that the memory management circuit 502 wants to read the rewritable nonvolatile memory module 406 to obtain the sub-data PT0 that has not been merged. The memory management circuit 502 can read the physical page storing the zero-padded DATA2_0x from the rewritable nonvolatile memory module 406 to obtain read DATA, and decrypt the read DATA to obtain decrypted DATA. Thereafter, the memory management circuit 502 can verify whether the decrypted DATA (e.g., the zero-padded DATA2_ 0) obtained after decryption contains an error bit with the error check code Pr0. If no error bit is contained, the memory management circuit 502 may output the obtained decrypted data to the host system 11.

In one embodiment, referring to FIG. 7B again, it is assumed that the memory management circuit 502 is about to read the rewritable nonvolatile memory module 406 to obtain the merged sub-data PT0 PT3. The memory management circuit 502 may read the merged encrypted DATA (i.e., the stored ciphertexts PX0 to PX3 that are merged) from the DATA bit area PG6_ D of the entity page PG6 and decrypt the merged encrypted DATA to obtain the DATA2 of fig. 7A that contains the sub-DATA PT0 to PT3. Thereafter, the memory management circuit 502 can verify whether the DATA2_0 obtained after decryption contains an error bit with the error check code Pr 4.

It should be noted that the error check code Pr4x is used to check whether the merged encrypted data (i.e., the merged ciphertexts PX 0-PX 3) stored in the data bit area PG6_ D of the physical page PG6 has error bits. However, based on the characteristics of the data encryption algorithm, when the encrypted data merged in the data bit region PG6_ D of the physical page PG6 is decrypted to obtain a plaintext, the error check code Pr4 (also referred to as a third plaintext error check code) may not be able to effectively check the error bit for the plaintext, and a check failure may occur.

Therefore, in the present embodiment, when the memory management circuit 502 reads the data bit region PG6_ D of the physical page PG6 to obtain read data stored in the form of ciphertext, the memory management circuit 502 decrypts the read data to obtain decrypted data (i.e., plaintext), and verifies the decrypted data according to the error check code Pr 4.

When the decrypted data fails to be verified according to the error check code Pr4, it represents that the read data may belong to "merged data". At this time, the memory management circuit 502 re-encrypts the decrypted data to obtain an encrypted data, and generates a new error check code according to the encrypted data. Thereafter, the memory management circuit 502 determines whether the new ECC is identical to the ECC Pr4x. When the new error checking code is the same as the error checking code Pr4x, the memory management circuit 502 determines that the decrypted data has no error and can output the decrypted data to the host system 11. When the new ECC is different from the ECC Pr4x, the memory management circuit 502 determines that the decrypted data has errors.

Fig. 8 is a flowchart illustrating a data writing method according to an example embodiment of the present invention.

Referring to fig. 8, in step S801, the memory management circuit 502 receives a first sub-data of the plurality of sub-data of the first data and generates a first error check code corresponding to the first sub-data. In step S803, the memory management circuit 502 receives second sub data of the plurality of sub data of the first data, and generates a second error check code corresponding to the second sub data. In step S805, the memory management circuit 502 combines the first error check code and the second error check code to obtain a third error check code. The third error checking code is used for checking whether the second data formed by combining the first subdata and the second subdata has errors. In step S807, the memory management circuit 502 stores the second data and the third error checking code into the rewritable nonvolatile memory module 406.

In summary, the data writing method, the memory control circuit unit and the memory storage device of the present invention can only read the error checking code of the sub-data to be merged without reading the sub-data to be merged to the buffer memory in the process of generating the merged data and the error checking code corresponding to the merged data. Thereafter, an error check code corresponding to the merged data may be generated from the read error check code. In addition, in the process of generating the merged data, because the invention does not need to read the sub data to be merged to the buffer memory but directly moves the sub data in the rewritable nonvolatile memory module to generate the merged data, the problem of generating error bits in the merged data in the prior art can be avoided.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data writing method is used for a rewritable nonvolatile memory module, and comprises the following steps:

receiving first subdata in a plurality of subdata of first data, wherein the subdata are arranged at a plurality of positions in sequence, and the first subdata is positioned at a first position in the plurality of positions;

configuring the first subdata at the first position and setting bits in other positions except the first position to be zero to generate first zero-padded data;

generating a first error check code according to the first zero-padded data;

storing the first zero-padded data and the first error check code to a first entity page of the rewritable nonvolatile memory module;

receiving second sub data of a plurality of sub data of the first data, the second sub data being located at a second location among the plurality of locations;

configuring the second subdata at the second position and setting bits in other positions except the second position as zero to generate second zero-padded data;

generating a second error check code according to the second zero-padded data;

storing the second zero-padded data and the second error check code to a second entity page of the rewritable nonvolatile memory module;

copying the first subdata in the first entity page to a third entity page of the rewritable non-volatile memory module and copying the second subdata in the second entity page to the third entity page;

combining the first error check code and the second error check code to obtain a third error check code, wherein the third error check code is used to check whether second data combined by the first subdata and the second subdata in the third physical page has an error; and

storing the third error check code in the third physical page.

2. The data writing method according to claim 1, further comprising:

recording a first bit sequence corresponding to the first zero-padded data, wherein bits corresponding to the first position in the first bit sequence are represented by a first numerical value and bits corresponding to positions other than the first position are represented by a second numerical value; and

recording a second bit sequence corresponding to the second zero-padded data, wherein bits corresponding to the second position in the second bit sequence are represented by the first numerical value and bits corresponding to positions other than the second position are represented by the second numerical value.

3. The data writing method according to claim 2, wherein the step of combining the first error check code and the second error check code to obtain the third error check code comprises:

performing exclusive-OR operation according to the first error check code and the second error check code to obtain the third error check code, and recording a third bit sequence corresponding to the second data,

wherein bits corresponding to the first and second positions in the third bit sequence are represented by the first numerical value and bits corresponding to positions other than the first and second positions are represented by the second numerical value.

4. The data writing method according to claim 1,

wherein combining the first error check code and the second error check code to obtain the third error check code comprises:

reading the first error check code from the first physical page and combining the first error check code and the second error check code to obtain the third error check code.

5. The data writing method according to claim 4, wherein a size of the first data conforms to a size of the third physical page, the plurality of sub-data of the first data are sequentially arranged at a plurality of positions of the third physical page, the first sub-data are located at the first position among the plurality of positions, the second sub-data are located at the second position among the plurality of positions,

wherein the data writing method further comprises:

and storing the second sub data to the third entity page so that the first sub data and the second sub data in the third entity page form the second data, wherein the first sub data is located at the first position and the second sub data is located at the second position in the third entity page.

6. The data writing method according to claim 1, wherein the first sub-data is a first cipher text generated by encrypting a first plain text,

wherein the step of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data comprises:

generating a first plaintext error checking code corresponding to the first plaintext, and storing the first ciphertext, the first plaintext error checking code, and the first error checking code in the third physical page.

7. The data writing method according to claim 6, wherein the size of the first data conforms to the size of the third physical page, the plurality of sub-data of the first data are sequentially arranged at a plurality of positions of the third physical page, the first sub-data are located at the first position among the plurality of positions, the second sub-data are located at the second position among the plurality of positions, and the second sub-data are second ciphertext generated by encrypting a second plaintext, the method further comprising:

storing the second ciphertext to the third physical page such that the first ciphertext and the second ciphertext in the third physical page form the second data, wherein the first ciphertext is located at the first position and the second ciphertext is located at the second position in the third physical page.

8. The data writing method of claim 7, further comprising:

combining the first plaintext error check code with a second plaintext error check code corresponding to the second plaintext to obtain a third plaintext error check code; and

storing the third plaintext error check code into the third physical page.

9. The data writing method according to claim 8, further comprising:

reading the third entity page to obtain read data, decrypting the read data to obtain decrypted data, and verifying the decrypted data according to the third plaintext error check code;

when the decrypted data is verified to be failed according to the third plaintext error check code, encrypting the decrypted data to obtain encrypted data, and generating a new error check code according to the encrypted data;

determining whether the new error check code is the same as the third error check code;

when the new error check code is the same as the third error check code, judging that the decrypted data has no error; and

and when the new error check code is different from the third error check code, judging that the decrypted data has errors.

10. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for coupling to a host system;

a memory interface to couple to the rewritable non-volatile memory module;

memory management circuitry coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to receive a first sub-data of a plurality of sub-data of a first data, wherein the plurality of sub-data are sequentially arranged at a plurality of positions, and the first sub-data is located at a first position among the plurality of positions,

wherein the memory management circuit is further configured to configure the first sub-data in the first position and set bits in other positions except the first position to zero to generate first zero-padded data and generate a first error check code according to the first zero-padded data,

wherein the memory management circuit is further configured to store the first zero padded data and the first error check code to a first physical page of the rewritable non-volatile memory module,

wherein the memory management circuit is further configured to receive a second sub-data of the plurality of sub-data of the first data, the second sub-data being located at a second position among the plurality of positions, configure the second sub-data at the second position and set bits in other positions than the second position to zero to generate a second zero-padded data and generate a second error check code according to the second zero-padded data,

wherein the memory management circuit is further configured to store the second zero padded data and the second error check code to a second physical page of the rewritable non-volatile memory module,

wherein the memory management circuit is further configured to copy the first sub-data in the first physical page to a third physical page of the rewritable non-volatile memory module and copy the second sub-data in the second physical page to the third physical page,

wherein the memory management circuit is further configured to combine the first error check code and the second error check code to obtain a third error check code, wherein the third error check code is configured to check whether second data combined by the first sub-data and the second sub-data in the third physical page has an error,

wherein the memory management circuitry is further to store the third error check code into the third physical page.

11. The memory control circuit unit of claim 10, wherein

The memory management circuit is further configured to record a first bit sequence corresponding to the first zero-padded data, wherein bits corresponding to the first position in the first bit sequence are represented by a first numerical value and bits corresponding to positions other than the first position are represented by a second numerical value, an

The memory management circuit is further configured to record a second bit sequence corresponding to the second zero-padded data, wherein bits corresponding to the second position in the second bit sequence are represented by the first numerical value and bits corresponding to positions other than the second position are represented by the second numerical value.

12. The memory control circuitry unit of claim 11, wherein in an operation of combining the first and second error check codes to obtain the third error check code,

the memory management circuit is further configured to perform exclusive-or operation according to the first error check code and the second error check code to obtain the third error check code, and record a third bit sequence corresponding to the second data,

wherein the bits corresponding to the first and second positions in the third bit sequence are represented by the first numerical value and the bits corresponding to positions other than the first and second positions are represented by the second numerical value.

13. The memory control circuit cell of claim 10,

wherein in the operation of combining the first error check code and the second error check code to obtain the third error check code,

the memory management circuitry is also to read the first error check code from the first physical page and combine the first error check code and the second error check code to obtain the third error check code.

14. The memory control circuit unit according to claim 13, wherein a size of the first data conforms to a size of the third physical page, the plurality of sub data of the first data are arranged in order at a plurality of positions of the third physical page, the first sub data are located at the first position among the plurality of positions, the second sub data are located at the second position among the plurality of positions,

the memory management circuit is further configured to store the second sub data to the third physical page, so that the first sub data and the second sub data in the third physical page form the second data, where the first sub data is located at the first position and the second sub data is located at the second position in the third physical page.

15. The memory control circuit unit according to claim 10, wherein the first sub-data is a first cipher text generated by encrypting a first plain text,

wherein in an operation of receiving the first sub-data of the plurality of sub-data of the first data and generating the first error check code corresponding to the first sub-data,

the memory management circuit is further configured to generate a first plaintext error check code corresponding to the first plaintext, and store the first ciphertext, the first plaintext error check code, and the first error check code into the third physical page.

16. The memory control circuit unit according to claim 15, wherein a size of the first data conforms to a size of the third physical page, the plurality of sub-data of the first data are sequentially arranged at a plurality of positions of the third physical page, the first sub-data are located at the first position among the plurality of positions, the second sub-data are located at the second position among the plurality of positions, the second sub-data are a second cipher text generated after encrypting a second plain text, and wherein

The memory management circuitry is further to store the second ciphertext to the third physical page such that the first ciphertext and the second ciphertext in the third physical page form the second data, wherein the first ciphertext is located at the first location and the second ciphertext is located at the second location in the third physical page.

17. The memory control circuit cell of claim 16, wherein

The memory management circuit is further configured to combine the first plaintext error check code with a second plaintext error check code corresponding to the second plaintext to obtain a third plaintext error check code, an

The memory management circuitry is also to store the third plaintext error check code into the third physical page.

18. The memory control circuit unit of claim 17, wherein

The memory management circuit is further configured to read the third physical page to obtain read data, decrypt the read data to obtain decrypted data, and verify the decrypted data according to the third plaintext error check code,

when the decrypted data is verified to be failed according to the third plaintext error check code, the memory management circuit is further used for encrypting the decrypted data to obtain encrypted data and generating a new error check code according to the encrypted data;

the memory management circuit is further configured to determine whether the new error check code is the same as the third error check code,

when the new error check code is the same as the third error check code, the memory management circuit is further configured to determine that there is no error in the decrypted data, an

When the new error check code is different from the third error check code, the memory management circuit is further configured to determine that the decrypted data has an error.

19. A memory device, comprising:

a connection interface unit for coupling to a host system;

a rewritable non-volatile memory module; and

a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to receive first sub data of a plurality of sub data of first data, wherein the plurality of sub data are sequentially arranged at a plurality of positions, the first sub data are located at a first position among the plurality of positions,

wherein the memory control circuit unit is further configured to configure the first sub-data at the first position and set bits in other positions except the first position to zero to generate first zero-padded data and generate a first error check code according to the first zero-padded data,

wherein the memory control circuit unit is further configured to store the first zero padded data and the first error check code to a first physical page of the rewritable non-volatile memory module,

wherein the memory control circuit unit is further configured to receive a second sub-data of the plurality of sub-data of the first data, the second sub-data being located at a second position among the plurality of positions, configure the second sub-data at the second position and set bits in other positions than the second position to zero to generate a second zero-padded data and generate a second error check code according to the second zero-padded data,

wherein the memory control circuit unit is further configured to store the second zero padded data and the second error check code to a second physical page of the rewritable non-volatile memory module,

wherein the memory control circuit unit is further configured to copy the first sub data in the first physical page to a third physical page of the rewritable non-volatile memory module and copy the second sub data in the second physical page to the third physical page,

wherein the memory control circuit unit is further configured to combine the first error check code and the second error check code to obtain a third error check code, wherein the third error check code is configured to check whether second data combined by the first sub data and the second sub data in the third physical page has an error,

wherein the memory control circuitry is further configured to store the third error check code in the third physical page.

20. The memory device of claim 19, wherein

The memory control circuit unit is further configured to record a first bit sequence corresponding to the first zero-padded data, wherein bits corresponding to the first position in the first bit sequence are represented by a first numerical value and bits corresponding to positions other than the first position are represented by a second numerical value, an

The memory control circuit unit is further configured to record a second bit sequence corresponding to the second zero-padded data, wherein bits corresponding to the second position in the second bit sequence are represented by the first numerical value and bits corresponding to positions other than the second position are represented by the second numerical value.

21. The memory device of claim 20, wherein in the combining of the first and second error checking codes to obtain the third error checking code,

the memory control circuit unit is further configured to perform exclusive-or operation according to the first error check code and the second error check code to obtain the third error check code, and record a third bit sequence corresponding to the second data,

22. The storage device as set forth in claim 19,

the memory control circuitry is further configured to read the first error check code from the first physical page and combine the first error check code with the second error check code to obtain the third error check code.

23. The storage device of claim 22, wherein a size of the first data conforms to a size of the third physical page, the plurality of sub-data of the first data are arranged in a plurality of positions in order, the first sub-data are located at the first position among the plurality of positions, the second sub-data are located at the second position among the plurality of positions,

the memory control circuit unit is further configured to store the second sub data to the third physical page, so that the first sub data and the second sub data in the third physical page form the second data, where the first sub data is located at the first position and the second sub data is located at the second position in the third physical page.

24. The storage device according to claim 19, wherein the first sub-data is a first cipher-text generated by encrypting a first plain-text,

the memory control circuit unit is further configured to generate a first plaintext error check code corresponding to the first plaintext, and store the first ciphertext, the first plaintext error check code, and the first error check code into the third physical page.

25. The storage device of claim 24, wherein the size of the first data conforms to the size of the third physical page, the plurality of sub-data of the first data are sequentially arranged at a plurality of positions of the third physical page, the first sub-data are located at the first position in the plurality of positions, the second sub-data are located at the second position in the plurality of positions, the second sub-data are second ciphertext generated by encrypting a second plaintext, and wherein the second ciphertext is generated by encrypting the second plaintext

The memory control circuitry unit is further to store the second ciphertext to the third physical page such that the first ciphertext and the second ciphertext in the third physical page form the second data, wherein the first ciphertext is located at the first position and the second ciphertext is located at the second position in the third physical page.

26. The storage device of claim 25, wherein

The memory control circuit unit is further configured to combine the first plaintext error check code with a second plaintext error check code corresponding to the second plaintext to obtain a third plaintext error check code, an

The memory control circuitry is also to store the third plaintext error check code into the third physical page.

27. The storage device of claim 26, wherein

The memory control circuit unit is further configured to read the third physical page to obtain read data, decrypt the read data to obtain decrypted data, and verify the decrypted data according to the third plaintext error check code,

when the decrypted data is verified to have failed according to the third plaintext error check code, the memory control circuit unit is further configured to encrypt the decrypted data to obtain encrypted data, and generate a new error check code according to the encrypted data,

the memory control circuit unit is further configured to determine whether the new error check code is identical to the third error check code,

when the new error check code is the same as the third error check code, the memory control circuit unit is further configured to determine that there is no error in the decrypted data, an

When the new error check code is different from the third error check code, the memory control circuit unit is further configured to determine that the decrypted data has an error.